1 /*""FILE COMMENT""*******************************************************
2 * System Name	: Timer TMR API for RX62Nxx
3 * File Name		: r_pdl_tmr.h
4 * Version		: 1.02
5 * Contents		: Timer TMR API header
6 * Customer		:
7 * Model			:
8 * Order			:
9 * CPU			: RX
10 * Compiler		: RXC
11 * OS			: Nothing
12 * Programmer	:
13 * Note			:
14 ************************************************************************
15 * Copyright, 2011. Renesas Electronics Corporation
16 * and Renesas Solutions Corporation
17 ************************************************************************
18 * History		: 2011.04.08
19 *				: Ver 1.02
20 *				: CS-5 release.
21 *""FILE COMMENT END""**************************************************/
22 
23 #ifndef R_PDL_TMR_H
24 #define R_PDL_TMR_H
25 
26 #include "r_pdl_common_defs_RX62Nxx.h"
27 
28 /* Function prototypes */
29 bool R_TMR_Set(
30 	uint8_t
31 );
32 bool R_TMR_CreateChannel(
33 	uint8_t,
34 	uint32_t,
35 	uint8_t,
36 	uint8_t,
37 	uint8_t,
38 	uint8_t,
39 	void *,
40 	void *,
41 	void *,
42 	uint8_t
43 );
44 bool R_TMR_CreateUnit(
45 	uint8_t,
46 	uint32_t,
47 	uint8_t,
48 	uint16_t,
49 	uint16_t,
50 	uint16_t,
51 	void *,
52 	void *,
53 	void *,
54 	uint8_t
55 );
56 bool R_TMR_CreatePeriodic(
57 	uint8_t,
58 	uint32_t,
59 	float,
60 	float,
61 	void *,
62 	void *,
63 	uint8_t
64 );
65 bool R_TMR_CreateOneShot(
66 	uint8_t,
67 	uint32_t,
68 	float,
69 	void *,
70 	uint8_t
71 );
72 bool R_TMR_Destroy(
73 	uint8_t
74 );
75 bool R_TMR_ControlChannel(
76 	uint8_t,
77 	uint32_t,
78 	uint8_t,
79 	uint8_t,
80 	uint8_t
81 );
82 bool R_TMR_ControlUnit(
83 	uint8_t,
84 	uint32_t,
85 	uint16_t,
86 	uint16_t,
87 	uint16_t
88 );
89 bool R_TMR_ControlPeriodic(
90 	uint8_t,
91 	uint32_t,
92 	float,
93 	float
94 );
95 bool R_TMR_ReadChannel(
96 	uint8_t,
97 	uint8_t *,
98 	uint8_t *,
99 	uint8_t *,
100 	uint8_t *
101 );
102 bool R_TMR_ReadUnit(
103 	uint8_t,
104 	uint8_t *,
105 	uint16_t *,
106 	uint16_t *,
107 	uint16_t *
108 );
109 
110 /* Pin selection */
111 #define PDL_TMR_PIN_TMR0_A	0x01u
112 #define PDL_TMR_PIN_TMR0_B	0x02u
113 #define PDL_TMR_PIN_TMR1_A	0x04u
114 #define PDL_TMR_PIN_TMR1_B	0x08u
115 #define PDL_TMR_PIN_TMR2_A	0x10u
116 #define PDL_TMR_PIN_TMR2_B	0x20u
117 #define PDL_TMR_PIN_TMR3_A	0x40u
118 #define PDL_TMR_PIN_TMR3_B	0x80u
119 
120 /* Counter clock sources */
121 #define PDL_TMR_CLK_OFF						0x00000001ul
122 #define PDL_TMR_CLK_EXT_RISING				0x00000002ul
123 #define PDL_TMR_CLK_EXT_FALLING				0x00000004ul
124 #define PDL_TMR_CLK_EXT_BOTH				0x00000008ul
125 #define PDL_TMR_CLK_PCLK_DIV_1				0x00000010ul
126 #define PDL_TMR_CLK_PCLK_DIV_2				0x00000020ul
127 #define PDL_TMR_CLK_PCLK_DIV_8				0x00000040ul
128 #define PDL_TMR_CLK_PCLK_DIV_32				0x00000080ul
129 #define PDL_TMR_CLK_PCLK_DIV_64				0x00000100ul
130 #define PDL_TMR_CLK_PCLK_DIV_1024			0x00000200ul
131 #define PDL_TMR_CLK_PCLK_DIV_8192			0x00000400ul
132 #define PDL_TMR_CLK_TMR1_OVERFLOW			0x00000800ul
133 #define PDL_TMR_CLK_TMR3_OVERFLOW			0x00001000ul
134 #define PDL_TMR_CLK_TMR0_CM_A				0x00002000ul
135 #define PDL_TMR_CLK_TMR2_CM_A				0x00004000ul
136 
137 /* A/D trigger control */
138 #define PDL_TMR_ADC_TRIGGER_DISABLE			0x00008000ul
139 #define PDL_TMR_ADC_TRIGGER_ENABLE			0x00010000ul
140 
141 /* Counter clearing options */
142 #define PDL_TMR_CLEAR_DISABLE				0x00020000ul
143 #define PDL_TMR_CLEAR_CM_A					0x00040000ul
144 #define PDL_TMR_CLEAR_CM_B					0x00080000ul
145 #define PDL_TMR_CLEAR_RESET_RISING			0x00100000ul
146 #define PDL_TMR_CLEAR_RESET_HIGH			0x00200000ul
147 
148 /* DTC CMA trigger control */
149 #define PDL_TMR_CM_A_DTC_TRIGGER_DISABLE	0x00400000ul
150 #define PDL_TMR_CM_A_DTC_TRIGGER_ENABLE		0x00800000ul
151 
152 /* DTC CMB trigger control */
153 #define PDL_TMR_CM_B_DTC_TRIGGER_DISABLE	0x01000000ul
154 #define PDL_TMR_CM_B_DTC_TRIGGER_ENABLE		0x02000000ul
155 
156 /* Output control options */
157 #define PDL_TMR_OUTPUT_IGNORE_CM_A	0x01u
158 #define PDL_TMR_OUTPUT_LOW_CM_A		0x02u
159 #define PDL_TMR_OUTPUT_HIGH_CM_A	0x04u
160 #define PDL_TMR_OUTPUT_INV_CM_A		0x08u
161 #define PDL_TMR_OUTPUT_IGNORE_CM_B	0x10u
162 #define PDL_TMR_OUTPUT_LOW_CM_B		0x20u
163 #define PDL_TMR_OUTPUT_HIGH_CM_B	0x40u
164 #define PDL_TMR_OUTPUT_INV_CM_B		0x80u
165 
166 /* Channels and units */
167 #define PDL_TMR_TMR0	0
168 #define PDL_TMR_TMR1	1
169 #define PDL_TMR_TMR2	2
170 #define PDL_TMR_TMR3	3
171 #define PDL_TMR_UNIT0	4
172 #define PDL_TMR_UNIT1	5
173 
174 /* Period or frequency selection */
175 #define PDL_TMR_PERIOD						0x00000001ul
176 #define PDL_TMR_FREQUENCY					0x00000002ul
177 
178 /* Output pin control */
179 #define PDL_TMR_OUTPUT_HIGH					0x00000004ul
180 #define PDL_TMR_OUTPUT_LOW					0x00000008ul
181 #define PDL_TMR_OUTPUT_OFF					0x00000010ul
182 #define PDL_TMR_OUTPUT_ENABLE				0x00000020ul
183 #define PDL_TMR_OUTPUT_DISABLE				0x00000040ul
184 
185 /* ADC trigger control */
186 #define PDL_TMR_ADC_TRIGGER_ON				0x00000080ul
187 #define PDL_TMR_ADC_TRIGGER_OFF				0x00000100ul
188 
189 /* Pulse DTC trigger control */
190 #define PDL_TMR_PULSE_DTC_TRIGGER_DISABLE	0x00000200ul
191 #define PDL_TMR_PULSE_DTC_TRIGGER_ENABLE	0x00000400ul
192 
193 /* Period DTC trigger control */
194 #define PDL_TMR_PERIOD_DTC_TRIGGER_DISABLE	0x00000800ul
195 #define PDL_TMR_PERIOD_DTC_TRIGGER_ENABLE	0x00001000ul
196 
197 /* CPU control */
198 #define PDL_TMR_CPU_ON						0x00002000ul
199 #define PDL_TMR_CPU_OFF						0x00004000ul
200 
201 /* Timer counter control */
202 #define PDL_TMR_STOP						0x00008000ul
203 #define PDL_TMR_START						0x00010000ul
204 
205 /* Register selections */
206 #define PDL_TMR_COUNTER						0x00020000ul
207 #define PDL_TMR_TIME_CONSTANT_A				0x00040000ul
208 #define PDL_TMR_TIME_CONSTANT_B				0x00080000ul
209 
210 #endif
211 /* End of file */
212