1 /* 2 * Copyright (c) 2006-2022, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2009-01-05 Bernard the first version 9 */ 10 11 #ifndef __ENC28J60_H__ 12 #define __ENC28J60_H__ 13 14 #include <rtthread.h> 15 16 // ENC28J60 Control Registers 17 // Control register definitions are a combination of address, 18 // bank number, and Ethernet/MAC/PHY indicator bits. 19 // - Register address (bits 0-4) 20 // - Bank number (bits 5-6) 21 // - MAC/PHY indicator (bit 7) 22 #define ADDR_MASK 0x1F 23 #define BANK_MASK 0x60 24 #define SPRD_MASK 0x80 25 #define ADDR_SHIFT (0) 26 #define BANK_SHIFT (5) 27 #define SPRD_SHIFT (7) 28 // All-bank registers 29 #define EIE 0x1B 30 #define EIR 0x1C 31 #define ESTAT 0x1D 32 #define ECON2 0x1E 33 #define ECON1 0x1F 34 // Bank 0 registers 35 #define ERDPTL (0x00|0x00) 36 #define ERDPTH (0x01|0x00) 37 #define EWRPTL (0x02|0x00) 38 #define EWRPTH (0x03|0x00) 39 #define ETXSTL (0x04|0x00) 40 #define ETXSTH (0x05|0x00) 41 #define ETXNDL (0x06|0x00) 42 #define ETXNDH (0x07|0x00) 43 #define ERXSTL (0x08|0x00) 44 #define ERXSTH (0x09|0x00) 45 #define ERXNDL (0x0A|0x00) 46 #define ERXNDH (0x0B|0x00) 47 #define ERXRDPTL (0x0C|0x00) 48 #define ERXRDPTH (0x0D|0x00) 49 #define ERXWRPTL (0x0E|0x00) 50 #define ERXWRPTH (0x0F|0x00) 51 #define EDMASTL (0x10|0x00) 52 #define EDMASTH (0x11|0x00) 53 #define EDMANDL (0x12|0x00) 54 #define EDMANDH (0x13|0x00) 55 #define EDMADSTL (0x14|0x00) 56 #define EDMADSTH (0x15|0x00) 57 #define EDMACSL (0x16|0x00) 58 #define EDMACSH (0x17|0x00) 59 // Bank 1 registers 60 #define EHT0 (0x00|0x20) 61 #define EHT1 (0x01|0x20) 62 #define EHT2 (0x02|0x20) 63 #define EHT3 (0x03|0x20) 64 #define EHT4 (0x04|0x20) 65 #define EHT5 (0x05|0x20) 66 #define EHT6 (0x06|0x20) 67 #define EHT7 (0x07|0x20) 68 #define EPMM0 (0x08|0x20) 69 #define EPMM1 (0x09|0x20) 70 #define EPMM2 (0x0A|0x20) 71 #define EPMM3 (0x0B|0x20) 72 #define EPMM4 (0x0C|0x20) 73 #define EPMM5 (0x0D|0x20) 74 #define EPMM6 (0x0E|0x20) 75 #define EPMM7 (0x0F|0x20) 76 #define EPMCSL (0x10|0x20) 77 #define EPMCSH (0x11|0x20) 78 #define EPMOL (0x14|0x20) 79 #define EPMOH (0x15|0x20) 80 #define ERXFCON (0x18|0x20) 81 #define EPKTCNT (0x19|0x20) 82 // Bank 2 registers 83 #define MACON1 (0x00|0x40|0x80) 84 #define MACON3 (0x02|0x40|0x80) 85 #define MACON4 (0x03|0x40|0x80) 86 #define MABBIPG (0x04|0x40|0x80) 87 #define MAIPGL (0x06|0x40|0x80) 88 #define MAIPGH (0x07|0x40|0x80) 89 #define MACLCON1 (0x08|0x40|0x80) 90 #define MACLCON2 (0x09|0x40|0x80) 91 #define MAMXFLL (0x0A|0x40|0x80) 92 #define MAMXFLH (0x0B|0x40|0x80) 93 #define MICMD (0x12|0x40|0x80) 94 #define MIREGADR (0x14|0x40|0x80) 95 #define MIWRL (0x16|0x40|0x80) 96 #define MIWRH (0x17|0x40|0x80) 97 #define MIRDL (0x18|0x40|0x80) 98 #define MIRDH (0x19|0x40|0x80) 99 // Bank 3 registers 100 #define MAADR5 (0x00|0x60|0x80) 101 #define MAADR6 (0x01|0x60|0x80) 102 #define MAADR3 (0x02|0x60|0x80) 103 #define MAADR4 (0x03|0x60|0x80) 104 #define MAADR1 (0x04|0x60|0x80) 105 #define MAADR2 (0x05|0x60|0x80) 106 #define EBSTSD (0x06|0x60) 107 #define EBSTCON (0x07|0x60) 108 #define EBSTCSL (0x08|0x60) 109 #define EBSTCSH (0x09|0x60) 110 #define MISTAT (0x0A|0x60|0x80) 111 #define EREVID (0x12|0x60) 112 #define ECOCON (0x15|0x60) 113 #define EFLOCON (0x17|0x60) 114 #define EPAUSL (0x18|0x60) 115 #define EPAUSH (0x19|0x60) 116 // PHY registers 117 #define PHCON1 0x00 118 #define PHSTAT1 0x01 119 #define PHHID1 0x02 120 #define PHHID2 0x03 121 #define PHCON2 0x10 122 #define PHSTAT2 0x11 123 #define PHIE 0x12 124 #define PHIR 0x13 125 #define PHLCON 0x14 126 127 // ENC28J60 ERXFCON Register Bit Definitions 128 #define ERXFCON_UCEN 0x80 129 #define ERXFCON_ANDOR 0x40 130 #define ERXFCON_CRCEN 0x20 131 #define ERXFCON_PMEN 0x10 132 #define ERXFCON_MPEN 0x08 133 #define ERXFCON_HTEN 0x04 134 #define ERXFCON_MCEN 0x02 135 #define ERXFCON_BCEN 0x01 136 // ENC28J60 EIE Register Bit Definitions 137 #define EIE_INTIE 0x80 138 #define EIE_PKTIE 0x40 139 #define EIE_DMAIE 0x20 140 #define EIE_LINKIE 0x10 141 #define EIE_TXIE 0x08 142 #define EIE_WOLIE 0x04 143 #define EIE_TXERIE 0x02 144 #define EIE_RXERIE 0x01 145 // ENC28J60 EIR Register Bit Definitions 146 #define EIR_PKTIF 0x40 147 #define EIR_DMAIF 0x20 148 #define EIR_LINKIF 0x10 149 #define EIR_TXIF 0x08 150 #define EIR_WOLIF 0x04 151 #define EIR_TXERIF 0x02 152 #define EIR_RXERIF 0x01 153 // ENC28J60 ESTAT Register Bit Definitions 154 #define ESTAT_INT 0x80 155 #define ESTAT_LATECOL 0x10 156 #define ESTAT_RXBUSY 0x04 157 #define ESTAT_TXABRT 0x02 158 #define ESTAT_CLKRDY 0x01 159 // ENC28J60 ECON2 Register Bit Definitions 160 #define ECON2_AUTOINC 0x80 161 #define ECON2_PKTDEC 0x40 162 #define ECON2_PWRSV 0x20 163 #define ECON2_VRPS 0x08 164 // ENC28J60 ECON1 Register Bit Definitions 165 #define ECON1_TXRST 0x80 166 #define ECON1_RXRST 0x40 167 #define ECON1_DMAST 0x20 168 #define ECON1_CSUMEN 0x10 169 #define ECON1_TXRTS 0x08 170 #define ECON1_RXEN 0x04 171 #define ECON1_BSEL1 0x02 172 #define ECON1_BSEL0 0x01 173 // ENC28J60 MACON1 Register Bit Definitions 174 #define MACON1_LOOPBK 0x10 175 #define MACON1_TXPAUS 0x08 176 #define MACON1_RXPAUS 0x04 177 #define MACON1_PASSALL 0x02 178 #define MACON1_MARXEN 0x01 179 // ENC28J60 MACON2 Register Bit Definitions 180 #define MACON2_MARST 0x80 181 #define MACON2_RNDRST 0x40 182 #define MACON2_MARXRST 0x08 183 #define MACON2_RFUNRST 0x04 184 #define MACON2_MATXRST 0x02 185 #define MACON2_TFUNRST 0x01 186 // ENC28J60 MACON3 Register Bit Definitions 187 #define MACON3_PADCFG2 0x80 188 #define MACON3_PADCFG1 0x40 189 #define MACON3_PADCFG0 0x20 190 #define MACON3_TXCRCEN 0x10 191 #define MACON3_PHDRLEN 0x08 192 #define MACON3_HFRMLEN 0x04 193 #define MACON3_FRMLNEN 0x02 194 #define MACON3_FULDPX 0x01 195 // ENC28J60 MACON4 Register Bit Definitions 196 #define MACON4_DEFER (1<<6) 197 #define MACON4_BPEN (1<<5) 198 #define MACON4_NOBKOFF (1<<4) 199 // ENC28J60 MICMD Register Bit Definitions 200 #define MICMD_MIISCAN 0x02 201 #define MICMD_MIIRD 0x01 202 // ENC28J60 MISTAT Register Bit Definitions 203 #define MISTAT_NVALID 0x04 204 #define MISTAT_SCAN 0x02 205 #define MISTAT_BUSY 0x01 206 // ENC28J60 PHY PHCON1 Register Bit Definitions 207 #define PHCON1_PRST 0x8000 208 #define PHCON1_PLOOPBK 0x4000 209 #define PHCON1_PPWRSV 0x0800 210 #define PHCON1_PDPXMD 0x0100 211 // ENC28J60 PHY PHSTAT1 Register Bit Definitions 212 #define PHSTAT1_PFDPX 0x1000 213 #define PHSTAT1_PHDPX 0x0800 214 #define PHSTAT1_LLSTAT 0x0004 215 #define PHSTAT1_JBSTAT 0x0002 216 /* ENC28J60 PHY PHSTAT2 Register Bit Definitions */ 217 #define PHSTAT2_TXSTAT (1 << 13) 218 #define PHSTAT2_RXSTAT (1 << 12) 219 #define PHSTAT2_COLSTAT (1 << 11) 220 #define PHSTAT2_LSTAT (1 << 10) 221 #define PHSTAT2_DPXSTAT (1 << 9) 222 #define PHSTAT2_PLRITY (1 << 5) 223 // ENC28J60 PHY PHCON2 Register Bit Definitions 224 #define PHCON2_FRCLINK 0x4000 225 #define PHCON2_TXDIS 0x2000 226 #define PHCON2_JABBER 0x0400 227 #define PHCON2_HDLDIS 0x0100 228 229 // ENC28J60 Packet Control Byte Bit Definitions 230 #define PKTCTRL_PHUGEEN 0x08 231 #define PKTCTRL_PPADEN 0x04 232 #define PKTCTRL_PCRCEN 0x02 233 #define PKTCTRL_POVERRIDE 0x01 234 235 /* ENC28J60 Transmit Status Vector */ 236 #define TSV_TXBYTECNT 0 237 #define TSV_TXCOLLISIONCNT 16 238 #define TSV_TXCRCERROR 20 239 #define TSV_TXLENCHKERROR 21 240 #define TSV_TXLENOUTOFRANGE 22 241 #define TSV_TXDONE 23 242 #define TSV_TXMULTICAST 24 243 #define TSV_TXBROADCAST 25 244 #define TSV_TXPACKETDEFER 26 245 #define TSV_TXEXDEFER 27 246 #define TSV_TXEXCOLLISION 28 247 #define TSV_TXLATECOLLISION 29 248 #define TSV_TXGIANT 30 249 #define TSV_TXUNDERRUN 31 250 #define TSV_TOTBYTETXONWIRE 32 251 #define TSV_TXCONTROLFRAME 48 252 #define TSV_TXPAUSEFRAME 49 253 #define TSV_BACKPRESSUREAPP 50 254 #define TSV_TXVLANTAGFRAME 51 255 256 #define TSV_SIZE 7 257 #define TSV_BYTEOF(x) ((x) / 8) 258 #define TSV_BITMASK(x) (1 << ((x) % 8)) 259 #define TSV_GETBIT(x, y) (((x)[TSV_BYTEOF(y)] & TSV_BITMASK(y)) ? 1 : 0) 260 261 /* ENC28J60 Receive Status Vector */ 262 #define RSV_RXLONGEVDROPEV 16 263 #define RSV_CARRIEREV 18 264 #define RSV_CRCERROR 20 265 #define RSV_LENCHECKERR 21 266 #define RSV_LENOUTOFRANGE 22 267 #define RSV_RXOK 23 268 #define RSV_RXMULTICAST 24 269 #define RSV_RXBROADCAST 25 270 #define RSV_DRIBBLENIBBLE 26 271 #define RSV_RXCONTROLFRAME 27 272 #define RSV_RXPAUSEFRAME 28 273 #define RSV_RXUNKNOWNOPCODE 29 274 #define RSV_RXTYPEVLAN 30 275 276 #define RSV_SIZE 6 277 #define RSV_BITMASK(x) (1 << ((x) - 16)) 278 #define RSV_GETBIT(x, y) (((x) & RSV_BITMASK(y)) ? 1 : 0) 279 280 // SPI operation codes 281 #define ENC28J60_READ_CTRL_REG (0x00) 282 #define ENC28J60_READ_BUF_MEM (0x20 | 0x1A) 283 #define ENC28J60_WRITE_CTRL_REG (0x40) 284 #define ENC28J60_WRITE_BUF_MEM (0x60 | 0x1A) 285 #define ENC28J60_BIT_FIELD_SET (0x80) 286 #define ENC28J60_BIT_FIELD_CLR (0xA0) 287 #define ENC28J60_SOFT_RESET (0xE0 | 0x1F) 288 289 // The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata 290 // buffer boundaries applied to internal 8K ram 291 // the entire available packet buffer space is allocated 292 // 293 294 // start with recbuf at 0/ 295 #define RXSTART_INIT 0x0 296 // receive buffer end 297 #define RXSTOP_INIT (0x1FFF - 0x0600 - 1) 298 // start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes) 299 300 #define TXSTART_INIT (0x1FFF - 0x0600) 301 // stp TX buffer at end of mem 302 #define TXSTOP_INIT 0x1FFF 303 304 // max frame length which the conroller will accept: 305 #define MAX_FRAMELEN 1518 306 307 void rt_hw_enc28j60_init(void); 308 309 #endif 310