1 /* 2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved. 3 * 4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in 5 * the the people's Republic of China and other countries. 6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission. 7 * 8 * DISCLAIMER 9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. 10 * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.) 11 * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN 12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. 13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS 14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE. 15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY. 16 * 17 * 18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT 19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND, 20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING 21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE 22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 30 * OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _AC108_H 34 #define _AC108_H 35 36 /* #include<snd_hal.h> */ 37 #include <sunxi_hal_twi.h> 38 39 /*** AC108 Codec Register Define***/ 40 41 //Chip Reset 42 #define CHIP_AUDIO_RST 0x00 43 44 //Power Control 45 #define PWR_CTRL1 0x01 46 #define PWR_CTRL2 0x02 47 #define PWR_CTRL3 0x03 48 #define PWR_CTRL4 0x04 49 #define PWR_CTRL5 0x05 50 #define PWR_CTRL6 0x06 51 #define PWR_CTRL7 0x07 52 #define PWR_CTRL8 0x08 53 #define PWR_CTRL9 0x09 54 55 //PLL Configure Control 56 #define PLL_CTRL1 0x10 57 #define PLL_CTRL2 0x11 58 #define PLL_CTRL3 0x12 59 #define PLL_CTRL4 0x13 60 #define PLL_CTRL5 0x14 61 #define PLL_CTRL6 0x16 62 #define PLL_CTRL7 0x17 63 #define PLL_LOCK_CTRL 0x18 64 65 //System Clock Control 66 #define SYSCLK_CTRL 0x20 67 #define MOD_CLK_EN 0x21 68 #define MOD_RST_CTRL 0x22 69 #define DSM_CLK_CTRL 0x25 70 71 //I2S Common Control 72 #define I2S_CTRL 0x30 73 #define I2S_BCLK_CTRL 0x31 74 #define I2S_LRCK_CTRL1 0x32 75 #define I2S_LRCK_CTRL2 0x33 76 #define I2S_FMT_CTRL1 0x34 77 #define I2S_FMT_CTRL2 0x35 78 #define I2S_FMT_CTRL3 0x36 79 80 //I2S TX1 Control 81 #define I2S_TX1_CTRL1 0x38 82 #define I2S_TX1_CTRL2 0x39 83 #define I2S_TX1_CTRL3 0x3A 84 #define I2S_TX1_CHMP_CTRL1 0x3C 85 #define I2S_TX1_CHMP_CTRL2 0x3D 86 #define I2S_TX1_CHMP_CTRL3 0x3E 87 #define I2S_TX1_CHMP_CTRL4 0x3F 88 89 //I2S TX2 Control 90 #define I2S_TX2_CTRL1 0x40 91 #define I2S_TX2_CTRL2 0x41 92 #define I2S_TX2_CTRL3 0x42 93 #define I2S_TX2_CHMP_CTRL1 0x44 94 #define I2S_TX2_CHMP_CTRL2 0x45 95 #define I2S_TX2_CHMP_CTRL3 0x46 96 #define I2S_TX2_CHMP_CTRL4 0x47 97 98 //I2S RX1 Control 99 #define I2S_RX1_CTRL1 0x50 100 #define I2S_RX1_CHMP_CTRL1 0x54 101 #define I2S_RX1_CHMP_CTRL2 0x55 102 #define I2S_RX1_CHMP_CTRL3 0x56 103 #define I2S_RX1_CHMP_CTRL4 0x57 104 105 //I2S Loopback Debug 106 #define I2S_LPB_DEBUG 0x58 107 108 //ADC Common Control 109 #define ADC_SPRC 0x60 110 #define ADC_DIG_EN 0x61 111 #define DMIC_EN 0x62 112 #define ADC_DSR 0x63 113 #define ADC_FIR 0x64 114 #define ADC_DDT_CTRL 0x65 115 116 //HPF Control 117 #define HPF_EN 0x66 118 #define HPF_COEF_REGH1 0x67 119 #define HPF_COEF_REGH2 0x68 120 #define HPF_COEF_REGL1 0x69 121 #define HPF_COEF_REGL2 0x6A 122 #define HPF_GAIN_REGH1 0x6B 123 #define HPF_GAIN_REGH2 0x6C 124 #define HPF_GAIN_REGL1 0x6D 125 #define HPF_GAIN_REGL2 0x6E 126 127 //ADC Digital Channel Volume Control 128 #define ADC1_DVOL_CTRL 0x70 129 #define ADC2_DVOL_CTRL 0x71 130 #define ADC3_DVOL_CTRL 0x72 131 #define ADC4_DVOL_CTRL 0x73 132 133 //ADC Digital Mixer Source and Gain Control 134 #define ADC1_DMIX_SRC 0x76 135 #define ADC2_DMIX_SRC 0x77 136 #define ADC3_DMIX_SRC 0x78 137 #define ADC4_DMIX_SRC 0x79 138 139 //ADC Digital Debug Control 140 #define ADC_DIG_DEBUG 0x7F 141 142 //I2S Pad Drive Control 143 #define I2S_DAT_PADDRV_CTRL 0x80 144 #define I2S_CLK_PADDRV_CTRL 0x81 145 146 //Analog PGA Control 147 #define ANA_PGA1_CTRL 0x90 148 #define ANA_PGA2_CTRL 0x91 149 #define ANA_PGA3_CTRL 0x92 150 #define ANA_PGA4_CTRL 0x93 151 152 //MIC Offset Control 153 #define MIC_OFFSET_CTRL1 0x96 154 #define MIC_OFFSET_CTRL2 0x97 155 #define MIC1_OFFSET_STATU1 0x98 156 #define MIC1_OFFSET_STATU2 0x99 157 #define MIC2_OFFSET_STATU1 0x9A 158 #define MIC2_OFFSET_STATU2 0x9B 159 #define MIC3_OFFSET_STATU1 0x9C 160 #define MIC3_OFFSET_STATU2 0x9D 161 #define MIC4_OFFSET_STATU1 0x9E 162 #define MIC4_OFFSET_STATU2 0x9F 163 164 //ADC1 Analog Control 165 #define ANA_ADC1_CTRL1 0xA0 166 #define ANA_ADC1_CTRL2 0xA1 167 #define ANA_ADC1_CTRL3 0xA2 168 #define ANA_ADC1_CTRL4 0xA3 169 #define ANA_ADC1_CTRL5 0xA4 170 #define ANA_ADC1_CTRL6 0xA5 171 #define ANA_ADC1_CTRL7 0xA6 172 173 //ADC2 Analog Control 174 #define ANA_ADC2_CTRL1 0xA7 175 #define ANA_ADC2_CTRL2 0xA8 176 #define ANA_ADC2_CTRL3 0xA9 177 #define ANA_ADC2_CTRL4 0xAA 178 #define ANA_ADC2_CTRL5 0xAB 179 #define ANA_ADC2_CTRL6 0xAC 180 #define ANA_ADC2_CTRL7 0xAD 181 182 //ADC3 Analog Control 183 #define ANA_ADC3_CTRL1 0xAE 184 #define ANA_ADC3_CTRL2 0xAF 185 #define ANA_ADC3_CTRL3 0xB0 186 #define ANA_ADC3_CTRL4 0xB1 187 #define ANA_ADC3_CTRL5 0xB2 188 #define ANA_ADC3_CTRL6 0xB3 189 #define ANA_ADC3_CTRL7 0xB4 190 191 //ADC4 Analog Control 192 #define ANA_ADC4_CTRL1 0xB5 193 #define ANA_ADC4_CTRL2 0xB6 194 #define ANA_ADC4_CTRL3 0xB7 195 #define ANA_ADC4_CTRL4 0xB8 196 #define ANA_ADC4_CTRL5 0xB9 197 #define ANA_ADC4_CTRL6 0xBA 198 #define ANA_ADC4_CTRL7 0xBB 199 200 //GPIO Configure 201 #define GPIO_CFG1 0xC0 202 #define GPIO_CFG2 0xC1 203 #define GPIO_DAT 0xC2 204 #define GPIO_DRV 0xC3 205 #define GPIO_PULL 0xC4 206 #define GPIO_INT_CFG 0xC5 207 #define GPIO_INT_EN 0xC6 208 #define GPIO_INT_STATUS 0xC7 209 210 //Misc 211 #define BGTC_DAT 0xD1 212 #define BGVC_DAT 0xD2 213 #define PRNG_CLK_CTRL 0xDF 214 #define AC108_REG_MAX 0xDF 215 216 217 /*** AC108 Codec Register Bit Define***/ 218 219 /*PWR_CTRL1*/ 220 #define CP12_CTRL 4 221 #define CP12_SENSE_SELECT 3 222 223 /*PWR_CTRL2*/ 224 #define CP12_SENSE_FILT 6 225 #define CP12_COMP_FF_EN 3 226 #define CP12_FORCE_ENABLE 2 227 #define CP12_FORCE_RSTB 1 228 229 /*PWR_CTRL3*/ 230 #define LDO33DIG_CTRL 0 231 232 /*PWR_CTRL6*/ 233 #define LDO33ANA_2XHDRM 2 234 #define LDO33ANA_ENABLE 0 235 236 /*PWR_CTRL7*/ 237 #define VREF_SEL 3 238 #define VREF_FASTSTART_ENABLE 1 239 #define VREF_ENABLE 0 240 241 /*PWR_CTRL9*/ 242 #define VREFP_FASTSTART_ENABLE 7 243 #define VREFP_RESCTRL 5 244 #define VREFP_LPMODE 4 245 #define IGEN_TRIM 1 246 #define VREFP_ENABLE 0 247 248 249 /*PLL_CTRL1*/ 250 #define PLL_IBIAS 4 251 #define PLL_NDET 3 252 #define PLL_LOCKED_STATUS 2 253 #define PLL_COM_EN 1 254 #define PLL_EN 0 255 256 /*PLL_CTRL2*/ 257 #define PLL_PREDIV2 5 258 #define PLL_PREDIV1 0 259 260 /*PLL_CTRL3*/ 261 #define PLL_LOOPDIV_MSB 0 262 263 /*PLL_CTRL4*/ 264 #define PLL_LOOPDIV_LSB 0 265 266 /*PLL_CTRL5*/ 267 #define PLL_POSTDIV2 5 268 #define PLL_POSTDIV1 0 269 270 /*PLL_CTRL6*/ 271 #define PLL_LDO 6 272 #define PLL_CP 0 273 274 /*PLL_CTRL7*/ 275 #define PLL_CAP 6 276 #define PLL_RES 4 277 #define PLL_TEST_EN 0 278 279 /*PLL_LOCK_CTRL*/ 280 #define LOCK_LEVEL1 2 281 #define LOCK_LEVEL2 1 282 #define PLL_LOCK_EN 0 283 284 285 /*SYSCLK_CTRL*/ 286 #define PLLCLK_EN 7 287 #define PLLCLK_SRC 4 288 #define SYSCLK_SRC 3 289 #define SYSCLK_EN 0 290 291 /*MOD_CLK_EN & MOD_RST_CTRL*/ 292 #define I2S 7 293 #define ADC_DIGITAL 4 294 #define MIC_OFFSET_CALIBRATION 1 295 #define ADC_ANALOG 0 296 297 /*DSM_CLK_CTRL*/ 298 #define MIC_OFFSET_DIV 4 299 #define DSM_CLK_SEL 0 300 301 302 /*I2S_CTRL*/ 303 #define BCLK_IOEN 7 304 #define LRCK_IOEN 6 305 #define SDO2_EN 5 306 #define SDO1_EN 4 307 #define TXEN 2 308 #define RXEN 1 309 #define GEN 0 310 311 /*I2S_BCLK_CTRL*/ 312 #define EDGE_TRANSFER 5 313 #define BCLK_POLARITY 4 314 #define BCLKDIV 0 315 316 /*I2S_LRCK_CTRL1*/ 317 #define LRCK_POLARITY 4 318 #define LRCK_PERIODH 0 319 320 /*I2S_LRCK_CTRL2*/ 321 #define LRCK_PERIODL 0 322 323 /*I2S_FMT_CTRL1*/ 324 #define ENCD_SEL 6 325 #define MODE_SEL 4 326 #define TX2_OFFSET 3 327 #define TX1_OFFSET 2 328 #define TX_SLOT_HIZ 1 329 #define TX_STATE 0 330 331 /*I2S_FMT_CTRL2*/ 332 #define SLOT_WIDTH_SEL 4 333 #define SAMPLE_RESOLUTION 0 334 335 /*I2S_FMT_CTRL3*/ 336 #define TX_MLS 7 337 #define SEXT 5 338 #define OUT2_MUTE 4 339 #define OUT1_MUTE 3 340 #define LRCK_WIDTH 2 341 #define TX_PDM 0 342 343 344 /*I2S_TX1_CTRL1*/ 345 #define TX1_CHSEL 0 346 347 /*I2S_TX1_CTRL2*/ 348 #define TX1_CH8_EN 7 349 #define TX1_CH7_EN 6 350 #define TX1_CH6_EN 5 351 #define TX1_CH5_EN 4 352 #define TX1_CH4_EN 3 353 #define TX1_CH3_EN 2 354 #define TX1_CH2_EN 1 355 #define TX1_CH1_EN 0 356 357 /*I2S_TX1_CTRL3*/ 358 #define TX1_CH16_EN 7 359 #define TX1_CH15_EN 6 360 #define TX1_CH14_EN 5 361 #define TX1_CH13_EN 4 362 #define TX1_CH12_EN 3 363 #define TX1_CH11_EN 2 364 #define TX1_CH10_EN 1 365 #define TX1_CH9_EN 0 366 367 /*I2S_TX1_CHMP_CTRL1*/ 368 #define TX1_CH4_MAP 6 369 #define TX1_CH3_MAP 4 370 #define TX1_CH2_MAP 2 371 #define TX1_CH1_MAP 0 372 373 /*I2S_TX1_CHMP_CTRL2*/ 374 #define TX1_CH8_MAP 6 375 #define TX1_CH7_MAP 4 376 #define TX1_CH6_MAP 2 377 #define TX1_CH5_MAP 0 378 379 /*I2S_TX1_CHMP_CTRL3*/ 380 #define TX1_CH12_MAP 6 381 #define TX1_CH11_MAP 4 382 #define TX1_CH10_MAP 2 383 #define TX1_CH9_MAP 0 384 385 /*I2S_TX1_CHMP_CTRL4*/ 386 #define TX1_CH16_MAP 6 387 #define TX1_CH15_MAP 4 388 #define TX1_CH14_MAP 2 389 #define TX1_CH13_MAP 0 390 391 392 /*I2S_TX2_CTRL1*/ 393 #define TX2_CHSEL 0 394 395 /*I2S_TX2_CHMP_CTRL1*/ 396 #define TX2_CH4_MAP 6 397 #define TX2_CH3_MAP 4 398 #define TX2_CH2_MAP 2 399 #define TX2_CH1_MAP 0 400 401 /*I2S_TX2_CHMP_CTRL2*/ 402 #define TX2_CH8_MAP 6 403 #define TX2_CH7_MAP 4 404 #define TX2_CH6_MAP 2 405 #define TX2_CH5_MAP 0 406 407 /*I2S_TX2_CHMP_CTRL3*/ 408 #define TX2_CH12_MAP 6 409 #define TX2_CH11_MAP 4 410 #define TX2_CH10_MAP 2 411 #define TX2_CH9_MAP 0 412 413 /*I2S_TX2_CHMP_CTRL4*/ 414 #define TX2_CH16_MAP 6 415 #define TX2_CH15_MAP 4 416 #define TX2_CH14_MAP 2 417 #define TX2_CH13_MAP 0 418 419 420 /*I2S_RX1_CTRL1*/ 421 #define RX1_CHSEL 0 422 423 /*I2S_RX1_CHMP_CTRL1*/ 424 #define RX1_CH4_MAP 6 425 #define RX1_CH3_MAP 4 426 #define RX1_CH2_MAP 2 427 #define RX1_CH1_MAP 0 428 429 /*I2S_RX1_CHMP_CTRL2*/ 430 #define RX1_CH8_MAP 6 431 #define RX1_CH7_MAP 4 432 #define RX1_CH6_MAP 2 433 #define RX1_CH5_MAP 0 434 435 /*I2S_RX1_CHMP_CTRL3*/ 436 #define RX1_CH12_MAP 6 437 #define RX1_CH11_MAP 4 438 #define RX1_CH10_MAP 2 439 #define RX1_CH9_MAP 0 440 441 /*I2S_RX1_CHMP_CTRL4*/ 442 #define RX1_CH16_MAP 6 443 #define RX1_CH15_MAP 4 444 #define RX1_CH14_MAP 2 445 #define RX1_CH13_MAP 0 446 447 448 /*I2S_LPB_DEBUG*/ 449 #define I2S_LPB_DEBUG_EN 0 450 451 452 /*ADC_SPRC*/ 453 #define ADC_FS_I2S1 0 454 455 /*ADC_DIG_EN*/ 456 #define DG_EN 4 457 #define ENAD4 3 458 #define ENAD3 2 459 #define ENAD2 1 460 #define ENAD1 0 461 462 /*DMIC_EN*/ 463 #define DMIC2_EN 1 464 #define DMIC1_EN 0 465 466 /*ADC_DSR*/ 467 #define DIG_ADC4_SRS 6 468 #define DIG_ADC3_SRS 4 469 #define DIG_ADC2_SRS 2 470 #define DIG_ADC1_SRS 0 471 472 /*ADC_DDT_CTRL*/ 473 #define ADOUT_DLY_EN 2 474 #define ADOUT_DTS 0 475 476 477 /*HPF_EN*/ 478 #define DIG_ADC4_HPF_EN 3 479 #define DIG_ADC3_HPF_EN 2 480 #define DIG_ADC2_HPF_EN 1 481 #define DIG_ADC1_HPF_EN 0 482 483 484 /*ADC1_DMIX_SRC*/ 485 #define ADC1_ADC4_DMXL_GC 7 486 #define ADC1_ADC3_DMXL_GC 6 487 #define ADC1_ADC2_DMXL_GC 5 488 #define ADC1_ADC1_DMXL_GC 4 489 #define ADC1_ADC4_DMXL_SRC 3 490 #define ADC1_ADC3_DMXL_SRC 2 491 #define ADC1_ADC2_DMXL_SRC 1 492 #define ADC1_ADC1_DMXL_SRC 0 493 494 /*ADC2_DMIX_SRC*/ 495 #define ADC2_ADC4_DMXL_GC 7 496 #define ADC2_ADC3_DMXL_GC 6 497 #define ADC2_ADC2_DMXL_GC 5 498 #define ADC2_ADC1_DMXL_GC 4 499 #define ADC2_ADC4_DMXL_SRC 3 500 #define ADC2_ADC3_DMXL_SRC 2 501 #define ADC2_ADC2_DMXL_SRC 1 502 #define ADC2_ADC1_DMXL_SRC 0 503 504 /*ADC3_DMIX_SRC*/ 505 #define ADC3_ADC4_DMXL_GC 7 506 #define ADC3_ADC3_DMXL_GC 6 507 #define ADC3_ADC2_DMXL_GC 5 508 #define ADC3_ADC1_DMXL_GC 4 509 #define ADC3_ADC4_DMXL_SRC 3 510 #define ADC3_ADC3_DMXL_SRC 2 511 #define ADC3_ADC2_DMXL_SRC 1 512 #define ADC3_ADC1_DMXL_SRC 0 513 514 /*ADC4_DMIX_SRC*/ 515 #define ADC4_ADC4_DMXL_GC 7 516 #define ADC4_ADC3_DMXL_GC 6 517 #define ADC4_ADC2_DMXL_GC 5 518 #define ADC4_ADC1_DMXL_GC 4 519 #define ADC4_ADC4_DMXL_SRC 3 520 #define ADC4_ADC3_DMXL_SRC 2 521 #define ADC4_ADC2_DMXL_SRC 1 522 #define ADC4_ADC1_DMXL_SRC 0 523 524 525 /*ADC_DIG_DEBUG*/ 526 #define ADC_PTN_SEL 0 527 528 529 /*I2S_DAT_PADDRV_CTRL*/ 530 #define TX2_DAT_DRV 4 531 #define TX1_DAT_DRV 0 532 533 /*I2S_CLK_PADDRV_CTRL*/ 534 #define LRCK_DRV 4 535 #define BCLK_DRV 0 536 537 538 /*ANA_PGA1_CTRL*/ 539 #define ADC1_ANALOG_PGA 1 540 #define ADC1_ANALOG_PGA_STEP 0 541 542 /*ANA_PGA2_CTRL*/ 543 #define ADC2_ANALOG_PGA 1 544 #define ADC2_ANALOG_PGA_STEP 0 545 546 /*ANA_PGA3_CTRL*/ 547 #define ADC3_ANALOG_PGA 1 548 #define ADC3_ANALOG_PGA_STEP 0 549 550 /*ANA_PGA4_CTRL*/ 551 #define ADC4_ANALOG_PGA 1 552 #define ADC4_ANALOG_PGA_STEP 0 553 554 555 /*MIC_OFFSET_CTRL1*/ 556 #define MIC_OFFSET_CAL_EN4 3 557 #define MIC_OFFSET_CAL_EN3 2 558 #define MIC_OFFSET_CAL_EN2 1 559 #define MIC_OFFSET_CAL_EN1 0 560 561 /*MIC_OFFSET_CTRL2*/ 562 #define MIC_OFFSET_CAL_GAIN 3 563 #define MIC_OFFSET_CAL_CHANNEL 1 564 #define MIC_OFFSET_CAL_EN_ONCE 0 565 566 /*MIC1_OFFSET_STATU1*/ 567 #define MIC1_OFFSET_CAL_DONE 7 568 #define MIC1_OFFSET_CAL_RUN_STA 6 569 #define MIC1_OFFSET_MSB 0 570 571 /*MIC1_OFFSET_STATU2*/ 572 #define MIC1_OFFSET_LSB 0 573 574 /*MIC2_OFFSET_STATU1*/ 575 #define MIC2_OFFSET_CAL_DONE 7 576 #define MIC2_OFFSET_CAL_RUN_STA 6 577 #define MIC2_OFFSET_MSB 0 578 579 /*MIC2_OFFSET_STATU2*/ 580 #define MIC2_OFFSET_LSB 0 581 582 /*MIC3_OFFSET_STATU1*/ 583 #define MIC3_OFFSET_CAL_DONE 7 584 #define MIC3_OFFSET_CAL_RUN_STA 6 585 #define MIC3_OFFSET_MSB 0 586 587 /*MIC3_OFFSET_STATU2*/ 588 #define MIC3_OFFSET_LSB 0 589 590 /*MIC4_OFFSET_STATU1*/ 591 #define MIC4_OFFSET_CAL_DONE 7 592 #define MIC4_OFFSET_CAL_RUN_STA 6 593 #define MIC4_OFFSET_MSB 0 594 595 /*MIC4_OFFSET_STATU2*/ 596 #define MIC4_OFFSET_LSB 0 597 598 599 /*ANA_ADC1_CTRL1*/ 600 #define ADC1_PGA_BYPASS 7 601 #define ADC1_PGA_BYP_RCM 6 602 #define ADC1_PGA_CTRL_RCM 4 603 #define ADC1_PGA_MUTE 3 604 #define ADC1_DSM_ENABLE 2 605 #define ADC1_PGA_ENABLE 1 606 #define ADC1_MICBIAS_EN 0 607 608 /*ANA_ADC1_CTRL3*/ 609 #define ADC1_ANA_CAL_EN 5 610 #define ADC1_SEL_OUT_EDGE 3 611 #define ADC1_DSM_DISABLE 2 612 #define ADC1_VREFP_DISABLE 1 613 #define ADC1_AAF_DISABLE 0 614 615 /*ANA_ADC1_CTRL6*/ 616 #define PGA_CTRL_TC 6 617 #define PGA_CTRL_RC 4 618 #define PGA_CTRL_I_LIN 2 619 #define PGA_CTRL_I_IN 0 620 621 /*ANA_ADC1_CTRL7*/ 622 #define PGA_CTRL_HI_Z 7 623 #define PGA_CTRL_SHORT_RF 6 624 #define PGA_CTRL_VCM_VG 4 625 #define PGA_CTRL_VCM_IN 0 626 627 628 /*ANA_ADC2_CTRL1*/ 629 #define ADC2_PGA_BYPASS 7 630 #define ADC2_PGA_BYP_RCM 6 631 #define ADC2_PGA_CTRL_RCM 4 632 #define ADC2_PGA_MUTE 3 633 #define ADC2_DSM_ENABLE 2 634 #define ADC2_PGA_ENABLE 1 635 #define ADC2_MICBIAS_EN 0 636 637 /*ANA_ADC2_CTRL3*/ 638 #define ADC2_ANA_CAL_EN 5 639 #define ADC2_SEL_OUT_EDGE 3 640 #define ADC2_DSM_DISABLE 2 641 #define ADC2_VREFP_DISABLE 1 642 #define ADC2_AAF_DISABLE 0 643 644 /*ANA_ADC2_CTRL6*/ 645 #define PGA_CTRL_IBOOST 7 646 #define PGA_CTRL_IQCTRL 6 647 #define PGA_CTRL_OABIAS 4 648 #define PGA_CTRL_CMLP_DIS 3 649 #define PGA_CTRL_PDB_RIN 2 650 #define PGA_CTRL_PEAKDET 0 651 652 /*ANA_ADC2_CTRL7*/ 653 #define AAF_LPMODE_EN 7 654 #define AAF_STG2_IB_SEL 4 655 #define AAFDSM_IB_DIV2 3 656 #define AAF_STG1_IB_SEL 0 657 658 659 /*ANA_ADC3_CTRL1*/ 660 #define ADC3_PGA_BYPASS 7 661 #define ADC3_PGA_BYP_RCM 6 662 #define ADC3_PGA_CTRL_RCM 4 663 #define ADC3_PGA_MUTE 3 664 #define ADC3_DSM_ENABLE 2 665 #define ADC3_PGA_ENABLE 1 666 #define ADC3_MICBIAS_EN 0 667 668 /*ANA_ADC3_CTRL3*/ 669 #define ADC3_ANA_CAL_EN 5 670 #define ADC3_INVERT_CLK 4 671 #define ADC3_SEL_OUT_EDGE 3 672 #define ADC3_DSM_DISABLE 2 673 #define ADC3_VREFP_DISABLE 1 674 #define ADC3_AAF_DISABLE 0 675 676 /*ANA_ADC3_CTRL7*/ 677 #define DSM_COMP_IB_SEL 6 678 #define DSM_OTA_CTRL 4 679 #define DSM_LPMODE 3 680 #define DSM_OTA_IB_SEL 0 681 682 683 /*ANA_ADC4_CTRL1*/ 684 #define ADC4_PGA_BYPASS 7 685 #define ADC4_PGA_BYP_RCM 6 686 #define ADC4_PGA_CTRL_RCM 4 687 #define ADC4_PGA_MUTE 3 688 #define ADC4_DSM_ENABLE 2 689 #define ADC4_PGA_ENABLE 1 690 #define ADC4_MICBIAS_EN 0 691 692 /*ANA_ADC4_CTRL3*/ 693 #define ADC4_ANA_CAL_EN 5 694 #define ADC4_SEL_OUT_EDGE 3 695 #define ADC4_DSM_DISABLE 2 696 #define ADC4_VREFP_DISABLE 1 697 #define ADC4_AAF_DISABLE 0 698 699 /*ANA_ADC4_CTRL6*/ 700 #define DSM_DEMOFF 5 701 #define DSM_EN_DITHER 4 702 #define DSM_VREFP_LPMODE 2 703 #define DSM_VREFP_OUTCTRL 0 704 705 /*ANA_ADC4_CTRL7*/ 706 #define CK8M_EN 5 707 #define OSC_EN 4 708 #define ADC4_CLK_GATING 3 709 #define ADC3_CLK_GATING 2 710 #define ADC2_CLK_GATING 1 711 #define ADC1_CLK_GATING 0 712 713 714 /*GPIO_CFG1*/ 715 #define GPIO2_SELECT 4 716 #define GPIO1_SELECT 0 717 718 /*GPIO_CFG2*/ 719 #define GPIO4_SELECT 4 720 #define GPIO3_SELECT 0 721 722 /*GPIO_DAT*/ 723 #define GPIO4_DAT 3 724 #define GPIO3_DAT 2 725 #define GPIO2_DAT 1 726 #define GPIO1_DAT 0 727 728 /*GPIO_DRV*/ 729 #define GPIO4_DRV 6 730 #define GPIO3_DRV 4 731 #define GPIO2_DRV 2 732 #define GPIO1_DRV 0 733 734 /*GPIO_PULL*/ 735 #define GPIO4_PULL 6 736 #define GPIO3_PULL 4 737 #define GPIO2_PULL 2 738 #define GPIO1_PULL 0 739 740 /*GPIO_INT_CFG*/ 741 #define GPIO4_EINT_CFG 6 742 #define GPIO3_EINT_CFG 4 743 #define GPIO2_EINT_CFG 2 744 #define GPIO1_EINT_CFG 0 745 746 /*GPIO_INT_EN*/ 747 #define GPIO4_EINT_EN 3 748 #define GPIO3_EINT_EN 2 749 #define GPIO2_EINT_EN 1 750 #define GPIO1_EINT_EN 0 751 752 /*GPIO_INT_STATUS*/ 753 #define GPIO4_EINT_STA 3 754 #define GPIO3_EINT_STA 2 755 #define GPIO2_EINT_STA 1 756 #define GPIO1_EINT_STA 0 757 758 759 /*PRNG_CLK_CTRL*/ 760 #define PRNG_CLK_EN 1 761 #define PRNG_CLK_POS 0 762 763 764 765 /*** Some Config Value ***/ 766 767 //[SYSCLK_CTRL]: PLLCLK_SRC 768 #define PLLCLK_SRC_MCLK 0 769 #define PLLCLK_SRC_BCLK 1 770 #define PLLCLK_SRC_GPIO2 2 771 #define PLLCLK_SRC_GPIO3 3 772 773 //[SYSCLK_CTRL]: SYSCLK_SRC 774 #define SYSCLK_SRC_MCLK 0 775 #define SYSCLK_SRC_PLL 1 776 777 //I2S BCLK POLARITY Control 778 #define BCLK_NORMAL_DRIVE_N_SAMPLE_P 0 779 #define BCLK_INVERT_DRIVE_P_SAMPLE_N 1 780 781 //I2S LRCK POLARITY Control 782 #define LRCK_LEFT_LOW_RIGHT_HIGH 0 783 #define LRCK_LEFT_HIGH_RIGHT_LOW 1 784 785 //I2S Format Selection 786 #define PCM_FORMAT 0 787 #define LEFT_JUSTIFIED_FORMAT 1 788 #define RIGHT_JUSTIFIED_FORMAT 2 789 790 //ADC Digital Debug Control 791 #define ADC_PTN_NORMAL 0 792 #define ADC_PTN_0x5A5A5A 1 793 #define ADC_PTN_0x123456 2 794 #define ADC_PTN_ZERO 3 795 #define ADC_PTN_I2S_RX_DATA 4 796 797 //ADC PGA GAIN Control 798 #define ADC_PGA_GAIN_0dB 0 799 #define ADC_PGA_GAIN_MINUS_6dB 1 800 #define ADC_PGA_GAIN_3dB 3 801 #define ADC_PGA_GAIN_4dB 4 802 #define ADC_PGA_GAIN_5dB 5 803 #define ADC_PGA_GAIN_6dB 6 804 #define ADC_PGA_GAIN_7dB 7 805 #define ADC_PGA_GAIN_8dB 8 806 #define ADC_PGA_GAIN_9dB 9 807 #define ADC_PGA_GAIN_10dB 10 808 #define ADC_PGA_GAIN_11dB 11 809 #define ADC_PGA_GAIN_12dB 12 810 #define ADC_PGA_GAIN_13dB 13 811 #define ADC_PGA_GAIN_14dB 14 812 #define ADC_PGA_GAIN_15dB 15 813 #define ADC_PGA_GAIN_16dB 16 814 #define ADC_PGA_GAIN_17dB 17 815 #define ADC_PGA_GAIN_18dB 18 816 #define ADC_PGA_GAIN_19dB 19 817 #define ADC_PGA_GAIN_20dB 20 818 #define ADC_PGA_GAIN_21dB 21 819 #define ADC_PGA_GAIN_22dB 22 820 #define ADC_PGA_GAIN_23dB 23 821 #define ADC_PGA_GAIN_24dB 24 822 #define ADC_PGA_GAIN_25dB 25 823 #define ADC_PGA_GAIN_26dB 26 824 #define ADC_PGA_GAIN_27dB 27 825 #define ADC_PGA_GAIN_28dB 28 826 #define ADC_PGA_GAIN_29dB 29 827 #define ADC_PGA_GAIN_30dB 30 828 829 //AC108 config 830 #define AC108_CHIP_NUM 1 831 #define AC108_NUM_MAX 4 832 833 //0dB~30dB and -6dB, except 1~2dB 834 #define AC108_PGA_GAIN ADC_PGA_GAIN_28dB 835 836 /* for ref channel */ 837 #define AC108_REF_NULL_CHAN \ 838 { .ref_pga = AC108_PGA_GAIN, .ref_channel = 0x0 } 839 840 //[b3]1 [b2]1 [b1]0 [b0]0 -> 0xC 841 #define AC108_REF_CHAN \ 842 { .ref_pga = ADC_PGA_GAIN_10dB, .ref_channel = 0xc } 843 844 #define AC108_CHIP_CFG \ 845 { \ 846 [0] = { .bus = TWI_MASTER_2, .addr = 0x3b, \ 847 .ref_chan = AC108_REF_CHAN, .debug_mode = ADC_PTN_NORMAL }, \ 848 [1] = { .bus = TWI_MASTER_2, .addr = 0x35, \ 849 .ref_chan = AC108_REF_CHAN, .debug_mode = ADC_PTN_NORMAL }, \ 850 [2] = { .bus = TWI_MASTER_0, .addr = 0x3c, \ 851 .ref_chan = AC108_REF_NULL_CHAN, .debug_mode = ADC_PTN_NORMAL }, \ 852 [3] = { .bus = TWI_MASTER_0, .addr = 0x36, \ 853 .ref_chan = AC108_REF_NULL_CHAN, .debug_mode = ADC_PTN_NORMAL }, \ 854 } 855 856 /* 857 *daudio_master(val << 12): 858 * 1: SND_SOC_DAIFMT_CBM_CFM(codec clk & FRM master) 859 * 4: SND_SOC_DAIFMT_CBS_CFS(codec clk & FRM slave) 860 */ 861 #define AC108_DAUDIO_MASTER 4 862 863 /* daudio_format(val << 0): 864 * 1:SND_SOC_DAIFMT_I2S 865 * 2:SND_SOC_DAIFMT_RIGHT_J 866 * 3:SND_SOC_DAIFMT_LEFT_J 867 * 4:SND_SOC_DAIFMT_DSP_A 868 * (pcm. MSB is available on 2nd BCLK rising edge after LRC rising edge) 869 * 5:SND_SOC_DAIFMT_DSP_B 870 * (pcm. MSB is available on 1nd BCLK rising edge after LRC rising edge) 871 */ 872 #define AC108_DAUDIO_FORMAT SND_SOC_DAIFMT_I2S 873 /* 874 *signal_inversion(val << 8): 875 * 1:SND_SOC_DAIFMT_NB_NF(normal bit clock + frame) use 876 * 2:SND_SOC_DAIFMT_NB_IF(normal BCLK + inv FRM) 877 * 3:SND_SOC_DAIFMT_IB_NF(invert BCLK + nor FRM) use 878 * 4:SND_SOC_DAIFMT_IB_IF(invert BCLK + FRM) 879 */ 880 #define AC108_DAUDIO_SIG_INV 1 881 882 //[0]ADC_PTN_NORMAL:ADC normal 883 //[1]ADC_PTN_0x5A5A5A:0x5A5A5A 884 //[2]ADC_PTN_0x123456:0x123456 885 //[3]ADC_PTN_ZERO:0x000000, 886 //[4~7]ADC_PTN_I2S_RX_DATA:I2S_RX_DATA, other:reserved 887 #define AC108_ADC_PATTERN_SEL ADC_PTN_NORMAL 888 889 #define AC108_CHANNELS_MAX 8 890 //16bit or 32bit slot width, other value will be reserved 891 #define AC108_SLOT_WIDTH 32 892 //TX Encoding mode enable 893 #define AC108_ENCODING_EN 0 894 //TX Encoding channel numbers, must be dual, range[1, 16] 895 #define AC108_ENCODING_CH_NUMS 8 896 897 //range[1, 1024], default PCM mode, I2S/LJ/RJ mode shall divide by 2 898 //#define AC108_LRCK_PERIOD (AC108_SLOT_WIDTH * (AC108_ENCODING_EN ? 2 : AC108_CHANNELS_MAX)) 899 #define AC108_LRCK_PERIOD ((AC108_SLOT_WIDTH * (AC108_ENCODING_EN ? 2 : AC108_CHANNELS_MAX))/2) 900 901 struct ref_chip_config { 902 unsigned int ref_pga; 903 unsigned int ref_channel; 904 }; 905 906 struct twi_device { 907 twi_port_t bus; 908 unsigned int addr; 909 unsigned int debug_mode; 910 struct ref_chip_config ref_chan; 911 }; 912 913 struct ac108_param { 914 unsigned int chip_num; 915 struct twi_device twi_dev[AC108_NUM_MAX]; 916 unsigned int pga_gain; 917 uint8_t daudio_master; 918 uint8_t daudio_format; 919 uint8_t signal_inversion; 920 unsigned int lrck_period; 921 unsigned int slot_width; 922 }; 923 924 struct ac108_priv { 925 struct snd_codec *codec; 926 struct ac108_param param; 927 }; 928 929 #endif 930