1 /* 2 ****************************************************************************** 3 * @file System_ACM32F4.h 4 * @version V1.0.0 5 * @date 2020 6 * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Headler File. 7 ****************************************************************************** 8 */ 9 #ifndef __SYSTEM_ACM32F4_H__ 10 #define __SYSTEM_ACM32F4_H__ 11 12 #include "ACM32Fxx_HAL.h" 13 14 /* ================================================================================ */ 15 /* ======================= Use Uart to Debug print ======================== */ 16 /* ================================================================================ */ 17 #define UART_DEBUG_ENABLE 18 19 #ifdef UART_DEBUG_ENABLE 20 #define printfS printf 21 #else 22 #define printfS(format, ...) ((void)0) 23 #endif 24 /* ================================================================================ */ 25 26 #define PLLCLK_SRC_RC4M (0x00) 27 #define PLLCLK_SRC_XTH (0x01) 28 29 #define DEFAULT_SYSTEM_CLOCK (180000000) // system clock frequency, 32M/64M/120M/180M 30 #define PLL_SOURCE_FROM (PLLCLK_SRC_RC4M) 31 32 /* CLK source Index */ 33 #define SYS_CLK_SRC_RCH (0x00) // CLK source from RC64M 34 #define SYS_CLK_SRC_RC32K (0x01) // CLK source from RC32K 35 #define SYS_CLK_SRC_XTH (0x02) // CLK source from XTH 36 #define SYS_CLK_SRC_XTL (0x03) // CLK source from XTL 37 #define SYS_CLK_SRC_PLLCLK (0x04) // CLK source from PLLCLK 38 39 /* APB Frequencey Division */ 40 #define APB_CLK_DIV_0 (0 << 8) 41 #define APB_CLK_DIV_2 (4 << 8) 42 #define APB_CLK_DIV_4 (5 << 8) 43 #define APB_CLK_DIV_8 (6 << 8) 44 #define APB_CLK_DIV_16 (7 << 8) 45 46 /* STOP WAKEUP Sorce */ 47 #define STOP_WAKEUP_GPIO_PIN0 BIT0 48 #define STOP_WAKEUP_GPIO_PIN1 BIT1 49 #define STOP_WAKEUP_GPIO_PIN2 BIT2 50 #define STOP_WAKEUP_GPIO_PIN3 BIT3 51 #define STOP_WAKEUP_GPIO_PIN4 BIT4 52 #define STOP_WAKEUP_GPIO_PIN5 BIT5 53 #define STOP_WAKEUP_GPIO_PIN6 BIT6 54 #define STOP_WAKEUP_GPIO_PIN7 BIT7 55 #define STOP_WAKEUP_GPIO_PIN8 BIT8 56 #define STOP_WAKEUP_GPIO_PIN9 BIT9 57 #define STOP_WAKEUP_GPIO_PIN10 BIT10 58 #define STOP_WAKEUP_GPIO_PIN11 BIT11 59 #define STOP_WAKEUP_GPIO_PIN12 BIT12 60 #define STOP_WAKEUP_GPIO_PIN13 BIT13 61 #define STOP_WAKEUP_GPIO_PIN14 BIT14 62 #define STOP_WAKEUP_GPIO_PIN15 BIT15 63 #define STOP_WAKEUP_PERIPHERAL_LVD BIT16 64 #define STOP_WAKEUP_PERIPHERAL_RTC BIT17 65 #define STOP_WAKEUP_PERIPHERAL_LPUART BIT18 66 #define STOP_WAKEUP_PERIPHERAL_IWDT BIT19 67 #define STOP_WAKEUP_PERIPHERAL_COMP1 BIT20 68 #define STOP_WAKEUP_PERIPHERAL_COMP2 BIT21 69 #define STOP_WAKEUP_RESERVE BIT22 70 #define STOP_WAKEUP_PERIPHERAL_USB BIT23 71 #define STOP_WAKEUP_ALL (0xFFFFFFU) 72 73 #define STANDBY_WAKEUP_PINS 6 74 #define STANDBY_WAKEUP_SOURCE_IO1 BIT0 75 #define STANDBY_WAKEUP_SOURCE_IO2 BIT1 76 #define STANDBY_WAKEUP_SOURCE_IO3 BIT2 77 #define STANDBY_WAKEUP_SOURCE_IO4 BIT3 78 #define STANDBY_WAKEUP_SOURCE_IO5 BIT4 79 #define STANDBY_WAKEUP_SOURCE_IO6 BIT5 80 #define STANDBY_WAKEUP_SOURCE_RTC BIT6 81 #define STANDBY_WAKEUP_SOURCE_ALL 0x7FU 82 83 // sleep/low power mode definition 84 #define STOPENTRY_WFI 0 85 #define STOPENTRY_WFE 1 86 87 #define SLEEPENTRY_WFI 0 88 #define SLEEPENTRY_WFE 1 89 /* 90 * @brief STOP WAKEUP EDGE structures definition 91 */ 92 typedef enum 93 { 94 WAKEUP_RISING = 0, 95 WAKEUP_FALLING = 1, 96 WAKEUP_RISING_FALLING = 2, // 0:rising, 1:falling, 2: rising and falling 97 }STOP_WAKEUP_EDGE; 98 99 typedef enum 100 { 101 FUNC_DISABLE = 0x00U, 102 FUNC_ENABLE = 0x01U, 103 }FUNC_DISABLE_ENABLE; 104 105 typedef enum 106 { 107 RESET_ENABLE_SOURCE_LVD = 0x00U, 108 RESET_ENABLE_SOURCE_WDT = 0x01U, 109 RESET_ENABLE_SOURCE_IWDT = 0x02U, 110 RESET_ENABLE_SOURCE_LOCKUP = 0x03U, 111 }RESET_ENABLE_SOURCE; 112 113 typedef enum 114 { 115 RESET_SOURCE_EFC = 0x00U, 116 RESET_SOURCE_NVIC_RESET = 0x01U, 117 RESET_SOFT_RESET = 0x02U, 118 }RESET_SOURCE; 119 120 /* 121 * @brief Peripheral Reset structures definition 122 */ 123 typedef enum 124 { 125 RST_SPI4 = 38, 126 RST_GPIOEF = 37, 127 RST_SPI3 = 36, 128 RST_UART4 = 35, 129 RST_TIM4 = 34, 130 RST_CAN2 = 33, 131 RST_I2S1 = 32, 132 133 RST_CAN1 = 31, 134 RST_TIM2 = 30, 135 RST_USB = 29, 136 RST_UAC = 28, 137 RST_TIM17 = 27, 138 RST_TIM16 = 26, 139 RST_TIM15 = 25, 140 RST_TIM14 = 24, 141 RST_TIM7 = 23, 142 RST_TIM6 = 22, 143 RST_TIM3 = 21, 144 RST_TIM1 = 20, 145 RST_UART3 = 19, 146 RST_EXTI = 18, 147 RST_OPA = 17, 148 RST_COMP = 16, 149 RST_TKEY = 15, 150 RST_ADC = 14, 151 RST_DAC = 13, 152 RST_DMA = 12, 153 RST_CRC = 11, 154 RST_IWDT = 10, 155 RST_WDT = 9, 156 RST_LPUART = 8, 157 RST_I2C2 = 7, 158 RST_I2C1 = 6, 159 RST_SPI2 = 5, 160 RST_SPI1 = 4, 161 RST_UART2 = 3, 162 RST_UART1 = 2, 163 RST_GPIOCD = 1, 164 RST_GPIOAB = 0, 165 }enum_RST_ID_t; 166 167 /**************** Bit definition for SCU RCR register ***********************/ 168 #define SCU_RCR_SOFT_RST BIT30 169 #define SCU_RCR_EFC_RST BIT29 170 #define SCU_RCR_REMAP_EN BIT16 171 #define SCU_RCR_LOCKRST_EN BIT3 172 #define SCU_RCR_IWDTRST_EN BIT2 173 #define SCU_RCR_WDTRST_EN BIT1 174 #define SCU_RCR_LVDRST_EN BIT0 175 176 /**************** Bit definition for SCU RSR register ***********************/ 177 #define SCU_RSR_RSTFLAG_CLR BIT16 178 #define SCU_RSR_PWRRST_F BIT10 179 #define SCU_RSR_POR12RST_F BIT9 180 #define SCU_RSR_SRST_F BIT8 181 #define SCU_RSR_SRSTNM_F BIT7 182 #define SCU_RSR_EFC_RST_F BIT6 183 #define SCU_RSR_RSTN_F BIT5 184 #define SCU_RSR_SYSREQRST_F BIT4 185 #define SCU_RSR_LOCKRST_F BIT3 186 #define SCU_RSR_IWDTRST_F BIT2 187 #define SCU_RSR_WDTRST_F BIT1 188 #define SCU_RSR_VDLRST_F BIT0 189 190 /**************** Bit definition for SCU IPRST register **********************/ 191 #define SCU_IPRST_UACRST BIT28 192 #define SCU_IPRST_TIM17RST BIT27 193 #define SCU_IPRST_TIM16RST BIT26 194 #define SCU_IPRST_TIM15RST BIT25 195 #define SCU_IPRST_TIM14RST BIT24 196 #define SCU_IPRST_TIM6RST BIT22 197 #define SCU_IPRST_TIM3RST BIT21 198 #define SCU_IPRST_TIM1RST BIT20 199 #define SCU_IPRST_UART3RST BIT19 200 #define SCU_IPRST_EXTIRST BIT18 201 #define SCU_IPRST_OPARST BIT17 202 #define SCU_IPRST_CMPRST BIT16 203 #define SCU_IPRST_TKEYRST BIT15 204 #define SCU_IPRST_ADCRST BIT14 205 #define SCU_IPRST_DMACRST BIT12 206 #define SCU_IPRST_CRCRST BIT11 207 #define SCU_IPRST_IWDTRST BIT10 208 #define SCU_IPRST_WDTRST BIT9 209 #define SCU_IPRST_LPUART BIT8 210 #define SCU_IPRST_I2C2RST BIT7 211 #define SCU_IPRST_I2C1RST BIT6 212 #define SCU_IPRST_SPI2RST BIT5 213 #define SCU_IPRST_SPI1RST BIT4 214 #define SCU_IPRST_UART2RST BIT3 215 #define SCU_IPRST_UART1RST BIT2 216 #define SCU_IPRST_GPIO2RST BIT1 217 #define SCU_IPRST_GPIO1RST BIT0 218 219 /**************** Bit definition for SCU CCR1 register ***********************/ 220 #define SCU_CCR1_SYS_CLK_SEL (BIT2|BIT1|BIT0) 221 #define SCU_CCR1_SYS_PLL (BIT2) 222 223 /**************** Bit definition for SCU CCR2 register ***********************/ 224 #define SCU_CCR2_DIVDONE BIT31 225 #define SCU_CCR2_TKSCLK_SEL BIT16 226 #define SCU_CCR2_FLTCLK_SEL BIT15 227 #define SCU_CCR2_LPUCLK_SEL (BIT14|BIT13) 228 #define SCU_CCR2_LPUARTDIV (BIT12|BIT11) 229 #define SCU_CCR2_PCLKDIV (BIT10|BIT9|BIT8) 230 #define SCU_CCR2_SYSDIV1 (BIT7|BIT6|BIT5|BIT4) 231 #define SCU_CCR2_SYSDIV0 (BIT3|BIT2|BIT1|BIT0) 232 233 /**************** Bit definition for SCU CIR register ***********************/ 234 #define SCU_CIR_RC4MRDYIC BIT21 235 #define SCU_CIR_PLLLOCKIC BIT20 236 #define SCU_CIR_XTHRDYIC BIT19 237 #define SCU_CIR_RCHRDYIC BIT18 238 #define SCU_CIR_XTLRDYIC BIT17 239 #define SCU_CIR_RC32KRDYIC BIT16 240 #define SCU_CIR_RC4MRDYIE BIT13 241 #define SCU_CIR_PLLLOCKIE BIT12 242 #define SCU_CIR_XTHRDYIE BIT11 243 #define SCU_CIR_RCHRDYIE BIT10 244 #define SCU_CIR_XTLRDYIE BIT9 245 #define SCU_CIR_RC32KRDYIE BIT8 246 #define SCU_CIR_RC4MRDYIF BIT5 247 #define SCU_CIR_PLLLOCKIF BIT4 248 #define SCU_CIR_XTHRDYIF BIT3 249 #define SCU_CIR_RCHRDYIF BIT2 250 #define SCU_CIR_XTLRDYIF BIT1 251 #define SCU_CIR_RC32KRDYIF BIT0 252 253 /**************** Bit definition for SCU IPCKENR register ********************/ 254 #define SCU_IPCKENR_ROMCLKEN BIT30 255 #define SCU_IPCKENR_HRNGCLKEN BIT29 256 #define SCU_IPCKENR_AESCLKEN BIT28 257 #define SCU_IPCKENR_TIM17CLKEN BIT27 258 #define SCU_IPCKENR_TIM16CLKEN BIT26 259 #define SCU_IPCKENR_TIM15CLKEN BIT25 260 #define SCU_IPCKENR_TIM14CLKEN BIT24 261 #define SCU_IPCKENR_TIM6CLKEN BIT22 262 #define SCU_IPCKENR_TIM3CLKEN BIT21 263 #define SCU_IPCKENR_TIM1CLKEN BIT20 264 #define SCU_IPCKENR_UART3CLKEN BIT19 265 #define SCU_IPCKENR_OPACLKEN BIT17 266 #define SCU_IPCKENR_CMPCLKEN BIT16 267 #define SCU_IPCKENR_TKEYCLKEN BIT15 268 #define SCU_IPCKENR_ADCCLKEN BIT14 269 #define SCU_IPCKENR_RTCCLKEN BIT13 270 #define SCU_IPCKENR_DMACCLKEN BIT12 271 #define SCU_IPCKENR_CRCCLKEN BIT11 272 #define SCU_IPCKENR_LPUARTCLKEN BIT8 273 #define SCU_IPCKENR_I2C2CLKEN BIT7 274 #define SCU_IPCKENR_I2C1CLKEN BIT6 275 #define SCU_IPCKENR_SPI2CLKEN BIT5 276 #define SCU_IPCKENR_SPI1CLKEN BIT4 277 #define SCU_IPCKENR_UART2CLKEN BIT3 278 #define SCU_IPCKENR_UART1CLKEN BIT2 279 280 /**************** Bit definition for SCU IPCKENR2 register ********************/ 281 #define SCU_IPCKENR2_EFCCLKEN BIT6 282 #define SCU_IPCKENR2_SRAMCLKEN BIT5 283 #define SCU_IPCKENR2_EXTICLKEN BIT4 284 #define SCU_IPCKENR2_IWDTCLKEN BIT3 285 #define SCU_IPCKENR2_WDTCLKEN BIT2 286 #define SCU_IPCKENR2_GPIO2CLKEN BIT1 287 #define SCU_IPCKENR2_GPIO1CLKEN BIT0 288 289 /**************** Bit definition for SCU RCHCR register **********************/ 290 #define SCU_RCHCR_RC4MRDY BIT22 291 #define SCU_RCHCR_RC4M_TRIM (BIT21|BIT20|BIT19|BIT18|BIT17) 292 #define SCU_RCHCR_RC4M_EN BIT16 293 #define SCU_RCHCR_RCHRDY BIT9 294 #define SCU_RCHCR_RCH_DIV BIT8 295 #define SCU_RCHCR_RCH_TRIM (BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1) 296 #define SCU_RCHCR_RCH_EN BIT0 297 298 /**************** Bit definition for SCU RCHCR register **********************/ 299 #define SCU_XTHCR_XTHRDY BIT4 300 #define SCU_XTHCR_XTH_RDYTIME (BIT3|BIT2) 301 #define SCU_XTHCR_XTH_BYP BIT1 302 #define SCU_XTHCR_XTH_EN BIT0 303 #define SCU_XTHCR_READYTIME_1024 0 304 #define SCU_XTHCR_READYTIME_4096 BIT2 305 #define SCU_XTHCR_READYTIME_16384 BIT3 306 #define SCU_XTHCR_READYTIME_32768 (BIT3|BIT2) 307 308 /**************** Bit definition for SCU PLLCR register **********************/ 309 #define SCU_PLLCR_PLL_LOCK_SEL BIT31 310 #define SCU_PLLCR_PLL_FREE_RUN BIT30 311 #define SCU_PLLCR_PLL_LOCK BIT29 312 #define SCU_PLLCR_PLL_RUN_DLY (BIT28|BIT27|BIT26|BIT25|BIT24|BIT23) 313 #define SCU_PLLCR_PLL_UPDATE_EN BIT22 314 #define SCU_PLLCR_PLL_SLEEP BIT21 315 #define SCU_PLLCR_PLL_OD (BIT19|BIT18) 316 #define SCU_PLLCR_PLL_N (BIT15|BIT14) 317 #define SCU_PLLCR_PLL_M (BIT6|BIT5|BIT4|BIT3) 318 #define SCU_PLLCR_PLL_SRC_SEL (BIT2|BIT1) 319 #define SCU_PLLCR_PLL_EN (BIT0) 320 321 /**************** Bit definition for SCU LDOCR register **********************/ 322 #define SCU_LDOCR_LPLDO12_TRIM (BIT28|BIT27|BIT26) 323 #define SCU_LDOCR_LPSTP_SFT BIT25 324 #define SCU_LDOCR_LPLDO12_EN_SFT BIT24 325 #define SCU_LDOCR_MLDO12_LOWP_SFT BIT22 326 #define SCU_LDOCR_MLDO12_LV_SFT (BIT21|BIT20) 327 #define SCU_LDOCR_LDO18A_EN BIT19 328 #define SCU_LDOCR_ANATEST_SEL (BIT18|BIT17|BIT16) 329 #define SCU_LDOCR_LDO18A_TRIM (BIT15|BIT14|BIT13) 330 #define SCU_LDOCR_LDO18_TRIM (BIT12|BIT11|BIT10) 331 #define SCU_LDOCR_LDO18_EN BIT9 332 #define SCU_LDOCR_LDOCTL_SEL BIT8 333 #define SCU_LDOCR_LDO12_TRIM (BIT7|BIT6|BIT5|BIT4) 334 #define SCU_LDOCR_VREF_TRIM (BIT2|BIT1|BIT0) 335 336 /**************** Bit definition for SCU WMR register ***********************/ 337 #define SCU_WMR_RTC_READY BIT6 338 #define SCU_WMR_REMAP_FLAG BIT4 339 #define SCU_WMR_BOOTPIN BIT3 340 341 /**************** Bit definition for SCU CLKOCR register ********************/ 342 #define SCU_CLKOCR_BUZZER2_EN BIT31 343 #define SCU_CLKOCR_BUZZER2_POL BIT30 344 #define SCU_CLKOCR_BUZZER2_DIV (BIT29|BIT28|BIT27|BIT26|BIT25|BIT24) 345 #define SCU_CLKOCR_BUZZER_EN BIT23 346 #define SCU_CLKOCR_BUZZER_POL BIT22 347 #define SCU_CLKOCR_BUZZER_DIV (0x3FFFE0) 348 #define SCU_CLKOCR_CLKOUT_SEL BIT4 349 #define SCU_CLKOCR_CLKTEST_SEL (BIT3|BIT2|BIT1|BIT0) 350 351 /**************** Bit definition for SCU SYSCFG1 register ********************/ 352 #define SCU_SYSCFG1_TIM15_CH2_SEL (BIT25|BIT24) 353 #define SCU_SYSCFG1_TIM15_CH1_SEL (BIT23|BIT22) 354 #define SCU_SYSCFG1_TIM14_CH1_SEL BIT20 355 #define SCU_SYSCFG1_IR_MODE (BIT18|BIT17) 356 #define SCU_SYSCFG1_IR_POL BIT16 357 #define SCU_SYSCFG1_SRAM_PEF BIT8 358 #define SCU_SYSCFG1_LVD_LOCK BIT2 359 #define SCU_SYSCFG1_SRAM_PARITY_LOCK BIT1 360 #define SCU_SYSCFG1_LOCKUP_LOCK BIT0 361 362 /**************** Bit definition for SCU LVDCFG register ********************/ 363 #define SCU_LVDCFG_LVD_VALUE BIT15 364 #define SCU_LVDCFG_LVD_FILTER BIT14 365 #define SCU_LVDCFG_FLT_TIME (BIT11|BIT10|BIT9) 366 #define SCU_LVDCFG_LVD_FLTEN BIT8 367 #define SCU_LVDCFG_LVD_TRIM (BIT4|BIT3|BIT2|BIT1) 368 #define SCU_LVDCFG_LVDEN BIT0 369 370 /**************** Bit definition for SCU STOPCFG register ********************/ 371 #define SCU_STOPCFG_LPLDO12_LV (BIT15|BIT14|BIT13) 372 #define SCU_STOPCFG_TKPCLK_SEL BIT12 373 #define SCU_STOPCFG_PDDS BIT11 374 #define SCU_STOPCFG_TK_LPLDOLV BIT10 375 #define SCU_STOPCFG_LPSTOP BIT9 376 #define SCU_STOPCFG_RCH_DIV_EN BIT8 377 #define SCU_STOPCFG_MLDO12_LOWP BIT6 378 #define SCU_STOPCFG_MLDO12_LV (BIT5|BIT4) 379 #define SCU_STOPCFG_RC64MPDEN BIT3 380 #define SCU_STOPCFG_RTC_WE BIT0 381 382 /************** Bit definition for SCU VECTOROFFSET register *****************/ 383 #define SCU_VECTOROFFSET_VOFFSETEN BIT0 384 385 /**************** Bit definition for SCU PASEL1 register *********************/ 386 #define SCU_PASEL1_PA7_SEL (BIT31|BIT30|BIT29|BIT28) 387 #define SCU_PASEL1_PA6_SEL (BIT27|BIT26|BIT25|BIT24) 388 #define SCU_PASEL1_PA5_SEL (BIT23|BIT22|BIT21|BIT20) 389 #define SCU_PASEL1_PA4_SEL (BIT19|BIT18|BIT17|BIT16) 390 #define SCU_PASEL1_PA3_SEL (BIT15|BIT14|BIT13|BIT12) 391 #define SCU_PASEL1_PA2_SEL (BIT11|BIT10|BIT9|BIT8) 392 #define SCU_PASEL1_PA1_SEL (BIT7|BIT6|BIT5|BIT4) 393 #define SCU_PASEL1_PA0_SEL (BIT3|BIT2|BIT1|BIT0) 394 395 /**************** Bit definition for SCU PASEL2 register *********************/ 396 #define SCU_PASEL2_PA15_SEL (BIT31|BIT30|BIT29|BIT28) 397 #define SCU_PASEL2_PA14_SEL (BIT27|BIT26|BIT25|BIT24) 398 #define SCU_PASEL2_PA13_SEL (BIT23|BIT22|BIT21|BIT20) 399 #define SCU_PASEL2_PA12_SEL (BIT19|BIT18|BIT17|BIT16) 400 #define SCU_PASEL2_PA11_SEL (BIT15|BIT14|BIT13|BIT12) 401 #define SCU_PASEL2_PA10_SEL (BIT11|BIT10|BIT9|BIT8) 402 #define SCU_PASEL2_PA9_SEL (BIT7|BIT6|BIT5|BIT4) 403 #define SCU_PASEL2_PA8_SEL (BIT3|BIT2|BIT1|BIT0) 404 405 /**************** Bit definition for SCU PBSEL1 register *********************/ 406 #define SCU_PBSEL1_PB7_SEL (BIT31|BIT30|BIT29|BIT28) 407 #define SCU_PBSEL1_PB6_SEL (BIT27|BIT26|BIT25|BIT24) 408 #define SCU_PBSEL1_PB5_SEL (BIT23|BIT22|BIT21|BIT20) 409 #define SCU_PBSEL1_PB4_SEL (BIT19|BIT18|BIT17|BIT16) 410 #define SCU_PBSEL1_PB3_SEL (BIT15|BIT14|BIT13|BIT12) 411 #define SCU_PBSEL1_PB2_SEL (BIT11|BIT10|BIT9|BIT8) 412 #define SCU_PBSEL1_PB1_SEL (BIT7|BIT6|BIT5|BIT4) 413 #define SCU_PBSEL1_PB0_SEL (BIT3|BIT2|BIT1|BIT0) 414 415 /**************** Bit definition for SCU PBSEL2 register *********************/ 416 #define SCU_PBSEL2_PB15_SEL (BIT31|BIT30|BIT29|BIT28) 417 #define SCU_PBSEL2_PB14_SEL (BIT27|BIT26|BIT25|BIT24) 418 #define SCU_PBSEL2_PB13_SEL (BIT23|BIT22|BIT21|BIT20) 419 #define SCU_PBSEL2_PB12_SEL (BIT19|BIT18|BIT17|BIT16) 420 #define SCU_PBSEL2_PB11_SEL (BIT15|BIT14|BIT13|BIT12) 421 #define SCU_PBSEL2_PB10_SEL (BIT11|BIT10|BIT9|BIT8) 422 #define SCU_PBSEL2_PB9_SEL (BIT7|BIT6|BIT5|BIT4) 423 #define SCU_PBSEL2_PB8_SEL (BIT3|BIT2|BIT1|BIT0) 424 425 /**************** Bit definition for SCU PASTR register **********************/ 426 #define SCU_PASTR_PA15_STH (BIT31|BIT30) 427 #define SCU_PASTR_PA14_STH (BIT29|BIT28) 428 #define SCU_PASTR_PA13_STH (BIT27|BIT26) 429 #define SCU_PASTR_PA12_STH (BIT25|BIT24) 430 #define SCU_PASTR_PA11_STH (BIT23|BIT22) 431 #define SCU_PASTR_PA10_STH (BIT21|BIT20) 432 #define SCU_PASTR_PA9_STH (BIT19|BIT18) 433 #define SCU_PASTR_PA8_STH (BIT17|BIT16) 434 #define SCU_PASTR_PA7_STH (BIT15|BIT14) 435 #define SCU_PASTR_PA6_STH (BIT13|BIT12) 436 #define SCU_PASTR_PA5_STH (BIT11|BIT10) 437 #define SCU_PASTR_PA4_STH (BIT9|BIT8) 438 #define SCU_PASTR_PA3_STH (BIT7|BIT6) 439 #define SCU_PASTR_PA2_STH (BIT5|BIT4) 440 #define SCU_PASTR_PA1_STH (BIT3|BIT2) 441 #define SCU_PASTR_PA0_STH (BIT1|BIT0) 442 443 /**************** Bit definition for SCU PBSTR register **********************/ 444 #define SCU_PBSTR_PB15_STH (BIT31|BIT30) 445 #define SCU_PBSTR_PB14_STH (BIT29|BIT28) 446 #define SCU_PBSTR_PB13_STH (BIT27|BIT26) 447 #define SCU_PBSTR_PB12_STH (BIT25|BIT24) 448 #define SCU_PBSTR_PB11_STH (BIT23|BIT22) 449 #define SCU_PBSTR_PB10_STH (BIT21|BIT20) 450 #define SCU_PBSTR_PB9_STH (BIT19|BIT18) 451 #define SCU_PBSTR_PB8_STH (BIT17|BIT16) 452 #define SCU_PBSTR_PB7_STH (BIT15|BIT14) 453 #define SCU_PBSTR_PB6_STH (BIT13|BIT12) 454 #define SCU_PBSTR_PB5_STH (BIT11|BIT10) 455 #define SCU_PBSTR_PB4_STH (BIT9|BIT8) 456 #define SCU_PBSTR_PB3_STH (BIT7|BIT6) 457 #define SCU_PBSTR_PB2_STH (BIT5|BIT4) 458 #define SCU_PBSTR_PB1_STH (BIT3|BIT2) 459 #define SCU_PBSTR_PB0_STH (BIT1|BIT0) 460 461 /**************** Bit definition for SCU PCSEL1 register *********************/ 462 #define SCU_PCSEL1_PC7_SEL (BIT31|BIT30|BIT29|BIT28) 463 #define SCU_PCSEL1_PC6_SEL (BIT27|BIT26|BIT25|BIT24) 464 #define SCU_PCSEL1_PC5_SEL (BIT23|BIT22|BIT21|BIT20) 465 #define SCU_PCSEL1_PC4_SEL (BIT19|BIT18|BIT17|BIT16) 466 #define SCU_PCSEL1_PC3_SEL (BIT15|BIT14|BIT13|BIT12) 467 #define SCU_PCSEL1_PC2_SEL (BIT11|BIT10|BIT9|BIT8) 468 #define SCU_PCSEL1_PC1_SEL (BIT7|BIT6|BIT5|BIT4) 469 #define SCU_PCSEL1_PC0_SEL (BIT3|BIT2|BIT1|BIT0) 470 471 /**************** Bit definition for SCU PCSEL2 register *********************/ 472 #define SCU_PCSEL2_PC15_SEL (BIT31|BIT30|BIT29|BIT28) 473 #define SCU_PCSEL2_PC14_SEL (BIT27|BIT26|BIT25|BIT24) 474 #define SCU_PCSEL2_PC13_SEL (BIT23|BIT22|BIT21|BIT20) 475 #define SCU_PCSEL2_PC12_SEL (BIT19|BIT18|BIT17|BIT16) 476 #define SCU_PCSEL2_PC11_SEL (BIT15|BIT14|BIT13|BIT12) 477 #define SCU_PCSEL2_PC10_SEL (BIT11|BIT10|BIT9|BIT8) 478 #define SCU_PCSEL2_PC9_SEL (BIT7|BIT6|BIT5|BIT4) 479 #define SCU_PCSEL2_PC8_SEL (BIT3|BIT2|BIT1|BIT0) 480 481 /**************** Bit definition for SCU PDSEL1 register *********************/ 482 #define SCU_PDSEL1_PD7_SEL (BIT31|BIT30|BIT29|BIT28) 483 #define SCU_PDSEL1_PD6_SEL (BIT27|BIT26|BIT25|BIT24) 484 #define SCU_PDSEL1_PD5_SEL (BIT23|BIT22|BIT21|BIT20) 485 #define SCU_PDSEL1_PD4_SEL (BIT19|BIT18|BIT17|BIT16) 486 #define SCU_PDSEL1_PD3_SEL (BIT15|BIT14|BIT13|BIT12) 487 #define SCU_PDSEL1_PD2_SEL (BIT11|BIT10|BIT9|BIT8) 488 #define SCU_PDSEL1_PD1_SEL (BIT7|BIT6|BIT5|BIT4) 489 #define SCU_PDSEL1_PD0_SEL (BIT3|BIT2|BIT1|BIT0) 490 491 /**************** Bit definition for SCU PCSTR register **********************/ 492 #define SCU_PCSTR_PC12_STH (BIT25|BIT24) 493 #define SCU_PCSTR_PC11_STH (BIT23|BIT22) 494 #define SCU_PCSTR_PC10_STH (BIT21|BIT20) 495 #define SCU_PCSTR_PC9_STH (BIT19|BIT18) 496 #define SCU_PCSTR_PC8_STH (BIT17|BIT16) 497 #define SCU_PCSTR_PC7_STH (BIT15|BIT14) 498 #define SCU_PCSTR_PC6_STH (BIT13|BIT12) 499 #define SCU_PCSTR_PC5_STH (BIT11|BIT10) 500 #define SCU_PCSTR_PC4_STH (BIT9|BIT8) 501 #define SCU_PCSTR_PC3_STH (BIT7|BIT6) 502 #define SCU_PCSTR_PC2_STH (BIT5|BIT4) 503 #define SCU_PCSTR_PC1_STH (BIT3|BIT2) 504 #define SCU_PCSTR_PC0_STH (BIT1|BIT0) 505 506 /**************** Bit definition for SCU PDSTR register **********************/ 507 #define SCU_PDSTR_PD7_STH (BIT15|BIT14) 508 #define SCU_PDSTR_PD6_STH (BIT13|BIT12) 509 #define SCU_PDSTR_PD5_STH (BIT11|BIT10) 510 #define SCU_PDSTR_PD4_STH (BIT9|BIT8) 511 #define SCU_PDSTR_PD3_STH (BIT7|BIT6) 512 #define SCU_PDSTR_PD2_STH (BIT5|BIT4) 513 #define SCU_PDSTR_PD1_STH (BIT3|BIT2) 514 #define SCU_PDSTR_PD0_STH (BIT1|BIT0) 515 516 /* 517 * @brief Peripheral Enable structures definition 518 */ 519 typedef enum 520 { 521 EN_CAN1 = 45, 522 EN_ROM = 44, 523 EN_HRNG = 43, 524 EN_AES = 42, 525 EN_TIM17 = 41, 526 EN_TIM16 = 40, 527 EN_TIM15 = 39, 528 EN_TIM14 = 38, 529 EN_TIM7 = 37, 530 EN_TIM6 = 36, 531 EN_TIM3 = 35, 532 EN_TIM1 = 34, 533 EN_UART3 = 33, 534 EN_TIM2 = 32, 535 EN_OPA = 31, 536 EN_COMP = 30, 537 EN_TKEY = 29, 538 EN_ADC = 28, 539 EN_RTC = 27, 540 EN_DMA = 26, 541 EN_CRC = 25, 542 EN_DAC = 24, 543 EN_USB = 23, 544 EN_LPUART = 22, 545 EN_I2C2 = 21, 546 EN_I2C1 = 20, 547 EN_SPI2 = 19, 548 EN_SPI1 = 18, 549 EN_UART2 = 17, 550 EN_UART1 = 16, 551 EN_CAN2 = 15, 552 EN_I2S1 = 14, 553 554 EN_SPI4 = 13, 555 EN_GPIOEF = 12, 556 EN_SPI3 = 11, 557 EN_UART4 = 10, 558 EN_TIM4 = 9, 559 EN_FAU = 8, 560 EN_EFC = 6, 561 EN_SRAM = 5, 562 EN_EXTI = 4, 563 EN_IWDT = 3, 564 EN_WDT = 2, 565 EN_GPIOCD = 1, 566 EN_GPIOAB = 0, 567 }enum_Enable_ID_t; 568 569 typedef enum 570 { 571 RESET_REASON_LOW_VOLTAGE = 0x00U, // low voltage detected, leads to reset 572 RESET_REASON_WDT = 0x01U, // System WDT reset 573 RESET_REASON_IWDT = 0x02U, // IWDT reset 574 RESET_REASON_LOCKUP = 0x03U, // cortex-m0 lockup leads to reset 575 RESET_REASON_SYSREQ = 0x04U, // system reset 576 RESET_REASON_RSTN = 0x05U, // RSTN negative pulse leads to reset 577 RESET_REASON_EFC = 0x06U, // efc reset leads to reset 578 RESET_REASON_SOFT = 0x07U, // soft reset 579 RESET_REASON_POR12 = 0x09U, // core power on reset, rtc not reset, eg:wakeup from standby 580 RESET_REASON_POR = 0x0AU, // chip power on reset 581 RESET_REASON_INVALID, 582 }RESET_REASON; 583 584 #define NVIC_PRIORITY_GROUP_3 0x00000004U // 3 bits for pre-emption priority, 0 bit for subpriority 585 #define NVIC_PRIORITY_GROUP_2 0x00000005U // 2 bits for pre-emption priority, 1 bit for subpriority 586 #define NVIC_PRIORITY_GROUP_1 0x00000006U // 1 bits for pre-emption priority, 2 bit for subpriority 587 #define NVIC_PRIORITY_GROUP_0 0x00000007U // 0 bits for pre-emption priority, 3 bit for subpriority 588 589 #define SYSTEM_TIMEOUT (1000000) 590 591 592 /* System_Init */ 593 void System_Init(void); 594 595 /* System_Core_Config */ 596 void System_Core_Config(void); 597 598 /* System_Clock_Init */ 599 bool System_Clock_Init(uint32_t fu32_Clock); 600 601 /* System_SysTick_Init */ 602 void System_SysTick_Init(void); 603 604 /* System_Get_SystemClock */ 605 uint32_t System_Get_SystemClock(void); 606 607 /* System_Get_APBClock */ 608 uint32_t System_Get_APBClock(void); 609 610 /* System_Module_Reset */ 611 void System_Module_Reset(enum_RST_ID_t fe_ID_Index); 612 613 /* System_Module_Enable */ 614 void System_Module_Enable(enum_Enable_ID_t fe_ID_Index); 615 616 /* System_Module_Disable */ 617 void System_Module_Disable(enum_Enable_ID_t fe_ID_Index); 618 619 /* System_Delay */ 620 void System_Delay(volatile uint32_t fu32_Delay); 621 622 /* System_Delay_MS */ 623 void System_Delay_MS(volatile uint32_t fu32_Delay); 624 625 /* System_Enable_RC32K */ 626 void System_Enable_RC32K(void); 627 628 /* System_Disable_RC32K */ 629 void System_Disable_RC32K(void); 630 631 /* System_Enable_XTAL */ 632 void System_Enable_XTAL(void); 633 634 /* System_Disable_XTAL */ 635 void System_Disable_XTAL(void); 636 637 /* System_Clear_Stop_Wakeup */ 638 void System_Clear_Stop_Wakeup(void); 639 640 /* System_Enter_Standby_Mode */ 641 void System_Enter_Standby_Mode(void); 642 643 /* System_Enter_Stop_Mode */ 644 void System_Enter_Stop_Mode(uint8_t STOPEntry); 645 646 /* System_Enter_Sleep_Mode */ 647 void System_Enter_Sleep_Mode(uint8_t SleepEntry); 648 649 /* System_Enable_Disable_Reset */ 650 void System_Enable_Disable_Reset(RESET_ENABLE_SOURCE source, FUNC_DISABLE_ENABLE enable_disable); 651 652 /* System_Reset_MCU */ 653 void System_Reset_MCU(RESET_SOURCE source); 654 655 /* System_Enable_Disable_RTC_Domain_Access */ 656 void System_Enable_Disable_RTC_Domain_Access(FUNC_DISABLE_ENABLE enable_disable); 657 658 /* System_Return_Last_Reset_Reason */ 659 RESET_REASON System_Return_Last_Reset_Reason(void) ; 660 661 /* System_Set_Buzzer_Divider */ 662 void System_Set_Buzzer_Divider(uint32_t div, FUNC_DISABLE_ENABLE enable); 663 664 /* System_USB_PHY_Config */ 665 uint32_t System_USB_PHY_Config(void); 666 667 #endif 668 669 670 671 672