1 /********************************************************************************** 2 * 3 * @file reg_pmu.h 4 * @brief PMU Head File 5 * 6 * @date 15 Dec. 2022 7 * @author AE Team 8 * @note 9 * Change Logs: 10 * Date Author Notes 11 * 15 Dec. 2022 Lisq the first version 12 * 13 * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. 14 * 15 * SPDX-License-Identifier: Apache-2.0 16 * 17 * Licensed under the Apache License, Version 2.0 (the License); you may 18 * not use this file except in compliance with the License. 19 * You may obtain a copy of the License at 20 * 21 * www.apache.org/licenses/LICENSE-2.0 22 * 23 * Unless required by applicable law or agreed to in writing, software 24 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 25 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 * See the License for the specific language governing permissions and 27 * limitations under the License. 28 * 29 ********************************************************************************** 30 */ 31 32 #ifndef __REG_PMU_H__ 33 #define __REG_PMU_H__ 34 35 /****************** Bit definition for PMU_CR register ************************/ 36 37 #define PMU_CR_WKEVNSEL_POSS 24U 38 #define PMU_CR_WKEVNSEL_POSE 28U 39 #define PMU_CR_WKEVNSEL_MSK BITS(PMU_CR_WKEVNSEL_POSS,PMU_CR_WKEVNSEL_POSE) 40 41 #define PMU_CR_FSTOP_POS 23U 42 #define PMU_CR_FSTOP_MSK BIT(PMU_CR_FSTOP_POS) 43 44 #define PMU_CR_BGSTOP_POS 21U 45 #define PMU_CR_BGSTOP_MSK BIT(PMU_CR_BGSTOP_POS) 46 47 #define PMU_CR_LPSTOP_POS 20U 48 #define PMU_CR_LPSTOP_MSK BIT(PMU_CR_LPSTOP_POS) 49 50 #define PMU_CR_LPRUN_POS 19U 51 #define PMU_CR_LPRUN_MSK BIT(PMU_CR_LPRUN_POS) 52 53 #define PMU_CR_LPVS_POSS 16U 54 #define PMU_CR_LPVS_POSE 17U 55 #define PMU_CR_LPVS_MSK BITS(PMU_CR_LPVS_POSS,PMU_CR_LPVS_POSE) 56 57 #define PMU_CR_VROSCEN_POS 7U 58 #define PMU_CR_VROSCEN_MSK BIT(PMU_CR_VROSCEN_POS) 59 60 #define PMU_CR_NORRTNEN_POS 6U 61 #define PMU_CR_NORRTNEN_MSK BIT(PMU_CR_NORRTNEN_POS) 62 63 #define PMU_CR_STPRTNEN_POS 5U 64 #define PMU_CR_STPRTNEN_MSK BIT(PMU_CR_STPRTNEN_POS) 65 66 #define PMU_CR_CWUF_POS 2U 67 #define PMU_CR_CWUF_MSK BIT(PMU_CR_CWUF_POS) 68 69 #define PMU_CR_LPM_POSS 0U 70 #define PMU_CR_LPM_POSE 1U 71 #define PMU_CR_LPM_MSK BITS(PMU_CR_LPM_POSS,PMU_CR_LPM_POSE) 72 73 /****************** Bit definition for PMU_SR register ************************/ 74 75 #define PMU_SR_WUF_POS 0U 76 #define PMU_SR_WUF_MSK BIT(PMU_SR_WUF_POS) 77 78 /****************** Bit definition for PMU_LVDCR register ************************/ 79 80 #define PMU_LVDCR_LVDO_POS 15U 81 #define PMU_LVDCR_LVDO_MSK BIT(PMU_LVDCR_LVDO_POS) 82 83 #define PMU_LVDCR_LVDFLT_POS 11U 84 #define PMU_LVDCR_LVDFLT_MSK BIT(PMU_LVDCR_LVDFLT_POS) 85 86 #define PMU_LVDCR_LVDIFS_POSS 8U 87 #define PMU_LVDCR_LVDIFS_POSE 10U 88 #define PMU_LVDCR_LVDIFS_MSK BITS(PMU_LVDCR_LVDIFS_POSS,PMU_LVDCR_LVDIFS_POSE) 89 90 #define PMU_LVDCR_LVDS_POSS 4U 91 #define PMU_LVDCR_LVDS_POSE 7U 92 #define PMU_LVDCR_LVDS_MSK BITS(PMU_LVDCR_LVDS_POSS,PMU_LVDCR_LVDS_POSE) 93 94 #define PMU_LVDCR_LVDCIF_POS 3U 95 #define PMU_LVDCR_LVDCIF_MSK BIT(PMU_LVDCR_LVDCIF_POS) 96 97 #define PMU_LVDCR_LVDIF_POS 2U 98 #define PMU_LVDCR_LVDIF_MSK BIT(PMU_LVDCR_LVDIF_POS) 99 100 #define PMU_LVDCR_LVDIE_POS 1U 101 #define PMU_LVDCR_LVDIE_MSK BIT(PMU_LVDCR_LVDIE_POS) 102 103 #define PMU_LVDCR_LVDEN_POS 0U 104 #define PMU_LVDCR_LVDEN_MSK BIT(PMU_LVDCR_LVDEN_POS) 105 106 /****************** Bit definition for PMU_TWUR register ************************/ 107 108 #define PMU_TWUR_TWU_POSS 0U 109 #define PMU_TWUR_TWU_POSE 11U 110 #define PMU_TWUR_TWU_MSK BITS(PMU_TWUR_TWU_POSS,PMU_TWUR_TWU_POSE) 111 112 typedef struct 113 { 114 __IO uint32_t CR; 115 __I uint32_t SR; 116 __IO uint32_t LVDCR; 117 uint32_t RESERVED0 ; 118 __IO uint32_t TWUR; 119 } PMU_TypeDef; 120 121 122 123 124 125 #endif /* __REG_PMU_H__ */ 126 127 /************* (C) COPYRIGHT Eastsoft Microelectronics *****END OF FILE****/ 128