1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_PPI_H
10 #define HPM_PPI_H
11 
12 typedef struct {
13     __RW uint32_t GLB_CFG;                     /* 0x0: glb_cfg */
14     __RW uint32_t PAD_CFG;                     /* 0x4: pad_cfg */
15     __R  uint8_t  RESERVED0[12];               /* 0x8 - 0x13: Reserved */
16     __RW uint32_t CLKPIN_CFG;                  /* 0x14: clkpin_cfg */
17     __RW uint32_t TM_CFG;                      /* 0x18: tm_cfg */
18     __R  uint8_t  RESERVED1[4];                /* 0x1C - 0x1F: Reserved */
19     __RW uint32_t IRQ_STS;                     /* 0x20: irq_sts */
20     __RW uint32_t IRQ_EN;                      /* 0x24: irq_en */
21     __R  uint8_t  RESERVED2[24];               /* 0x28 - 0x3F: Reserved */
22     struct {
23         __RW uint32_t CFG0;                    /* 0x40: cfg0 */
24         __RW uint32_t CFG1;                    /* 0x44: cfg1 */
25         __RW uint32_t CFG2;                    /* 0x48: cfg2 */
26         __RW uint32_t CFG3;                    /* 0x4C: cfg3 */
27         __RW uint32_t CFG4;                    /* 0x50: cfg4 */
28         __R  uint8_t  RESERVED0[12];           /* 0x54 - 0x5F: Reserved */
29     } CS[4];
30     __R  uint8_t  RESERVED3[832];              /* 0xC0 - 0x3FF: Reserved */
31     struct {
32         __RW uint32_t CMD_CFG;                 /* 0x400: cmd_cfg */
33         __RW uint32_t AD_CFG;                  /* 0x404: ad_cfg */
34         __RW uint32_t CTRL_CFG;                /* 0x408: ctrl_cfg */
35         __R  uint8_t  RESERVED0[4];            /* 0x40C - 0x40F: Reserved */
36     } CMD[64];
37 } PPI_Type;
38 
39 
40 /* Bitfield definition for register: GLB_CFG */
41 /*
42  * PAD_OUT_REG_ENJ (RW)
43  *
44  * 0:  register output, one cycle delay;
45  * 1:  direct output， no delay but may have timing issue
46  */
47 #define PPI_GLB_CFG_PAD_OUT_REG_ENJ_MASK (0x2U)
48 #define PPI_GLB_CFG_PAD_OUT_REG_ENJ_SHIFT (1U)
49 #define PPI_GLB_CFG_PAD_OUT_REG_ENJ_SET(x) (((uint32_t)(x) << PPI_GLB_CFG_PAD_OUT_REG_ENJ_SHIFT) & PPI_GLB_CFG_PAD_OUT_REG_ENJ_MASK)
50 #define PPI_GLB_CFG_PAD_OUT_REG_ENJ_GET(x) (((uint32_t)(x) & PPI_GLB_CFG_PAD_OUT_REG_ENJ_MASK) >> PPI_GLB_CFG_PAD_OUT_REG_ENJ_SHIFT)
51 
52 /*
53  * SOFT_RESET (RW)
54  *
55  * software reset
56  */
57 #define PPI_GLB_CFG_SOFT_RESET_MASK (0x1U)
58 #define PPI_GLB_CFG_SOFT_RESET_SHIFT (0U)
59 #define PPI_GLB_CFG_SOFT_RESET_SET(x) (((uint32_t)(x) << PPI_GLB_CFG_SOFT_RESET_SHIFT) & PPI_GLB_CFG_SOFT_RESET_MASK)
60 #define PPI_GLB_CFG_SOFT_RESET_GET(x) (((uint32_t)(x) & PPI_GLB_CFG_SOFT_RESET_MASK) >> PPI_GLB_CFG_SOFT_RESET_SHIFT)
61 
62 /* Bitfield definition for register: PAD_CFG */
63 /*
64  * CS_IDLE_ST (RW)
65  *
66  * cs pin idle state, default high for active low
67  */
68 #define PPI_PAD_CFG_CS_IDLE_ST_MASK (0xF000000UL)
69 #define PPI_PAD_CFG_CS_IDLE_ST_SHIFT (24U)
70 #define PPI_PAD_CFG_CS_IDLE_ST_SET(x) (((uint32_t)(x) << PPI_PAD_CFG_CS_IDLE_ST_SHIFT) & PPI_PAD_CFG_CS_IDLE_ST_MASK)
71 #define PPI_PAD_CFG_CS_IDLE_ST_GET(x) (((uint32_t)(x) & PPI_PAD_CFG_CS_IDLE_ST_MASK) >> PPI_PAD_CFG_CS_IDLE_ST_SHIFT)
72 
73 /*
74  * DM_PAD_POL (RW)
75  *
76  * dm pin polarity
77  */
78 #define PPI_PAD_CFG_DM_PAD_POL_MASK (0xF0000UL)
79 #define PPI_PAD_CFG_DM_PAD_POL_SHIFT (16U)
80 #define PPI_PAD_CFG_DM_PAD_POL_SET(x) (((uint32_t)(x) << PPI_PAD_CFG_DM_PAD_POL_SHIFT) & PPI_PAD_CFG_DM_PAD_POL_MASK)
81 #define PPI_PAD_CFG_DM_PAD_POL_GET(x) (((uint32_t)(x) & PPI_PAD_CFG_DM_PAD_POL_MASK) >> PPI_PAD_CFG_DM_PAD_POL_SHIFT)
82 
83 /*
84  * CTRL_PAD_OE (RW)
85  *
86  * the pad output enable signal. 0 for IN; 1 for OUT.
87  * NOTE: for unused pads, set both ctrl_pad_oe and ctrl_pad_pol to 0
88  */
89 #define PPI_PAD_CFG_CTRL_PAD_OE_MASK (0xFF00U)
90 #define PPI_PAD_CFG_CTRL_PAD_OE_SHIFT (8U)
91 #define PPI_PAD_CFG_CTRL_PAD_OE_SET(x) (((uint32_t)(x) << PPI_PAD_CFG_CTRL_PAD_OE_SHIFT) & PPI_PAD_CFG_CTRL_PAD_OE_MASK)
92 #define PPI_PAD_CFG_CTRL_PAD_OE_GET(x) (((uint32_t)(x) & PPI_PAD_CFG_CTRL_PAD_OE_MASK) >> PPI_PAD_CFG_CTRL_PAD_OE_SHIFT)
93 
94 /*
95  * CTRL_PAD_POL (RW)
96  *
97  * for OUT pad:
98  * 0: output the value in cmd
99  * 1: output reversed value in cmd
100  * for IN pad, defines the signal active value,  when ctrl_cfg.io_cfg is set,
101  * will wait the active value for ready(generally read or write ready)
102  */
103 #define PPI_PAD_CFG_CTRL_PAD_POL_MASK (0xFFU)
104 #define PPI_PAD_CFG_CTRL_PAD_POL_SHIFT (0U)
105 #define PPI_PAD_CFG_CTRL_PAD_POL_SET(x) (((uint32_t)(x) << PPI_PAD_CFG_CTRL_PAD_POL_SHIFT) & PPI_PAD_CFG_CTRL_PAD_POL_MASK)
106 #define PPI_PAD_CFG_CTRL_PAD_POL_GET(x) (((uint32_t)(x) & PPI_PAD_CFG_CTRL_PAD_POL_MASK) >> PPI_PAD_CFG_CTRL_PAD_POL_SHIFT)
107 
108 /* Bitfield definition for register: CLKPIN_CFG */
109 /*
110  * CYCLE (RW)
111  *
112  * there will be a system counter run from 0 to cycle,
113  * clk output will be set to high when counter is clk_high, and low when counter is clk_low.
114  * The output will be system clock if cycle is 0.
115  * All 4 CS share same clock configuration(one clock pin with configured frequency).
116  * different CS can be assert at different  counter value.
117  */
118 #define PPI_CLKPIN_CFG_CYCLE_MASK (0xF000000UL)
119 #define PPI_CLKPIN_CFG_CYCLE_SHIFT (24U)
120 #define PPI_CLKPIN_CFG_CYCLE_SET(x) (((uint32_t)(x) << PPI_CLKPIN_CFG_CYCLE_SHIFT) & PPI_CLKPIN_CFG_CYCLE_MASK)
121 #define PPI_CLKPIN_CFG_CYCLE_GET(x) (((uint32_t)(x) & PPI_CLKPIN_CFG_CYCLE_MASK) >> PPI_CLKPIN_CFG_CYCLE_SHIFT)
122 
123 /*
124  * HIGH (RW)
125  *
126  * clock high numer
127  */
128 #define PPI_CLKPIN_CFG_HIGH_MASK (0xF0000UL)
129 #define PPI_CLKPIN_CFG_HIGH_SHIFT (16U)
130 #define PPI_CLKPIN_CFG_HIGH_SET(x) (((uint32_t)(x) << PPI_CLKPIN_CFG_HIGH_SHIFT) & PPI_CLKPIN_CFG_HIGH_MASK)
131 #define PPI_CLKPIN_CFG_HIGH_GET(x) (((uint32_t)(x) & PPI_CLKPIN_CFG_HIGH_MASK) >> PPI_CLKPIN_CFG_HIGH_SHIFT)
132 
133 /*
134  * LOW (RW)
135  *
136  * clock low number
137  */
138 #define PPI_CLKPIN_CFG_LOW_MASK (0xF00U)
139 #define PPI_CLKPIN_CFG_LOW_SHIFT (8U)
140 #define PPI_CLKPIN_CFG_LOW_SET(x) (((uint32_t)(x) << PPI_CLKPIN_CFG_LOW_SHIFT) & PPI_CLKPIN_CFG_LOW_MASK)
141 #define PPI_CLKPIN_CFG_LOW_GET(x) (((uint32_t)(x) & PPI_CLKPIN_CFG_LOW_MASK) >> PPI_CLKPIN_CFG_LOW_SHIFT)
142 
143 /*
144  * INVERT (RW)
145  *
146  * set to invert clock output
147  */
148 #define PPI_CLKPIN_CFG_INVERT_MASK (0x20U)
149 #define PPI_CLKPIN_CFG_INVERT_SHIFT (5U)
150 #define PPI_CLKPIN_CFG_INVERT_SET(x) (((uint32_t)(x) << PPI_CLKPIN_CFG_INVERT_SHIFT) & PPI_CLKPIN_CFG_INVERT_MASK)
151 #define PPI_CLKPIN_CFG_INVERT_GET(x) (((uint32_t)(x) & PPI_CLKPIN_CFG_INVERT_MASK) >> PPI_CLKPIN_CFG_INVERT_SHIFT)
152 
153 /*
154  * AON (RW)
155  *
156  * 0:  use clk_gate in cmd sequence for whether output clock
157  * 1: always enable clock output;
158  */
159 #define PPI_CLKPIN_CFG_AON_MASK (0x2U)
160 #define PPI_CLKPIN_CFG_AON_SHIFT (1U)
161 #define PPI_CLKPIN_CFG_AON_SET(x) (((uint32_t)(x) << PPI_CLKPIN_CFG_AON_SHIFT) & PPI_CLKPIN_CFG_AON_MASK)
162 #define PPI_CLKPIN_CFG_AON_GET(x) (((uint32_t)(x) & PPI_CLKPIN_CFG_AON_MASK) >> PPI_CLKPIN_CFG_AON_SHIFT)
163 
164 /*
165  * EN (RW)
166  *
167  * set to enable clock logic
168  */
169 #define PPI_CLKPIN_CFG_EN_MASK (0x1U)
170 #define PPI_CLKPIN_CFG_EN_SHIFT (0U)
171 #define PPI_CLKPIN_CFG_EN_SET(x) (((uint32_t)(x) << PPI_CLKPIN_CFG_EN_SHIFT) & PPI_CLKPIN_CFG_EN_MASK)
172 #define PPI_CLKPIN_CFG_EN_GET(x) (((uint32_t)(x) & PPI_CLKPIN_CFG_EN_MASK) >> PPI_CLKPIN_CFG_EN_SHIFT)
173 
174 /* Bitfield definition for register: TM_CFG */
175 /*
176  * TM_EN (RW)
177  *
178  * timeout enable.
179  * if enabled, then if each AHB transfer time exceed tm_cfg clock cycles, will assert irq
180  */
181 #define PPI_TM_CFG_TM_EN_MASK (0x10000UL)
182 #define PPI_TM_CFG_TM_EN_SHIFT (16U)
183 #define PPI_TM_CFG_TM_EN_SET(x) (((uint32_t)(x) << PPI_TM_CFG_TM_EN_SHIFT) & PPI_TM_CFG_TM_EN_MASK)
184 #define PPI_TM_CFG_TM_EN_GET(x) (((uint32_t)(x) & PPI_TM_CFG_TM_EN_MASK) >> PPI_TM_CFG_TM_EN_SHIFT)
185 
186 /*
187  * TM_CFG (RW)
188  *
189  * timeout value, max 20us at 200MHz clock
190  */
191 #define PPI_TM_CFG_TM_CFG_MASK (0xFFFU)
192 #define PPI_TM_CFG_TM_CFG_SHIFT (0U)
193 #define PPI_TM_CFG_TM_CFG_SET(x) (((uint32_t)(x) << PPI_TM_CFG_TM_CFG_SHIFT) & PPI_TM_CFG_TM_CFG_MASK)
194 #define PPI_TM_CFG_TM_CFG_GET(x) (((uint32_t)(x) & PPI_TM_CFG_TM_CFG_MASK) >> PPI_TM_CFG_TM_CFG_SHIFT)
195 
196 /* Bitfield definition for register: IRQ_STS */
197 /*
198  * IRQ_TMOUT_STS (RW1C)
199  *
200  * tiemout interrupt status, write 1 to clear
201  */
202 #define PPI_IRQ_STS_IRQ_TMOUT_STS_MASK (0x1U)
203 #define PPI_IRQ_STS_IRQ_TMOUT_STS_SHIFT (0U)
204 #define PPI_IRQ_STS_IRQ_TMOUT_STS_SET(x) (((uint32_t)(x) << PPI_IRQ_STS_IRQ_TMOUT_STS_SHIFT) & PPI_IRQ_STS_IRQ_TMOUT_STS_MASK)
205 #define PPI_IRQ_STS_IRQ_TMOUT_STS_GET(x) (((uint32_t)(x) & PPI_IRQ_STS_IRQ_TMOUT_STS_MASK) >> PPI_IRQ_STS_IRQ_TMOUT_STS_SHIFT)
206 
207 /* Bitfield definition for register: IRQ_EN */
208 /*
209  * IRQ_TMOUT_EN (RW)
210  *
211  * timeout interrupt enable
212  */
213 #define PPI_IRQ_EN_IRQ_TMOUT_EN_MASK (0x1U)
214 #define PPI_IRQ_EN_IRQ_TMOUT_EN_SHIFT (0U)
215 #define PPI_IRQ_EN_IRQ_TMOUT_EN_SET(x) (((uint32_t)(x) << PPI_IRQ_EN_IRQ_TMOUT_EN_SHIFT) & PPI_IRQ_EN_IRQ_TMOUT_EN_MASK)
216 #define PPI_IRQ_EN_IRQ_TMOUT_EN_GET(x) (((uint32_t)(x) & PPI_IRQ_EN_IRQ_TMOUT_EN_MASK) >> PPI_IRQ_EN_IRQ_TMOUT_EN_SHIFT)
217 
218 /* Bitfield definition for register of struct array CS: CFG0 */
219 /*
220  * ADDR_END (RW)
221  *
222  */
223 #define PPI_CS_CFG0_ADDR_END_MASK (0xFFF0000UL)
224 #define PPI_CS_CFG0_ADDR_END_SHIFT (16U)
225 #define PPI_CS_CFG0_ADDR_END_SET(x) (((uint32_t)(x) << PPI_CS_CFG0_ADDR_END_SHIFT) & PPI_CS_CFG0_ADDR_END_MASK)
226 #define PPI_CS_CFG0_ADDR_END_GET(x) (((uint32_t)(x) & PPI_CS_CFG0_ADDR_END_MASK) >> PPI_CS_CFG0_ADDR_END_SHIFT)
227 
228 /*
229  * ADDR_START (RW)
230  *
231  * addr_start and addr_end config the address slot for CS0, use high 12bit,
232  * the minimun slot is 1Mbyte(addr_start==addr_end)
233  */
234 #define PPI_CS_CFG0_ADDR_START_MASK (0xFFFU)
235 #define PPI_CS_CFG0_ADDR_START_SHIFT (0U)
236 #define PPI_CS_CFG0_ADDR_START_SET(x) (((uint32_t)(x) << PPI_CS_CFG0_ADDR_START_SHIFT) & PPI_CS_CFG0_ADDR_START_MASK)
237 #define PPI_CS_CFG0_ADDR_START_GET(x) (((uint32_t)(x) & PPI_CS_CFG0_ADDR_START_MASK) >> PPI_CS_CFG0_ADDR_START_SHIFT)
238 
239 /* Bitfield definition for register of struct array CS: CFG1 */
240 /*
241  * ADDR_MASK (RW)
242  *
243  * the high AHB address will AND with {cs0_mask[15:0], 16'hFFFF},
244  * shift right with addr_shift, then output as real address.
245  */
246 #define PPI_CS_CFG1_ADDR_MASK_MASK (0xFFFF0000UL)
247 #define PPI_CS_CFG1_ADDR_MASK_SHIFT (16U)
248 #define PPI_CS_CFG1_ADDR_MASK_SET(x) (((uint32_t)(x) << PPI_CS_CFG1_ADDR_MASK_SHIFT) & PPI_CS_CFG1_ADDR_MASK_MASK)
249 #define PPI_CS_CFG1_ADDR_MASK_GET(x) (((uint32_t)(x) & PPI_CS_CFG1_ADDR_MASK_MASK) >> PPI_CS_CFG1_ADDR_MASK_SHIFT)
250 
251 /*
252  * ADDR_SHIFT (RW)
253  *
254  * gennerally should be configured according to port size,
255  * 0 for 8bit; 1 for 16bit; 2 for 32bit;
256  */
257 #define PPI_CS_CFG1_ADDR_SHIFT_MASK (0xFU)
258 #define PPI_CS_CFG1_ADDR_SHIFT_SHIFT (0U)
259 #define PPI_CS_CFG1_ADDR_SHIFT_SET(x) (((uint32_t)(x) << PPI_CS_CFG1_ADDR_SHIFT_SHIFT) & PPI_CS_CFG1_ADDR_SHIFT_MASK)
260 #define PPI_CS_CFG1_ADDR_SHIFT_GET(x) (((uint32_t)(x) & PPI_CS_CFG1_ADDR_SHIFT_MASK) >> PPI_CS_CFG1_ADDR_SHIFT_SHIFT)
261 
262 /* Bitfield definition for register of struct array CS: CFG2 */
263 /*
264  * CS_SYNC_EN (RW)
265  *
266  * set to enable CS pin sync with clock counter.
267  * Clr if use async mode(no clk pin), or not care the CS start time with clk pin
268  */
269 #define PPI_CS_CFG2_CS_SYNC_EN_MASK (0x10000000UL)
270 #define PPI_CS_CFG2_CS_SYNC_EN_SHIFT (28U)
271 #define PPI_CS_CFG2_CS_SYNC_EN_SET(x) (((uint32_t)(x) << PPI_CS_CFG2_CS_SYNC_EN_SHIFT) & PPI_CS_CFG2_CS_SYNC_EN_MASK)
272 #define PPI_CS_CFG2_CS_SYNC_EN_GET(x) (((uint32_t)(x) & PPI_CS_CFG2_CS_SYNC_EN_MASK) >> PPI_CS_CFG2_CS_SYNC_EN_SHIFT)
273 
274 /*
275  * SYNC_CLK_SEL (RW)
276  *
277  * CS assert at when clk_div_cnt equal to sync_clk_sel
278  */
279 #define PPI_CS_CFG2_SYNC_CLK_SEL_MASK (0xF00000UL)
280 #define PPI_CS_CFG2_SYNC_CLK_SEL_SHIFT (20U)
281 #define PPI_CS_CFG2_SYNC_CLK_SEL_SET(x) (((uint32_t)(x) << PPI_CS_CFG2_SYNC_CLK_SEL_SHIFT) & PPI_CS_CFG2_SYNC_CLK_SEL_MASK)
282 #define PPI_CS_CFG2_SYNC_CLK_SEL_GET(x) (((uint32_t)(x) & PPI_CS_CFG2_SYNC_CLK_SEL_MASK) >> PPI_CS_CFG2_SYNC_CLK_SEL_SHIFT)
283 
284 /*
285  * READY_IN_SEL (RW)
286  *
287  * 0: use two stage sync;
288  * 1: use one stage sync
289  */
290 #define PPI_CS_CFG2_READY_IN_SEL_MASK (0x1000U)
291 #define PPI_CS_CFG2_READY_IN_SEL_SHIFT (12U)
292 #define PPI_CS_CFG2_READY_IN_SEL_SET(x) (((uint32_t)(x) << PPI_CS_CFG2_READY_IN_SEL_SHIFT) & PPI_CS_CFG2_READY_IN_SEL_MASK)
293 #define PPI_CS_CFG2_READY_IN_SEL_GET(x) (((uint32_t)(x) & PPI_CS_CFG2_READY_IN_SEL_MASK) >> PPI_CS_CFG2_READY_IN_SEL_SHIFT)
294 
295 /*
296  * INTER_CMD_DLY (RW)
297  *
298  * set to none-zero value, will add delay between each command sequence for burst cmd,
299  * or splited transfer cmd sequence(such as transfer 32bit on 16bit port),
300  * CS will be de-assert during the delay.
301  */
302 #define PPI_CS_CFG2_INTER_CMD_DLY_MASK (0xF0U)
303 #define PPI_CS_CFG2_INTER_CMD_DLY_SHIFT (4U)
304 #define PPI_CS_CFG2_INTER_CMD_DLY_SET(x) (((uint32_t)(x) << PPI_CS_CFG2_INTER_CMD_DLY_SHIFT) & PPI_CS_CFG2_INTER_CMD_DLY_MASK)
305 #define PPI_CS_CFG2_INTER_CMD_DLY_GET(x) (((uint32_t)(x) & PPI_CS_CFG2_INTER_CMD_DLY_MASK) >> PPI_CS_CFG2_INTER_CMD_DLY_SHIFT)
306 
307 /*
308  * PORT_SIZE (RW)
309  *
310  * 00-8bit; 01-16bit; 10-32bit; 11-reserved
311  */
312 #define PPI_CS_CFG2_PORT_SIZE_MASK (0x6U)
313 #define PPI_CS_CFG2_PORT_SIZE_SHIFT (1U)
314 #define PPI_CS_CFG2_PORT_SIZE_SET(x) (((uint32_t)(x) << PPI_CS_CFG2_PORT_SIZE_SHIFT) & PPI_CS_CFG2_PORT_SIZE_MASK)
315 #define PPI_CS_CFG2_PORT_SIZE_GET(x) (((uint32_t)(x) & PPI_CS_CFG2_PORT_SIZE_MASK) >> PPI_CS_CFG2_PORT_SIZE_SHIFT)
316 
317 /*
318  * ENABLE (RW)
319  *
320  * CS enable
321  */
322 #define PPI_CS_CFG2_ENABLE_MASK (0x1U)
323 #define PPI_CS_CFG2_ENABLE_SHIFT (0U)
324 #define PPI_CS_CFG2_ENABLE_SET(x) (((uint32_t)(x) << PPI_CS_CFG2_ENABLE_SHIFT) & PPI_CS_CFG2_ENABLE_MASK)
325 #define PPI_CS_CFG2_ENABLE_GET(x) (((uint32_t)(x) & PPI_CS_CFG2_ENABLE_MASK) >> PPI_CS_CFG2_ENABLE_SHIFT)
326 
327 /* Bitfield definition for register of struct array CS: CFG3 */
328 /*
329  * RCMD_END1 (RW)
330  *
331  * sequential read cmd end index
332  */
333 #define PPI_CS_CFG3_RCMD_END1_MASK (0x3F000000UL)
334 #define PPI_CS_CFG3_RCMD_END1_SHIFT (24U)
335 #define PPI_CS_CFG3_RCMD_END1_SET(x) (((uint32_t)(x) << PPI_CS_CFG3_RCMD_END1_SHIFT) & PPI_CS_CFG3_RCMD_END1_MASK)
336 #define PPI_CS_CFG3_RCMD_END1_GET(x) (((uint32_t)(x) & PPI_CS_CFG3_RCMD_END1_MASK) >> PPI_CS_CFG3_RCMD_END1_SHIFT)
337 
338 /*
339  * RCMD_START1 (RW)
340  *
341  * sequential read cmd start index
342  */
343 #define PPI_CS_CFG3_RCMD_START1_MASK (0x3F0000UL)
344 #define PPI_CS_CFG3_RCMD_START1_SHIFT (16U)
345 #define PPI_CS_CFG3_RCMD_START1_SET(x) (((uint32_t)(x) << PPI_CS_CFG3_RCMD_START1_SHIFT) & PPI_CS_CFG3_RCMD_START1_MASK)
346 #define PPI_CS_CFG3_RCMD_START1_GET(x) (((uint32_t)(x) & PPI_CS_CFG3_RCMD_START1_MASK) >> PPI_CS_CFG3_RCMD_START1_SHIFT)
347 
348 /*
349  * RCMD_END0 (RW)
350  *
351  * first read cmd end index
352  */
353 #define PPI_CS_CFG3_RCMD_END0_MASK (0x3F00U)
354 #define PPI_CS_CFG3_RCMD_END0_SHIFT (8U)
355 #define PPI_CS_CFG3_RCMD_END0_SET(x) (((uint32_t)(x) << PPI_CS_CFG3_RCMD_END0_SHIFT) & PPI_CS_CFG3_RCMD_END0_MASK)
356 #define PPI_CS_CFG3_RCMD_END0_GET(x) (((uint32_t)(x) & PPI_CS_CFG3_RCMD_END0_MASK) >> PPI_CS_CFG3_RCMD_END0_SHIFT)
357 
358 /*
359  * RCMD_START0 (RW)
360  *
361  * first read cmd start index
362  */
363 #define PPI_CS_CFG3_RCMD_START0_MASK (0x3FU)
364 #define PPI_CS_CFG3_RCMD_START0_SHIFT (0U)
365 #define PPI_CS_CFG3_RCMD_START0_SET(x) (((uint32_t)(x) << PPI_CS_CFG3_RCMD_START0_SHIFT) & PPI_CS_CFG3_RCMD_START0_MASK)
366 #define PPI_CS_CFG3_RCMD_START0_GET(x) (((uint32_t)(x) & PPI_CS_CFG3_RCMD_START0_MASK) >> PPI_CS_CFG3_RCMD_START0_SHIFT)
367 
368 /* Bitfield definition for register of struct array CS: CFG4 */
369 /*
370  * WCMD_END1 (RW)
371  *
372  * sequential write cmd end index
373  */
374 #define PPI_CS_CFG4_WCMD_END1_MASK (0x3F000000UL)
375 #define PPI_CS_CFG4_WCMD_END1_SHIFT (24U)
376 #define PPI_CS_CFG4_WCMD_END1_SET(x) (((uint32_t)(x) << PPI_CS_CFG4_WCMD_END1_SHIFT) & PPI_CS_CFG4_WCMD_END1_MASK)
377 #define PPI_CS_CFG4_WCMD_END1_GET(x) (((uint32_t)(x) & PPI_CS_CFG4_WCMD_END1_MASK) >> PPI_CS_CFG4_WCMD_END1_SHIFT)
378 
379 /*
380  * WCMD_START1 (RW)
381  *
382  * sequential write cmd start index
383  */
384 #define PPI_CS_CFG4_WCMD_START1_MASK (0x3F0000UL)
385 #define PPI_CS_CFG4_WCMD_START1_SHIFT (16U)
386 #define PPI_CS_CFG4_WCMD_START1_SET(x) (((uint32_t)(x) << PPI_CS_CFG4_WCMD_START1_SHIFT) & PPI_CS_CFG4_WCMD_START1_MASK)
387 #define PPI_CS_CFG4_WCMD_START1_GET(x) (((uint32_t)(x) & PPI_CS_CFG4_WCMD_START1_MASK) >> PPI_CS_CFG4_WCMD_START1_SHIFT)
388 
389 /*
390  * WCMD_END0 (RW)
391  *
392  * first write cmd end index
393  */
394 #define PPI_CS_CFG4_WCMD_END0_MASK (0x3F00U)
395 #define PPI_CS_CFG4_WCMD_END0_SHIFT (8U)
396 #define PPI_CS_CFG4_WCMD_END0_SET(x) (((uint32_t)(x) << PPI_CS_CFG4_WCMD_END0_SHIFT) & PPI_CS_CFG4_WCMD_END0_MASK)
397 #define PPI_CS_CFG4_WCMD_END0_GET(x) (((uint32_t)(x) & PPI_CS_CFG4_WCMD_END0_MASK) >> PPI_CS_CFG4_WCMD_END0_SHIFT)
398 
399 /*
400  * WCMD_START0 (RW)
401  *
402  * first write cmd start index
403  */
404 #define PPI_CS_CFG4_WCMD_START0_MASK (0x3FU)
405 #define PPI_CS_CFG4_WCMD_START0_SHIFT (0U)
406 #define PPI_CS_CFG4_WCMD_START0_SET(x) (((uint32_t)(x) << PPI_CS_CFG4_WCMD_START0_SHIFT) & PPI_CS_CFG4_WCMD_START0_MASK)
407 #define PPI_CS_CFG4_WCMD_START0_GET(x) (((uint32_t)(x) & PPI_CS_CFG4_WCMD_START0_MASK) >> PPI_CS_CFG4_WCMD_START0_SHIFT)
408 
409 /* Bitfield definition for register of struct array CMD: CMD_CFG */
410 /*
411  * CS_VAL (RW)
412  *
413  * cs value in current cmd
414  */
415 #define PPI_CMD_CMD_CFG_CS_VAL_MASK (0x20000UL)
416 #define PPI_CMD_CMD_CFG_CS_VAL_SHIFT (17U)
417 #define PPI_CMD_CMD_CFG_CS_VAL_SET(x) (((uint32_t)(x) << PPI_CMD_CMD_CFG_CS_VAL_SHIFT) & PPI_CMD_CMD_CFG_CS_VAL_MASK)
418 #define PPI_CMD_CMD_CFG_CS_VAL_GET(x) (((uint32_t)(x) & PPI_CMD_CMD_CFG_CS_VAL_MASK) >> PPI_CMD_CMD_CFG_CS_VAL_SHIFT)
419 
420 /*
421  * CLK_GATE (RW)
422  *
423  * the clock gate enable signal, set to output clock signal
424  */
425 #define PPI_CMD_CMD_CFG_CLK_GATE_MASK (0x10000UL)
426 #define PPI_CMD_CMD_CFG_CLK_GATE_SHIFT (16U)
427 #define PPI_CMD_CMD_CFG_CLK_GATE_SET(x) (((uint32_t)(x) << PPI_CMD_CMD_CFG_CLK_GATE_SHIFT) & PPI_CMD_CMD_CFG_CLK_GATE_MASK)
428 #define PPI_CMD_CMD_CFG_CLK_GATE_GET(x) (((uint32_t)(x) & PPI_CMD_CMD_CFG_CLK_GATE_MASK) >> PPI_CMD_CMD_CFG_CLK_GATE_SHIFT)
429 
430 /*
431  * CYCLE_NUM (RW)
432  *
433  * cmd clock cycles
434  */
435 #define PPI_CMD_CMD_CFG_CYCLE_NUM_MASK (0xFFU)
436 #define PPI_CMD_CMD_CFG_CYCLE_NUM_SHIFT (0U)
437 #define PPI_CMD_CMD_CFG_CYCLE_NUM_SET(x) (((uint32_t)(x) << PPI_CMD_CMD_CFG_CYCLE_NUM_SHIFT) & PPI_CMD_CMD_CFG_CYCLE_NUM_MASK)
438 #define PPI_CMD_CMD_CFG_CYCLE_NUM_GET(x) (((uint32_t)(x) & PPI_CMD_CMD_CFG_CYCLE_NUM_MASK) >> PPI_CMD_CMD_CFG_CYCLE_NUM_SHIFT)
439 
440 /* Bitfield definition for register of struct array CMD: AD_CFG */
441 /*
442  * DIR3 (RW)
443  *
444  */
445 #define PPI_CMD_AD_CFG_DIR3_MASK (0x8000U)
446 #define PPI_CMD_AD_CFG_DIR3_SHIFT (15U)
447 #define PPI_CMD_AD_CFG_DIR3_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_DIR3_SHIFT) & PPI_CMD_AD_CFG_DIR3_MASK)
448 #define PPI_CMD_AD_CFG_DIR3_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_DIR3_MASK) >> PPI_CMD_AD_CFG_DIR3_SHIFT)
449 
450 /*
451  * AD_SEL3 (RW)
452  *
453  */
454 #define PPI_CMD_AD_CFG_AD_SEL3_MASK (0x4000U)
455 #define PPI_CMD_AD_CFG_AD_SEL3_SHIFT (14U)
456 #define PPI_CMD_AD_CFG_AD_SEL3_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_AD_SEL3_SHIFT) & PPI_CMD_AD_CFG_AD_SEL3_MASK)
457 #define PPI_CMD_AD_CFG_AD_SEL3_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_AD_SEL3_MASK) >> PPI_CMD_AD_CFG_AD_SEL3_SHIFT)
458 
459 /*
460  * BYTE_SEL3 (RW)
461  *
462  */
463 #define PPI_CMD_AD_CFG_BYTE_SEL3_MASK (0x3000U)
464 #define PPI_CMD_AD_CFG_BYTE_SEL3_SHIFT (12U)
465 #define PPI_CMD_AD_CFG_BYTE_SEL3_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_BYTE_SEL3_SHIFT) & PPI_CMD_AD_CFG_BYTE_SEL3_MASK)
466 #define PPI_CMD_AD_CFG_BYTE_SEL3_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_BYTE_SEL3_MASK) >> PPI_CMD_AD_CFG_BYTE_SEL3_SHIFT)
467 
468 /*
469  * DIR2 (RW)
470  *
471  */
472 #define PPI_CMD_AD_CFG_DIR2_MASK (0x800U)
473 #define PPI_CMD_AD_CFG_DIR2_SHIFT (11U)
474 #define PPI_CMD_AD_CFG_DIR2_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_DIR2_SHIFT) & PPI_CMD_AD_CFG_DIR2_MASK)
475 #define PPI_CMD_AD_CFG_DIR2_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_DIR2_MASK) >> PPI_CMD_AD_CFG_DIR2_SHIFT)
476 
477 /*
478  * AD_SEL2 (RW)
479  *
480  */
481 #define PPI_CMD_AD_CFG_AD_SEL2_MASK (0x400U)
482 #define PPI_CMD_AD_CFG_AD_SEL2_SHIFT (10U)
483 #define PPI_CMD_AD_CFG_AD_SEL2_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_AD_SEL2_SHIFT) & PPI_CMD_AD_CFG_AD_SEL2_MASK)
484 #define PPI_CMD_AD_CFG_AD_SEL2_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_AD_SEL2_MASK) >> PPI_CMD_AD_CFG_AD_SEL2_SHIFT)
485 
486 /*
487  * BYTE_SEL2 (RW)
488  *
489  */
490 #define PPI_CMD_AD_CFG_BYTE_SEL2_MASK (0x300U)
491 #define PPI_CMD_AD_CFG_BYTE_SEL2_SHIFT (8U)
492 #define PPI_CMD_AD_CFG_BYTE_SEL2_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_BYTE_SEL2_SHIFT) & PPI_CMD_AD_CFG_BYTE_SEL2_MASK)
493 #define PPI_CMD_AD_CFG_BYTE_SEL2_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_BYTE_SEL2_MASK) >> PPI_CMD_AD_CFG_BYTE_SEL2_SHIFT)
494 
495 /*
496  * DIR1 (RW)
497  *
498  */
499 #define PPI_CMD_AD_CFG_DIR1_MASK (0x80U)
500 #define PPI_CMD_AD_CFG_DIR1_SHIFT (7U)
501 #define PPI_CMD_AD_CFG_DIR1_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_DIR1_SHIFT) & PPI_CMD_AD_CFG_DIR1_MASK)
502 #define PPI_CMD_AD_CFG_DIR1_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_DIR1_MASK) >> PPI_CMD_AD_CFG_DIR1_SHIFT)
503 
504 /*
505  * AD_SEL1 (RW)
506  *
507  */
508 #define PPI_CMD_AD_CFG_AD_SEL1_MASK (0x40U)
509 #define PPI_CMD_AD_CFG_AD_SEL1_SHIFT (6U)
510 #define PPI_CMD_AD_CFG_AD_SEL1_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_AD_SEL1_SHIFT) & PPI_CMD_AD_CFG_AD_SEL1_MASK)
511 #define PPI_CMD_AD_CFG_AD_SEL1_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_AD_SEL1_MASK) >> PPI_CMD_AD_CFG_AD_SEL1_SHIFT)
512 
513 /*
514  * BYTE_SEL1 (RW)
515  *
516  */
517 #define PPI_CMD_AD_CFG_BYTE_SEL1_MASK (0x30U)
518 #define PPI_CMD_AD_CFG_BYTE_SEL1_SHIFT (4U)
519 #define PPI_CMD_AD_CFG_BYTE_SEL1_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_BYTE_SEL1_SHIFT) & PPI_CMD_AD_CFG_BYTE_SEL1_MASK)
520 #define PPI_CMD_AD_CFG_BYTE_SEL1_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_BYTE_SEL1_MASK) >> PPI_CMD_AD_CFG_BYTE_SEL1_SHIFT)
521 
522 /*
523  * DIR0 (RW)
524  *
525  * 0 for OUT; 1 for IN
526  */
527 #define PPI_CMD_AD_CFG_DIR0_MASK (0x8U)
528 #define PPI_CMD_AD_CFG_DIR0_SHIFT (3U)
529 #define PPI_CMD_AD_CFG_DIR0_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_DIR0_SHIFT) & PPI_CMD_AD_CFG_DIR0_MASK)
530 #define PPI_CMD_AD_CFG_DIR0_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_DIR0_MASK) >> PPI_CMD_AD_CFG_DIR0_SHIFT)
531 
532 /*
533  * AD_SEL0 (RW)
534  *
535  * 0 for data; 1 for address.
536  */
537 #define PPI_CMD_AD_CFG_AD_SEL0_MASK (0x4U)
538 #define PPI_CMD_AD_CFG_AD_SEL0_SHIFT (2U)
539 #define PPI_CMD_AD_CFG_AD_SEL0_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_AD_SEL0_SHIFT) & PPI_CMD_AD_CFG_AD_SEL0_MASK)
540 #define PPI_CMD_AD_CFG_AD_SEL0_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_AD_SEL0_MASK) >> PPI_CMD_AD_CFG_AD_SEL0_SHIFT)
541 
542 /*
543  * BYTE_SEL0 (RW)
544  *
545  * select one of the 4 bytes(11 for 31:24,  10 for 23:16, 01 for 15:8, 00 for 7:0)
546  */
547 #define PPI_CMD_AD_CFG_BYTE_SEL0_MASK (0x3U)
548 #define PPI_CMD_AD_CFG_BYTE_SEL0_SHIFT (0U)
549 #define PPI_CMD_AD_CFG_BYTE_SEL0_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_BYTE_SEL0_SHIFT) & PPI_CMD_AD_CFG_BYTE_SEL0_MASK)
550 #define PPI_CMD_AD_CFG_BYTE_SEL0_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_BYTE_SEL0_MASK) >> PPI_CMD_AD_CFG_BYTE_SEL0_SHIFT)
551 
552 /* Bitfield definition for register of struct array CMD: CTRL_CFG */
553 /*
554  * IO_CFG7 (RW)
555  *
556  */
557 #define PPI_CMD_CTRL_CFG_IO_CFG7_MASK (0x10000000UL)
558 #define PPI_CMD_CTRL_CFG_IO_CFG7_SHIFT (28U)
559 #define PPI_CMD_CTRL_CFG_IO_CFG7_SET(x) (((uint32_t)(x) << PPI_CMD_CTRL_CFG_IO_CFG7_SHIFT) & PPI_CMD_CTRL_CFG_IO_CFG7_MASK)
560 #define PPI_CMD_CTRL_CFG_IO_CFG7_GET(x) (((uint32_t)(x) & PPI_CMD_CTRL_CFG_IO_CFG7_MASK) >> PPI_CMD_CTRL_CFG_IO_CFG7_SHIFT)
561 
562 /*
563  * IO_CFG6 (RW)
564  *
565  */
566 #define PPI_CMD_CTRL_CFG_IO_CFG6_MASK (0x1000000UL)
567 #define PPI_CMD_CTRL_CFG_IO_CFG6_SHIFT (24U)
568 #define PPI_CMD_CTRL_CFG_IO_CFG6_SET(x) (((uint32_t)(x) << PPI_CMD_CTRL_CFG_IO_CFG6_SHIFT) & PPI_CMD_CTRL_CFG_IO_CFG6_MASK)
569 #define PPI_CMD_CTRL_CFG_IO_CFG6_GET(x) (((uint32_t)(x) & PPI_CMD_CTRL_CFG_IO_CFG6_MASK) >> PPI_CMD_CTRL_CFG_IO_CFG6_SHIFT)
570 
571 /*
572  * IO_CFG5 (RW)
573  *
574  */
575 #define PPI_CMD_CTRL_CFG_IO_CFG5_MASK (0x100000UL)
576 #define PPI_CMD_CTRL_CFG_IO_CFG5_SHIFT (20U)
577 #define PPI_CMD_CTRL_CFG_IO_CFG5_SET(x) (((uint32_t)(x) << PPI_CMD_CTRL_CFG_IO_CFG5_SHIFT) & PPI_CMD_CTRL_CFG_IO_CFG5_MASK)
578 #define PPI_CMD_CTRL_CFG_IO_CFG5_GET(x) (((uint32_t)(x) & PPI_CMD_CTRL_CFG_IO_CFG5_MASK) >> PPI_CMD_CTRL_CFG_IO_CFG5_SHIFT)
579 
580 /*
581  * IO_CFG4 (RW)
582  *
583  */
584 #define PPI_CMD_CTRL_CFG_IO_CFG4_MASK (0x10000UL)
585 #define PPI_CMD_CTRL_CFG_IO_CFG4_SHIFT (16U)
586 #define PPI_CMD_CTRL_CFG_IO_CFG4_SET(x) (((uint32_t)(x) << PPI_CMD_CTRL_CFG_IO_CFG4_SHIFT) & PPI_CMD_CTRL_CFG_IO_CFG4_MASK)
587 #define PPI_CMD_CTRL_CFG_IO_CFG4_GET(x) (((uint32_t)(x) & PPI_CMD_CTRL_CFG_IO_CFG4_MASK) >> PPI_CMD_CTRL_CFG_IO_CFG4_SHIFT)
588 
589 /*
590  * IO_CFG3 (RW)
591  *
592  */
593 #define PPI_CMD_CTRL_CFG_IO_CFG3_MASK (0x1000U)
594 #define PPI_CMD_CTRL_CFG_IO_CFG3_SHIFT (12U)
595 #define PPI_CMD_CTRL_CFG_IO_CFG3_SET(x) (((uint32_t)(x) << PPI_CMD_CTRL_CFG_IO_CFG3_SHIFT) & PPI_CMD_CTRL_CFG_IO_CFG3_MASK)
596 #define PPI_CMD_CTRL_CFG_IO_CFG3_GET(x) (((uint32_t)(x) & PPI_CMD_CTRL_CFG_IO_CFG3_MASK) >> PPI_CMD_CTRL_CFG_IO_CFG3_SHIFT)
597 
598 /*
599  * IO_CFG2 (RW)
600  *
601  */
602 #define PPI_CMD_CTRL_CFG_IO_CFG2_MASK (0x100U)
603 #define PPI_CMD_CTRL_CFG_IO_CFG2_SHIFT (8U)
604 #define PPI_CMD_CTRL_CFG_IO_CFG2_SET(x) (((uint32_t)(x) << PPI_CMD_CTRL_CFG_IO_CFG2_SHIFT) & PPI_CMD_CTRL_CFG_IO_CFG2_MASK)
605 #define PPI_CMD_CTRL_CFG_IO_CFG2_GET(x) (((uint32_t)(x) & PPI_CMD_CTRL_CFG_IO_CFG2_MASK) >> PPI_CMD_CTRL_CFG_IO_CFG2_SHIFT)
606 
607 /*
608  * IO_CFG1 (RW)
609  *
610  */
611 #define PPI_CMD_CTRL_CFG_IO_CFG1_MASK (0x10U)
612 #define PPI_CMD_CTRL_CFG_IO_CFG1_SHIFT (4U)
613 #define PPI_CMD_CTRL_CFG_IO_CFG1_SET(x) (((uint32_t)(x) << PPI_CMD_CTRL_CFG_IO_CFG1_SHIFT) & PPI_CMD_CTRL_CFG_IO_CFG1_MASK)
614 #define PPI_CMD_CTRL_CFG_IO_CFG1_GET(x) (((uint32_t)(x) & PPI_CMD_CTRL_CFG_IO_CFG1_MASK) >> PPI_CMD_CTRL_CFG_IO_CFG1_SHIFT)
615 
616 /*
617  * IO_CFG0 (RW)
618  *
619  * for OUT, it defines the output value(0 or 1);
620  * for IN, it defines whether to wait for ready(ready polarity is defined in ctrl_pad_pol)
621  */
622 #define PPI_CMD_CTRL_CFG_IO_CFG0_MASK (0x1U)
623 #define PPI_CMD_CTRL_CFG_IO_CFG0_SHIFT (0U)
624 #define PPI_CMD_CTRL_CFG_IO_CFG0_SET(x) (((uint32_t)(x) << PPI_CMD_CTRL_CFG_IO_CFG0_SHIFT) & PPI_CMD_CTRL_CFG_IO_CFG0_MASK)
625 #define PPI_CMD_CTRL_CFG_IO_CFG0_GET(x) (((uint32_t)(x) & PPI_CMD_CTRL_CFG_IO_CFG0_MASK) >> PPI_CMD_CTRL_CFG_IO_CFG0_SHIFT)
626 
627 
628 
629 /* CS register group index macro definition */
630 #define PPI_CS_0 (0UL)
631 #define PPI_CS_1 (1UL)
632 #define PPI_CS_2 (2UL)
633 #define PPI_CS_3 (3UL)
634 
635 /* CMD register group index macro definition */
636 #define PPI_CMD_0 (0UL)
637 #define PPI_CMD_1 (1UL)
638 #define PPI_CMD_2 (2UL)
639 #define PPI_CMD_3 (3UL)
640 #define PPI_CMD_4 (4UL)
641 #define PPI_CMD_5 (5UL)
642 #define PPI_CMD_6 (6UL)
643 #define PPI_CMD_7 (7UL)
644 #define PPI_CMD_8 (8UL)
645 #define PPI_CMD_9 (9UL)
646 #define PPI_CMD_10 (10UL)
647 #define PPI_CMD_11 (11UL)
648 #define PPI_CMD_12 (12UL)
649 #define PPI_CMD_13 (13UL)
650 #define PPI_CMD_14 (14UL)
651 #define PPI_CMD_15 (15UL)
652 #define PPI_CMD_16 (16UL)
653 #define PPI_CMD_17 (17UL)
654 #define PPI_CMD_18 (18UL)
655 #define PPI_CMD_19 (19UL)
656 #define PPI_CMD_20 (20UL)
657 #define PPI_CMD_21 (21UL)
658 #define PPI_CMD_22 (22UL)
659 #define PPI_CMD_23 (23UL)
660 #define PPI_CMD_24 (24UL)
661 #define PPI_CMD_25 (25UL)
662 #define PPI_CMD_26 (26UL)
663 #define PPI_CMD_27 (27UL)
664 #define PPI_CMD_28 (28UL)
665 #define PPI_CMD_29 (29UL)
666 #define PPI_CMD_30 (30UL)
667 #define PPI_CMD_31 (31UL)
668 #define PPI_CMD_32 (32UL)
669 #define PPI_CMD_33 (33UL)
670 #define PPI_CMD_34 (34UL)
671 #define PPI_CMD_35 (35UL)
672 #define PPI_CMD_36 (36UL)
673 #define PPI_CMD_37 (37UL)
674 #define PPI_CMD_38 (38UL)
675 #define PPI_CMD_39 (39UL)
676 #define PPI_CMD_40 (40UL)
677 #define PPI_CMD_41 (41UL)
678 #define PPI_CMD_42 (42UL)
679 #define PPI_CMD_43 (43UL)
680 #define PPI_CMD_44 (44UL)
681 #define PPI_CMD_45 (45UL)
682 #define PPI_CMD_46 (46UL)
683 #define PPI_CMD_47 (47UL)
684 #define PPI_CMD_48 (48UL)
685 #define PPI_CMD_49 (49UL)
686 #define PPI_CMD_50 (50UL)
687 #define PPI_CMD_51 (51UL)
688 #define PPI_CMD_52 (52UL)
689 #define PPI_CMD_53 (53UL)
690 #define PPI_CMD_54 (54UL)
691 #define PPI_CMD_55 (55UL)
692 #define PPI_CMD_56 (56UL)
693 #define PPI_CMD_57 (57UL)
694 #define PPI_CMD_58 (58UL)
695 #define PPI_CMD_59 (59UL)
696 #define PPI_CMD_61 (61UL)
697 #define PPI_CMD_62 (62UL)
698 #define PPI_CMD_63 (63UL)
699 
700 
701 #endif /* HPM_PPI_H */
702