1 /** 2 ****************************************************************************** 3 * @file bl808_psram_uhs.h 4 * @version V1.0 5 * @date 6 * @brief This file is the standard driver header file 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __BL808_PSRAM_UHS_H__ 37 #define __BL808_PSRAM_UHS_H__ 38 39 #include "psram_uhs_reg.h" 40 #include "bl808_common.h" 41 42 /** @addtogroup BL808_Peripheral_Driver 43 * @{ 44 */ 45 46 /** @addtogroup PSRAM_UHS 47 * @{ 48 */ 49 50 /** @defgroup PSRAM_UHS_Public_Types 51 * @{ 52 */ 53 54 /** 55 * @brief Psram UHS Size 56 */ 57 typedef enum { 58 PSRAM_MEM_SIZE_4MB = 0x03, /*!< PSRAM Memory Size 4M */ 59 PSRAM_MEM_SIZE_8MB = 0x07, /*!< PSRAM Memory Size 8M */ 60 PSRAM_MEM_SIZE_16MB = 0x0f, /*!< PSRAM Memory Size 16M */ 61 PSRAM_MEM_SIZE_32MB = 0x1f, /*!< PSRAM Memory Size 32M */ 62 PSRAM_MEM_SIZE_64MB = 0x3f, /*!< PSRAM Memory Size 64M */ 63 } PSRAM_UHS_Mem_Size_Type; 64 65 /** 66 * @brief Psram UHS Page Type 67 */ 68 typedef enum { 69 PSRAM_PAGE_SIZE_2KB = 0x0B, /*!< PSRAM Page Size 2KB */ 70 PSRAM_PAGE_SIZE_4KB = 0x16, /*!< PSRAM Page Size 4KB */ 71 } PSRAM_UHS_Page_Size_Type; 72 73 /** 74 * @brief Psram UHS Burst Size 75 */ 76 typedef enum { 77 PSRAM_UHS_WARP_BURST_64, /*!< PSRAM Warp Burst Size 64 */ 78 PSRAM_UHS_WARP_BURST_32, /*!< PSRAM Warp Burst Size 32 */ 79 PSRAM_UHS_WARP_BURST_16, /*!< PSRAM Warp Burst Size 16 */ 80 PSRAM_UHS_WARP_BURST_NONE, /*!< PSRAM Warp Burst NONE */ 81 PSRAM_UHS_WARP_BURST_NO_CHANGE, /*!< Not change this value */ 82 } PSRAM_UHS_WARP_BURST_Type; 83 84 /** 85 * @brief Psram UHS Driver Strength 86 */ 87 typedef enum { 88 PSRAM_UHS_DRIVER_ST_34P3_PDPU = 0x1, /*!< 34.3 PD/PU */ 89 PSRAM_UHS_DRIVER_ST_40_PDPU = 0x2, /*!< 40 PD/PU */ 90 PSRAM_UHS_DRIVER_ST_48_PDPU = 0x3, /*!< 48 PD/PU */ 91 PSRAM_UHS_DRIVER_ST_60_PDPU = 0x4, /*!< 60 PD/PU */ 92 PSRAM_UHS_DRIVER_ST_80_PDPU = 0x6, /*!< 80 PD/PU */ 93 PSRAM_UHS_DRIVER_ST_34P3_PD_40_PU = 0x9, /*!< 34.3 PD & 40 PU */ 94 PSRAM_UHS_DRIVER_ST_40_PD_48_PU = 0xa, /*!< 40 PD & 48 PU */ 95 PSRAM_UHS_DRIVER_ST_34P3_PD_48_PU = 0xb, /*!< 34.3 PD & 48 PU */ 96 PSRAM_UHS_DRIVER_ST_NO_CHANGE = 0xf, /*!< Not change this value */ 97 } PSRAM_UHS_DRIVER_ST_Type; 98 99 /** 100 * @brief Psram UHS LATENCY 101 */ 102 typedef enum { 103 PSRAM_UHS_LATENCY_W10_R20_MAX_FRE_533_MHZ, /*!< MAX freq. = 533 MHz / Write LATENCY=10 / Read LATENCY=20 */ 104 PSRAM_UHS_LATENCY_W14_R29_MAX_FRE_800_MHZ, /*!< MAX freq. = 800 MHz / Write LATENCY=14 / Read LATENCY=29 */ 105 PSRAM_UHS_LATENCY_W16_R33_MAX_FRE_933_MHZ, /*!< MAX freq. = 933 MHz / Write LATENCY=16 / Read LATENCY=33 */ 106 PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ, /*!< MAX freq. = 1066 MHz / Write LATENCY=18 / Read LATENCY=37 */ 107 PSRAM_UHS_LATENCY_RESERVED, /*!< Reserved */ 108 PSRAM_UHS_LATENCY_W6_R16_MAX_FRE_400_MHZ, /*!< MAX freq. = 400 MHz / Write LATENCY=6 / Read LATENCY=16 */ 109 PSRAM_UHS_LATENCY_W5_R13_MAX_FRE_333_MHZ, /*!< MAX freq. = 333 MHz / Write LATENCY=5 / Read LATENCY=13 */ 110 PSRAM_UHS_LATENCY_W5_R9_MAX_FRE_200_MHZ, /*!< MAX freq. = 200 MHz / Write LATENCY=5 / Read LATENCY=9 */ 111 PSRAM_UHS_LATENCY_NO_CHANGE, /*!< Not change this value */ 112 } PSRAM_UHS_LATENCY_Type; 113 114 /** 115 * @brief Psram UHS CMD Type 116 */ 117 typedef enum { 118 PSRAM_UHS_CMD_SELF_REFRESH_IN, /*!< pSRAM self-refresh in command */ 119 PSRAM_UHS_CMD_SELF_REFRESH_EXIT, /*!< pSRAM self-refresh exit command */ 120 PSRAM_UHS_CMD_GLOBAL_RESET, /*!< pSRAM global reset command */ 121 PSRAM_UHS_CMD_ZQ_CAL_LONG, /*!<ZQ calibration, long> */ 122 PSRAM_UHS_CMD_ZQ_CAL_SHORT, /*!<ZQ calibration, short>*/ 123 PSRAM_UHS_CMD_ZQ_CAL_RESET, /*!<ZQ calibration,reset>*/ 124 } PSRAM_UHS_CMD_Type; 125 126 /** 127 * @brief PSRAM UHS Temperature 128 * 129 */ 130 typedef enum { 131 PSRAM_UHS_NORMAL_TEMP, 132 PSRAM_UHS_HIGH_TEMP, 133 } PSRAM_UHS_TEMP_Type; 134 135 /** 136 * @brief PSRAM_UHS_Cfg_Type 137 */ 138 typedef struct { 139 uint32_t pck_freq; /*!< pck frequency unit is MHZ */ 140 PSRAM_UHS_Mem_Size_Type psramMemSize; /*!< psram uhm memory size */ 141 PSRAM_UHS_Page_Size_Type psramPageSize; /*!< psram uhm page size */ 142 PSRAM_UHS_TEMP_Type isHighTem; /*!< auto refresh work temperature */ 143 } PSRAM_UHS_Cfg_Type; 144 145 /** 146 * @brief PSRAM_UHS_Phy_Latency_Pra_Type 147 */ 148 typedef struct { 149 uint8_t phy_rl_ana; /*!< phy_rl_ana */ 150 uint8_t phy_rl_dig; /*!< phy_rl_dig*/ 151 uint8_t phy_wl_ana; /*!< phy_wl_ana */ 152 uint8_t phy_wl_dig; /*!< phy_wl_dig*/ 153 uint8_t phy_wl_dq_ana; /*!< phy_wl_dq_ana */ 154 uint8_t phy_wl_dq_dig; /*!< phy_wl_dq_dig */ 155 156 uint8_t reg_timer_array_read; /*!< reg_timer_array_read */ 157 uint8_t reg_timer_array_write; /*!< reg_timer_array_write */ 158 uint8_t reg_timer_dqs_array_stop; /*!< reg_timer_dqs_array_stop */ 159 uint8_t reg_timer_dqs_start; /*!< reg_timer_dqs_start */ 160 161 uint8_t reg_timer_dqs_stop; /*!< reg_timer_dqs_stop */ 162 uint8_t reg_timer_reg_read; /*!< reg_timer_reg_read */ 163 uint8_t reg_timer_reg_write; /*!< reg_timer_reg_write */ 164 uint8_t reg_timer_auto_refresh; /*!< reg_timer_auto_refresh */ 165 166 uint16_t reg_timer_global_rst; /*!< reg_timer_global_rst */ 167 uint8_t reg_timer_self_refresh1_in; /*!< reg_timer_self_refresh1_in */ 168 uint8_t reg_timer_self_refresh1_exit; /*!< reg_timer_self_refresh1_exit */ 169 170 uint8_t reg_timer_reg_write_busy; /*!< reg_timer_reg_write_busy */ 171 uint8_t reg_timer_reg_read_busy; /*!< reg_timer_reg_read_busy */ 172 uint8_t reg_timer_arrary_write_busy; /*!< reg_timer_arrary_write_busy */ 173 uint8_t reg_timer_arrary_read_busy; /*!< reg_timer_arrary_read_busy */ 174 175 uint8_t en_rx_fe_dly; /*!< en_rx_fe_dly */ 176 uint8_t odt_sel_dly; /*!< odt_sel_dly */ 177 178 uint8_t reg_trc_cycle; /*!< reg_trc_cycle */ 179 uint8_t reg_trfc_cycle; /*!< reg_trfc_cycle */ 180 uint8_t reg_tcphr_cycle; /*!< reg_tcphr_cycle */ 181 uint8_t reg_tcphw_cycle; /*!< reg_tcphw_cycle */ 182 183 } PSRAM_UHS_Phy_Latency_Pra_Type; 184 185 /** 186 * @brief PSRAM_UHS_Write_Reg_Cfg_Type 187 */ 188 typedef struct { 189 PSRAM_UHS_DRIVER_ST_Type driver_st; /*!< driver strength */ 190 PSRAM_UHS_WARP_BURST_Type burst_size; /*!< burst size */ 191 PSRAM_UHS_LATENCY_Type lentency; /*!< lentency */ 192 } PSRAM_UHS_Write_Reg_Cfg_Type; 193 194 /*@} end of group PSRAM_UHS_Public_Types */ 195 196 /** @defgroup PSRAM_UHS_Public_Constants 197 * @{ 198 */ 199 200 /** @defgroup PSRAM_UHS_MEM_SIZE_TYPE 201 * @{ 202 */ 203 #define IS_PSRAM_UHS_MEM_SIZE_TYPE(type) (((type) == PSRAM_MEM_SIZE_4MB) || \ 204 ((type) == PSRAM_MEM_SIZE_8MB) || \ 205 ((type) == PSRAM_MEM_SIZE_16MB) || \ 206 ((type) == PSRAM_MEM_SIZE_32MB)) 207 208 /** @defgroup PSRAM_UHS_PAGE_SIZE_TYPE 209 * @{ 210 */ 211 #define IS_PSRAM_UHS_PAGE_SIZE_TYPE(type) (((type) == PSRAM_PAGE_SIZE_2KB) || \ 212 ((type) == PSRAM_PAGE_SIZE_4KB)) 213 214 /** @defgroup PSRAM_UHS_WARP_BURST_TYPE 215 * @{ 216 */ 217 #define IS_PSRAM_UHS_WARP_BURST_TYPE(type) (((type) == PSRAM_UHS_WARP_BURST_64) || \ 218 ((type) == PSRAM_UHS_WARP_BURST_32) || \ 219 ((type) == PSRAM_UHS_WARP_BURST_16)) 220 221 /** @defgroup PSRAM_UHS_DRIVER_ST_TYPE 222 * @{ 223 */ 224 #define IS_PSRAM_UHS_DRIVER_ST_TYPE(type) (((type) == PSRAM_UHS_DRIVER_ST_34P3_PUPU) || \ 225 ((type) == PSRAM_UHS_DRIVER_ST_40_PUPU) || \ 226 ((type) == PSRAM_UHS_DRIVER_ST_48_PUPU) || \ 227 ((type) == PSRAM_UHS_DRIVER_ST_60_PUPU) || \ 228 ((type) == PSRAM_UHS_DRIVER_ST_80_PUPU) || \ 229 ((type) == PSRAM_UHS_DRIVER_ST_34P3_PD_40_PU) || \ 230 ((type) == PSRAM_UHS_DRIVER_ST_40_PD_48_PU) || \ 231 ((type) == PSRAM_UHS_DRIVER_ST_34P3_PD_48_PU)) 232 233 /** @defgroup PSRAM_UHS_LATENCY_TYPE 234 * @{ 235 */ 236 #define IS_PSRAM_UHS_LATENCY_TYPE(type) (((type) == PSRAM_UHS_LATENCY_W10_R20_MAX_FRE_533_MHZ) || \ 237 ((type) == PSRAM_UHS_LATENCY_W14_R29_MAX_FRE_800_MHZ) || \ 238 ((type) == PSRAM_UHS_LATENCY_W16_R33_MAX_FRE_933_MHZ) || \ 239 ((type) == PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ) || \ 240 ((type) == PSRAM_UHS_LATENCY_W6_R16_MAX_FRE_400_MHZ) || \ 241 ((type) == PSRAM_UHS_LATENCY_W5_R13_MAX_FRE_333_MHZ) || \ 242 ((type) == PSRAM_UHS_LATENCY_W5_R9_MAX_FRE_200_MHZ)) 243 /** @defgroup PSRAM_UHS_CMD_Type 244 * @{ 245 */ 246 #define IS_PSRAM_UHS_CMD_TYPE(type) (((type) == PSRAM_UHS_CMD_SELF_REFRESH_IN) || \ 247 ((type) == PSRAM_UHS_CMD_SELF_REFRESH_EXIT) || \ 248 ((type) == PSRAM_UHS_CMD_GLOBAL_RESET) 249 250 /*@} end of group PSRAM_UHS_Public_Constants */ 251 252 /** @defgroup PSRAM_UHS_Public_Macros 253 * @{ 254 */ 255 256 /*@} end of group PSRAM_UHS_Public_Macros */ 257 258 /** @defgroup PSRAM_UHS_Public_Functions 259 * @{ 260 */ 261 void Psram_UHS_Init(PSRAM_UHS_Cfg_Type *cfg); 262 int PSram_UHS_Read_Reg(uint32_t reg_addr, uint8_t *regVal); 263 int PSram_UHS_Write_Reg(PSRAM_UHS_Write_Reg_Cfg_Type *regCfg); 264 int PSram_UHS_Construct_Cmd(PSRAM_UHS_CMD_Type cmd); 265 void Psram_UHS_x16_Init(uint32_t uhs_pll_clk); 266 void Psram_UHS_x16_Init_Override(PSRAM_UHS_Cfg_Type *cfg); 267 /*@} end of group PSRAM_UHS_Public_Functions */ 268 269 /*@} end of group PSRAM_UHS */ 270 271 /*@} end of group BL808_Peripheral_Driver */ 272 273 #endif /* __BL808_PSRAM_UHS_H__ */ 274