1 /**
2 ******************************************************************************
3 * @file bl616_psram_ctrl.c
4 * @version V1.0
5 * @date
6 * @brief This file is the standard driver c file
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>© COPYRIGHT(c) 2022 Bouffalo Lab</center></h2>
11 *
12 * Redistribution and use in source and binary forms, with or without modification,
13 * are permitted provided that the following conditions are met:
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 ******************************************************************************
35 */
36 #include "bl616_glb.h"
37 #include "bl616_psram.h"
38 #include "psram_reg.h"
39
40 /** @addtogroup BL616_Peripheral_Driver
41 * @{
42 */
43
44 /** @addtogroup PSRAM_CTRL
45 * @{
46 */
47
48 /** @defgroup PSRAM_CTRL_Private_Macros
49 * @{
50 */
51 #define PSRAM_X8_CTRL_WAIT_TIMEOUT 1000
52 /*@} end of group PSRAM_CTRL_Private_Macros */
53
54 /** @defgroup PSRAM_CTRL_Private_Types
55 * @{
56 */
57
58 /*@} end of group PSRAM_CTRL_Private_Types */
59
60 /** @defgroup PSRAM_CTRL_Private_Variables
61 * @{
62 */
63
64 /*@} end of group PSRAM_CTRL_Private_Variables */
65
66 /** @defgroup PSRAM_CTRL_Global_Variables
67 * @{
68 */
69
70 /*@} end of group PSRAM_CTRL_Global_Variables */
71
72 /** @defgroup PSRAM_CTRL_Private_Fun_Declaration
73 * @{
74 */
75
76 /*@} end of group PSRAM_CTRL_Private_Fun_Declaration */
77
78 /** @defgroup PSRAM_CTRL_Private_Functions
79 * @{
80 */
81
82 /*@} end of group PSRAM_CTRL_Private_Functions */
83
84 /** @defgroup PSRAM_CTRL_Public_Functions
85 * @{
86 */
87
88 /****************************************************************************/ /**
89 * @brief Init PSRAM controller
90 *
91 * @param PSRAM_ID: PSRAM vendor
92 * @param psramCtrlCfg: PSRAM controller IO type
93 *
94 * @return None
95 *
96 *******************************************************************************/
PSram_Ctrl_Init(PSRAM_ID_Type PSRAM_ID,PSRAM_Ctrl_Cfg_Type * psramCtrlCfg)97 void PSram_Ctrl_Init(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Cfg_Type *psramCtrlCfg)
98 {
99 uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
100 uint32_t tmpVal = 0;
101
102 CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));
103 CHECK_PARAM(IS_PSRAM_CTRL_CFG_TYPE(psramCtrlCfg));
104
105 //PSRAM initial sequence
106 arch_delay_us(150);
107 /* set psram dqs delay 0xfff0 */
108 tmpVal = BL_RD_REG(psram_base, PSRAM_ROUGH_DELAY_CTRL5);
109 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_ROUGH_SEL_I_DQS0, psramCtrlCfg->dqs_delay);
110 BL_WR_REG(psram_base, PSRAM_ROUGH_DELAY_CTRL5, tmpVal);
111
112 /* Set vendor and mode for psram controller */
113 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
114 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_PCK_S_DIV, 0x1);
115 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_VENDOR_SEL, psramCtrlCfg->vendor);
116 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_X16_MODE, psramCtrlCfg->ioMode);
117 BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);
118
119 tmpVal = BL_RD_REG(psram_base, PSRAM_MANUAL_CONTROL2);
120 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_ADDR_MASK, psramCtrlCfg->size);
121 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_DQS_REL_VAL, 0x1f);
122 BL_WR_REG(psram_base, PSRAM_MANUAL_CONTROL2, tmpVal);
123
124 if (psramCtrlCfg->vendor == PSRAM_CTRL_VENDOR_WINBOND && psramCtrlCfg->ioMode == PSRAM_CTRL_X16_MODE && psramCtrlCfg->size == PSRAM_SIZE_16MB) {
125 //If using W957D6NKR, must set reg_wb_hyper3 bit to 1
126 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
127 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_WB_HYPER3);
128 BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);
129 }
130 }
131
132 /****************************************************************************/ /**
133 * @brief PSRAM Ctrl request access
134 *
135 * @param PSRAM_ID: PSRAM ID
136 *
137 * @return None
138 *
139 *******************************************************************************/
PSram_Ctrl_Request(PSRAM_ID_Type PSRAM_ID)140 static void PSram_Ctrl_Request(PSRAM_ID_Type PSRAM_ID)
141 {
142 uint32_t tmpVal = 0;
143 uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
144 uint32_t time_out = 0;
145
146 //start configure request
147 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
148 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_CONFIG_REQ, 1);
149 BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);
150
151 //Waiting for the authorization
152 do {
153 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
154 if (time_out++ > PSRAM_X8_CTRL_WAIT_TIMEOUT) {
155 break;
156 }
157 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_REG_CONFIG_GNT));
158 }
159
160 /****************************************************************************/ /**
161 * @brief PSRAM Ctrl release access
162 *
163 * @param PSRAM_ID: PSRAM ID
164 *
165 * @return None
166 *
167 *******************************************************************************/
PSram_Ctrl_Release(PSRAM_ID_Type PSRAM_ID)168 static void PSram_Ctrl_Release(PSRAM_ID_Type PSRAM_ID)
169 {
170 uint32_t tmpVal = 0;
171 uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
172
173 //clear start configure request
174 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
175 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_CONFIG_REQ, 0);
176 BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);
177 }
178
179 /****************************************************************************/ /**
180 * @brief Read register for winbond PSRAM
181 *
182 * @param PSRAM_ID: PSRAM ID
183 * @param reg_addr: PSRAM Register ID CR0 or CR1
184 * @param regVal: read Reister value
185 *
186 * @return SUCCESS or TIMEOUT
187 *
188 *******************************************************************************/
PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID,PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr,uint16_t * regVal)189 BL_Err_Type PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, uint16_t *regVal)
190 {
191 uint32_t tmpVal = 0;
192 uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
193 uint32_t time_out = 0;
194
195 CHECK_PARAM(IS_PSRAM_WINBON_CFG_TYPE(reg_cfg));
196 CHECK_PARAM(IS_PSRAM_CTRL_WINBOND_CFG_REG_TYPE(reg_addr));
197 CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));
198
199 PSram_Ctrl_Request(PSRAM_ID);
200
201 //configure pSRAM register,select reg_addr CR0 or CR1
202 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
203 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_REG_SEL, reg_addr);
204 BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);
205
206 //start psram configure
207 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
208 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_CONFIG_R_PUSLE, 1);
209 BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);
210
211 //waiting confiure complete
212 do {
213 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
214 if (time_out++ > PSRAM_X8_CTRL_WAIT_TIMEOUT) {
215 return TIMEOUT;
216 }
217 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_R_DONE));
218
219 //read reg data form sts_config_read
220 tmpVal = BL_RD_REG(psram_base, PSRAM_MANUAL_CONTROL);
221 *regVal = (uint16_t)(tmpVal >> 16);
222
223 PSram_Ctrl_Release(PSRAM_ID);
224
225 return SUCCESS;
226 }
227
228 /****************************************************************************/ /**
229 * @brief write register for winbond PSRAM
230 *
231 * @param PSRAM_ID: PSRAM ID
232 * @param reg_addr: PSRAM Register ID CR0 or CR1
233 * @param reg_cfg: winbond configuration
234 *
235 * @return SUCCESS or TIMEOUT
236 *
237 *******************************************************************************/
PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID,PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr,PSRAM_Winbond_Cfg_Type * reg_cfg)238 BL_Err_Type PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, PSRAM_Winbond_Cfg_Type *reg_cfg)
239 {
240 uint32_t tmpVal = 0;
241 uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
242 PSRAM_Ctrl_Size_Type psramDensity;
243 uint32_t time_out = 0;
244
245 CHECK_PARAM(IS_PSRAM_WINBON_CFG_TYPE(reg_cfg));
246 CHECK_PARAM(IS_PSRAM_CTRL_WINBOND_CFG_REG_TYPE(reg_addr));
247 CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));
248
249 PSram_Ctrl_Request(PSRAM_ID);
250
251 //configure Winbond register
252 tmpVal = BL_RD_REG(psram_base, PSRAM_WINBOND_PSRAM_CONFIGURE);
253
254 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_LATENCY, reg_cfg->latency);
255 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_DRIVE_ST, reg_cfg->driveStrength);
256 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_HYBRID_EN, reg_cfg->brustType);
257
258 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_BURST_LENGTH, reg_cfg->brustLen);
259 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_FIX_LATENCY, reg_cfg->fixedLatency);
260
261 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_DPD_DIS, reg_cfg->disDeepPowerDownMode);
262
263 psramDensity = BL_GET_REG_BITS_VAL(BL_RD_REG(psram_base, PSRAM_MANUAL_CONTROL2), PSRAM_REG_ADDR_MASK);
264
265 if (psramDensity == PSRAM_SIZE_4MB) {
266 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_PASR, reg_cfg->PASR);
267 } else {
268 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_PASR, reg_cfg->PASR << 2);
269 }
270
271 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_HYBRID_SLP, reg_cfg->hybridSleepMode);
272
273 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_IPD, reg_cfg->inputPowerDownMode);
274 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_MCLK_TYPE, reg_cfg->clockType);
275 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_LINEAR_DIS, reg_cfg->linear_dis);
276 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_SW_RST, reg_cfg->rst);
277
278 BL_WR_REG(psram_base, PSRAM_WINBOND_PSRAM_CONFIGURE, tmpVal);
279
280 //configure pSRAM register,select reg_addr CR0 or CR1
281 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
282 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_REG_SEL, reg_addr);
283 BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);
284
285 //start psram configure
286 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
287 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_CONFIG_W_PUSLE, 1);
288 BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);
289
290 //waiting confiure complete
291 do {
292 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
293 if (time_out++ > PSRAM_X8_CTRL_WAIT_TIMEOUT) {
294 return TIMEOUT;
295 }
296 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_W_DONE));
297
298 PSram_Ctrl_Release(PSRAM_ID);
299
300 return SUCCESS;
301 }
302
303 /****************************************************************************/ /**
304 * @brief Read register for APmemory PSRAM
305 *
306 * @param PSRAM_ID: PSRAM ID
307 * @param reg_addr: PSRAM Register ID CR0 or CR1
308 * @param regVal: read Reister value
309 *
310 * @return SUCCESS or TIMEOUT
311 *
312 *******************************************************************************/
PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID,PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr,uint16_t * regVal)313 BL_Err_Type PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, uint16_t *regVal)
314 {
315 uint32_t tmpVal = 0;
316 uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
317 uint32_t time_out = 0;
318
319 CHECK_PARAM(IS_PSRAM_WINBON_CFG_TYPE(reg_cfg));
320 CHECK_PARAM(IS_PSRAM_CTRL_APMEM_CFG_REG_TYPE(reg_addr));
321 CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));
322
323 PSram_Ctrl_Request(PSRAM_ID);
324
325 //configure pSRAM register,select reg_addr CR0 or CR1
326 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
327 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_REG_SEL, reg_addr);
328 BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);
329
330 //start psram configure
331 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
332 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_CONFIG_R_PUSLE, 1);
333 BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);
334
335 //waiting confiure complete
336 do {
337 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
338 if (time_out++ > PSRAM_X8_CTRL_WAIT_TIMEOUT) {
339 return TIMEOUT;
340 }
341 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_R_DONE));
342
343 //read reg data form sts_config_read
344 tmpVal = BL_RD_REG(psram_base, PSRAM_MANUAL_CONTROL);
345 *regVal = (uint16_t)(tmpVal >> 16);
346
347 PSram_Ctrl_Release(PSRAM_ID);
348
349 return SUCCESS;
350 }
351
352 /****************************************************************************/ /**
353 * @brief write register for Apmemory PSRAM
354 *
355 * @param PSRAM_ID: PSRAM ID
356 * @param reg_addr: PSRAM Register ID
357 * @param reg_cfg: winbond configuration
358 *
359 * @return SUCCESS or TIMEOUT
360 *
361 *******************************************************************************/
PSram_Ctrl_ApMem_Write_Reg(PSRAM_ID_Type PSRAM_ID,PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr,PSRAM_APMemory_Cfg_Type * reg_cfg)362 BL_Err_Type PSram_Ctrl_ApMem_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, PSRAM_APMemory_Cfg_Type *reg_cfg)
363 {
364 uint32_t tmpVal = 0;
365 uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
366 uint32_t time_out = 0;
367
368 CHECK_PARAM(IS_PSRAM_WINBON_CFG_TYPE(reg_cfg));
369 CHECK_PARAM(IS_PSRAM_CTRL_APMEM_CFG_REG_TYPE(reg_addr));
370 CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));
371
372 PSram_Ctrl_Request(PSRAM_ID);
373
374 //configure Winbond register
375 tmpVal = BL_RD_REG(psram_base, PSRAM_APMEMORY_PSRAM_CONFIGURE);
376
377 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_R_LATENCY_TYPE, reg_cfg->fixedLatency);
378 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_R_LATENCY_CODE, reg_cfg->readLatency);
379 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_RF, reg_cfg->refreshFreq);
380 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_DRIVE_ST, reg_cfg->driveStrength);
381 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_W_LATENCY_CODE, reg_cfg->writeLatency);
382 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_PASR, reg_cfg->PASR);
383 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_SLEEP, reg_cfg->halfSleepModeEnable);
384 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_DPD, reg_cfg->deepPowerDownModeEnable);
385 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_RBX, reg_cfg->crossBoundaryEnable);
386 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_BURST_TYPE, reg_cfg->brustType);
387 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_AP_BURST_LENGTH, reg_cfg->brustLen);
388
389 BL_WR_REG(psram_base, PSRAM_APMEMORY_PSRAM_CONFIGURE, tmpVal);
390
391 //configure pSRAM register,select reg_addr CR0 or CR1
392 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
393 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_REG_SEL, reg_addr);
394 BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);
395
396 //start psram configure
397 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
398 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_CONFIG_W_PUSLE, 1);
399 BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);
400
401 //waiting confiure complete
402 do {
403 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
404 if (time_out++ > PSRAM_X8_CTRL_WAIT_TIMEOUT) {
405 return TIMEOUT;
406 }
407 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_W_DONE));
408
409 PSram_Ctrl_Release(PSRAM_ID);
410
411 return SUCCESS;
412 }
413
414 /****************************************************************************/ /**
415 * @brief write register for apmemory PSRAM
416 *
417 * @param PSRAM_ID: apmemory configuration register type
418 *
419 * @return None
420 *
421 *******************************************************************************/
PSram_Ctrl_ApMem_Reset(PSRAM_ID_Type PSRAM_ID)422 void PSram_Ctrl_ApMem_Reset(PSRAM_ID_Type PSRAM_ID)
423 {
424 uint32_t tmpVal = 0;
425 uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
426
427 CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));
428
429 tmpVal = BL_RD_REG(psram_base, PSRAM_APMEMORY_PSRAM_CONFIGURE);
430 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_GLB_RESET_PULSE);
431 BL_WR_REG(psram_base, PSRAM_APMEMORY_PSRAM_CONFIGURE, tmpVal);
432 }
433
434 /****************************************************************************/ /**
435 * @brief write register for Winbond PSRAM
436 *
437 * @param PSRAM_ID: Winbond configuration register type
438 *
439 * @return None
440 *
441 *******************************************************************************/
PSram_Ctrl_Winbond_Reset(PSRAM_ID_Type PSRAM_ID)442 void PSram_Ctrl_Winbond_Reset(PSRAM_ID_Type PSRAM_ID)
443 {
444 uint32_t tmpVal = 0;
445 uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
446
447 CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));
448
449 tmpVal = BL_RD_REG(psram_base, PSRAM_WINBOND_PSRAM_CONFIGURE);
450 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_WB_SW_RST);
451 BL_WR_REG(psram_base, PSRAM_WINBOND_PSRAM_CONFIGURE, tmpVal);
452 }
453
454 /****************************************************************************/ /**
455 * @brief set clk type diff/single
456 *
457 * @param PSRAM_ID: PSRAM ID
458 * @param clkSel: Clock Type
459 *
460 * @return None
461 *
462 *******************************************************************************/
PSram_Ctrl_CK_Sel(PSRAM_ID_Type PSRAM_ID,PSRAM_Clock_Type clkSel)463 void PSram_Ctrl_CK_Sel(PSRAM_ID_Type PSRAM_ID, PSRAM_Clock_Type clkSel)
464 {
465 uint32_t tmpVal = 0;
466 uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
467
468 CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));
469
470 tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
471
472 if (clkSel == PSRAM_CLOCK_DIFF) {
473 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_CLKN_FREE);
474 } else {
475 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_REG_CLKN_FREE);
476 }
477
478 BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);
479 }
480
481 /****************************************************************************/ /**
482 * @brief get timeout status
483 *
484 * @param PSRAM_ID: PSRAM ID
485 *
486 * @return FLAG
487 *
488 *******************************************************************************/
PSram_Ctrl_Get_Timeout_Flag(PSRAM_ID_Type PSRAM_ID)489 uint8_t PSram_Ctrl_Get_Timeout_Flag(PSRAM_ID_Type PSRAM_ID)
490 {
491 uint32_t tmpVal = 0;
492 uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
493
494 CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));
495
496 tmpVal = BL_RD_REG(psram_base, PSRAM_TIMEOUT_REG);
497
498 return BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_TIMEOUT);
499 }
500
501 /****************************************************************************/ /**
502 * @brief PSram_Ctrl_Clear_Timout_Flag
503 *
504 * @param PSRAM_ID: PSRAM ID
505 *
506 * @return None
507 *
508 *******************************************************************************/
PSram_Ctrl_Clear_Timout_Flag(PSRAM_ID_Type PSRAM_ID)509 void PSram_Ctrl_Clear_Timout_Flag(PSRAM_ID_Type PSRAM_ID)
510 {
511 uint32_t tmpVal = 0;
512 uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
513
514 CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));
515
516 tmpVal = BL_RD_REG(psram_base, PSRAM_TIMEOUT_REG);
517 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_TIMEOUT_CLR);
518 BL_WR_REG(psram_base, PSRAM_TIMEOUT_REG, tmpVal);
519
520 tmpVal = BL_RD_REG(psram_base, PSRAM_TIMEOUT_REG);
521 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_REG_TIMEOUT_CLR);
522 BL_WR_REG(psram_base, PSRAM_TIMEOUT_REG, tmpVal);
523 }
524
525 /****************************************************************************/ /**
526 * @brief set clk type diff/single
527 *
528 * @param PSRAM_ID: PSRAM ID
529 * @param enable: Enable or not
530 * @param timeoutThr: timeoutThr
531 *
532 * @return None
533 *
534 *******************************************************************************/
PSram_Ctrl_Debug_Timout(PSRAM_ID_Type PSRAM_ID,uint8_t enable,uint32_t timeoutThr)535 void PSram_Ctrl_Debug_Timout(PSRAM_ID_Type PSRAM_ID, uint8_t enable, uint32_t timeoutThr)
536 {
537 uint32_t tmpVal = 0;
538 uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
539
540 CHECK_PARAM(IS_PSRAM_ID_TYPE(PSRAM_ID));
541
542 tmpVal = BL_RD_REG(psram_base, PSRAM_TIMEOUT_REG);
543
544 if (enable) {
545 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_REG_TIMEOUT_EN);
546 } else {
547 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_REG_TIMEOUT_EN);
548 }
549
550 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_TIMEOUT_CNT, timeoutThr);
551
552 BL_WR_REG(psram_base, PSRAM_TIMEOUT_REG, tmpVal);
553 }
554
555 /*@} end of group PSRAM_CTRL_Public_Functions */
556
557 /*@} end of group PSRAM_CTRL */
558
559 /*@} end of group BL616_Peripheral_Driver */
560