1 /**
2 ******************************************************************************
3 * @file bl808_psram_uhs.c
4 * @version V1.0
5 * @date
6 * @brief This file is the standard driver c file
7 ******************************************************************************
8 * @attention
9 *
10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
11 *
12 * Redistribution and use in source and binary forms, with or without modification,
13 * are permitted provided that the following conditions are met:
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 * this list of conditions and the following disclaimer in the documentation
18 * and/or other materials provided with the distribution.
19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 ******************************************************************************
35 */
36
37 #include "bl808_psram_uhs.h"
38 #include "bl808_uhs_phy.h"
39 #include "bl808_common.h"
40 #include "bl808_glb.h"
41 #include "psram_uhs_reg.h"
42
43 /** @addtogroup BL808_Peripheral_Driver
44 * @{
45 */
46
47 /** @addtogroup PSRAM_UHS
48 * @{
49 */
50
51 /** @defgroup PSRAM_UHS_Private_Macros
52 * @{
53 */
54 #define PSRAM_UHS_RW_TIMEOUT 0xffffffff
55 /*@} end of group PSRAM_UHS_Private_Macros */
56
57 /** @defgroup PSRAM_UHS_Private_Types
58 * @{
59 */
60
61 /*@} end of group PSRAM_UHS_Private_Types */
62
63 /** @defgroup PSRAM_UHS_Private_Variables
64 * @{
65 */
66
67 /*@} end of group PSRAM_UHS_Private_Variables */
68
69 /** @defgroup PSRAM_UHS_Global_Variables
70 * @{
71 */
72
73 /*@} end of group PSRAM_UHS_Global_Variables */
74
75 /** @defgroup PSRAM_UHS_Private_Fun_Declaration
76 * @{
77 */
78
79 /*@} end of group PSRAM_UHS_Private_Fun_Declaration */
80
81 /** @defgroup PSRAM_UHS_Private_Functions
82 * @{
83 */
84
85 /*@} end of group PSRAM_UHS_Private_Functions */
86
87 /** @defgroup PSRAM_UHS_Public_Functions
88 * @{
89 */
config_uhs_phy(uint32_t datarate)90 int config_uhs_phy(uint32_t datarate)
91 {
92 uint32_t tmpVal = 0;
93
94 if (datarate > 1866) {
95 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F0A1323);
96 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x0b030404);
97 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x050e0419);
98 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x0a6a1c1c);
99 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x0711070e);
100
101 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
102 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 1);
103 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
104
105 }
106 #ifndef CONIFG_DISABLE_ALL_PSRAM_FRQ_EXCEPT_2000
107 else if (datarate > 1600) {
108 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F283203);
109 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x0a020303);
110 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x040d0416);
111 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x091e1818);
112 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x0710070d);
113
114 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
115 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 3);
116 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
117
118 } else if (datarate > 1066) {
119 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F270212);
120 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x09020303);
121 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x040c0313);
122 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x07d11515);
123 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x060f060c);
124
125 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
126 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 1);
127 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
128 } else if (datarate > 800) {
129 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F270212);
130 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x06010202);
131 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x0309020d);
132 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x05360e0e);
133 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x050c0509);
134
135 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
136 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 1);
137 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
138
139 } else if (datarate > 666) {
140 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F041020);
141 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x05000101);
142 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x0208010a);
143 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x03e90b0b);
144 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x040b0408);
145
146 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
147 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 0);
148 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
149 } else if (datarate > 400) {
150 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F130010);
151 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x05000101);
152 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x02080108);
153 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x03420909);
154 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x040b0408);
155
156 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
157 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 0);
158 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
159 } else {
160 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F020010);
161 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x04000101);
162 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x02070106);
163 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x01f50606);
164 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_44_OFFSET, 0x040a0407);
165
166 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
167 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 0);
168 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
169 }
170 #endif
171 return 0;
172 }
173
power_up_ldo12uhs(void)174 static void power_up_ldo12uhs(void)
175 {
176 uint32_t tmpVal = 0;
177 tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS);
178
179 #ifdef BL808D_REWORK
180 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO12UHS_PULLDOWN, 0);
181 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO12UHS_PULLDOWN_SEL, 1);
182 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_LDO12UHS, 0);
183 #else
184 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_LDO12UHS, 1);
185 BL_WR_REG(GLB_BASE, GLB_LDO12UHS, tmpVal);
186 arch_delay_us(300);
187
188 tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS);
189 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO12UHS_VOUT_SEL, 6);
190 #endif
191 BL_WR_REG(GLB_BASE, GLB_LDO12UHS, tmpVal);
192 arch_delay_us(1);
193 }
194
set_cen_ck_ckn(void)195 static void set_cen_ck_ckn(void)
196 {
197 uint32_t tmpVal = 0;
198 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
199 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_N_REG, 0);
200 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_P_REG, 0);
201 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
202 arch_delay_us(1);
203 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40);
204 tmpVal &= 0xFFFCFFFF;
205 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY0, 1);
206 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal);
207 arch_delay_us(1);
208 }
209
set_or_uhs(uint32_t datarate)210 static int set_or_uhs(uint32_t datarate)
211 {
212 uint32_t tmpVal = 0;
213 uint32_t *uhs_phy_cfg_base_addr = (uint32_t *)(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_00_OFFSET);
214 // clang-format off
215 const static uint32_t uhs_phy_cfg_data[] ={
216 0x802b0200, 0x60206020, 0x70027002, 0x70027002,
217 0x70027002, 0x70027002, 0x70027002, 0x70027002,
218 0x70027002, 0x70027002, 0x26000000, 0x26000006,
219 };
220 // clang-format on
221
222 for (uint32_t i = 0; i < 12; i++) {
223 uhs_phy_cfg_base_addr[i] = uhs_phy_cfg_data[i];
224 }
225
226 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_30);
227 tmpVal &= 0x08ffffff;
228 tmpVal |= 0x07000000;
229 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_30, tmpVal);
230
231 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_48);
232 tmpVal &= 0xfffffcff;
233 tmpVal |= 0x00000200;
234 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_48, tmpVal);
235
236 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_4C);
237 tmpVal &= 0xffe0ffff;
238 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_4C, tmpVal);
239
240 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
241 tmpVal &= 0xff88ff88;
242 tmpVal |= 0x00330033;
243 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
244
245 arch_delay_us(1);
246
247 return 0;
248 }
switch_to_ldo12uhs(void)249 static void switch_to_ldo12uhs(void)
250 {
251 uint32_t tmpVal = 0;
252 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40);
253 tmpVal &= 0xFFCFFFFF;
254 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal);
255 arch_delay_us(1);
256 }
257
release_cen_ck_ckn(void)258 static void release_cen_ck_ckn(void)
259 {
260 uint32_t tmpVal = 0;
261 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40);
262 tmpVal &= 0xFFFCFEFF;
263 #ifdef BL808D_REWORK
264 tmpVal |= 0x10000;
265 #else
266 tmpVal |= 0x30000;
267 #endif
268 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal);
269 arch_delay_us(1);
270
271 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
272 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_N_REG, 3);
273 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_P_REG, 3);
274 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
275 arch_delay_us(1);
276 }
277
Psram_analog_init(uint32_t pck_freq)278 static void Psram_analog_init(uint32_t pck_freq)
279 {
280 /* power on ldo12 */
281 power_up_ldo12uhs();
282
283 /* set cen ck ckn */
284 set_cen_ck_ckn();
285
286 /*
287 * overwrite default register content
288 * only support 2000M and 1500MHZ
289 */
290 set_or_uhs(pck_freq);
291
292 /* switch to ldo12 */
293 switch_to_ldo12uhs();
294
295 /* release cen ck */
296 release_cen_ck_ckn();
297
298 /* config phy paramater */
299 config_uhs_phy(pck_freq);
300 }
301
302 /****************************************************************************/ /**
303 * @brief Init Psram UHS ,set auto refresh cycle
304 *
305 * @param cfg: pck frequency unit is MHZ
306 *
307 * @return None
308 *
309 *******************************************************************************/
Psram_UHS_Init(PSRAM_UHS_Cfg_Type * cfg)310 void Psram_UHS_Init(PSRAM_UHS_Cfg_Type *cfg)
311 {
312 uint32_t tmpVal = 0;
313
314 CHECK_PARAM(IS_PSRAM_UHS_MEM_SIZE_TYPE(cfg->psramMemSize));
315 CHECK_PARAM(IS_PSRAM_UHS_PAGE_SIZE_TYPE(cfg->psramPageSize));
316
317 if (cfg->pck_freq > 2300) {
318 /* max support 2300MHZ */
319 while (1)
320 ;
321 } else if (cfg->pck_freq > 1600) {
322 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_UHS_TIMING_CTRL_OFFSET, 0x1a03000f);
323 } else {
324 BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_UHS_TIMING_CTRL_OFFSET, 0x1202000b);
325 }
326
327 Psram_analog_init(cfg->pck_freq);
328
329 /* Wait 150 us */
330 arch_delay_us(150);
331
332 /* set refresh paramater */
333 /* 1. auto refresh clock source is pck_t, Adjust pck_t_div so that the frequency is around ~50Mhz */
334 /* tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL);
335 tmpVal &= 0x00ffffff;
336
337 if (cfg->pck_freq >= 2200) {
338 tmpVal |= 0x05000000;
339 } else if (cfg->pck_freq >= 2000) {
340 tmpVal |= 0x04000000;
341 } else if (cfg->pck_freq >= 1500) {
342 tmpVal |= 0x03000000;
343 } else if (cfg->pck_freq >= 1400) {
344 tmpVal |= 0x02000000;
345 } else if (cfg->pck_freq >= 666) {
346 tmpVal |= 0x01000000;
347 }
348 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL, tmpVal); */
349 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL);
350 tmpVal &= 0x00ffffff;
351
352 if (cfg->pck_freq >= 2200) {
353 tmpVal |= 0x05000000;
354 } else if (cfg->pck_freq >= 1800) {
355 tmpVal |= 0x04000000;
356 } else if (cfg->pck_freq >= 1500) {
357 tmpVal |= 0x03000000;
358 } else if (cfg->pck_freq >= 1400) {
359 tmpVal |= 0x02000000;
360 } else if (cfg->pck_freq >= 666) {
361 tmpVal |= 0x01000000;
362 }
363 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL, tmpVal);
364
365 /* 2. setting refresh windows cycle count
366 * reg_win_cycle = refresh_window / Tpck_y
367 *
368 * refresh_window unit is ms
369 * when refresh tempotory > 85
370 * refresh_window = 16
371 * elsee
372 * refresh_window = 32
373 */
374 if (cfg->isHighTem == PSRAM_UHS_NORMAL_TEMP) {
375 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_1, 0x16e360);
376 } else {
377 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_1, 0xB71B0);
378 }
379 /* 3 & 4. setting refresh count in a windows fixed value 4096 in v0.2
380 * calculate Average cycle between two auto-refresh
381 * reg_refi_cycle = reg_win_cycle / reg_win_ref_cnt
382 * */
383 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_2);
384 // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_WIN_REF_CNT, 0x1000);
385 if (cfg->isHighTem == PSRAM_UHS_NORMAL_TEMP) {
386 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_REFI_CYCLE, (370));
387 } else {
388 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_REFI_CYCLE, (190));
389 }
390 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_2, tmpVal);
391
392 /* 5 setting single auto refresh time */
393 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_4);
394 // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_BUST_CYCLE, (uint32_t)(90 / T_pck_t));
395 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_BUST_CYCLE, 5);
396 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_AUTO_FRESH_4, tmpVal);
397
398 /* 6 auto-refesh enable */
399 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
400 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_AF_EN);
401
402 /* 7&8 . set psram memory size and page size */
403 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_ADDRMB_MSK, cfg->psramMemSize);
404 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_LINEAR_BND_B, cfg->psramPageSize);
405 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
406
407 /* 9. psram enable initial */
408 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
409 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_INIT_EN);
410 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
411 }
412
413 /****************************************************************************/ /**
414 * @brief Read register for uhs
415 *
416 * @param reg_addr: read addr
417 * @param regVal: regVal
418 *
419 * @return success or not
420 *
421 *******************************************************************************/
PSram_UHS_Read_Reg(uint32_t reg_addr,uint8_t * regVal)422 int PSram_UHS_Read_Reg(uint32_t reg_addr, uint8_t *regVal)
423 {
424 uint32_t tmpVal = 0;
425 uint32_t cnt = 0;
426
427 /* 1 generate requeset and wait authorization*/
428 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
429 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);
430 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
431
432 do {
433 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
434 cnt++;
435 if (cnt > PSRAM_UHS_RW_TIMEOUT)
436 return -1;
437 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_REG_CONFIG_GNT));
438
439 /* 2 set mode reg */
440 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
441 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, reg_addr);
442 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
443
444 /* 3 enable controller Rx*/
445 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
446 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGR_PULSE);
447 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);
448
449 cnt = 0;
450
451 /* 4 wait read done */
452 do {
453 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
454 cnt++;
455 if (cnt > PSRAM_UHS_RW_TIMEOUT)
456 return -1;
457 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGR_DONE));
458
459 /* 5 steup up read data */
460 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
461
462 *regVal = (uint8_t)(BL_GET_REG_BITS_VAL(tmpVal, PSRAM_UHS_STS_CONFIG_READ));
463
464 /* 6 cancel requeset singnal */
465 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
466 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);
467 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
468
469 return 0;
470 }
471
472 /****************************************************************************/ /**
473 * @brief write register for winbond PSRAM
474 *
475 * @param regCfg: wirte reg data
476 *
477 * @return None
478 *
479 *******************************************************************************/
PSram_UHS_Write_Reg(PSRAM_UHS_Write_Reg_Cfg_Type * regCfg)480 int PSram_UHS_Write_Reg(PSRAM_UHS_Write_Reg_Cfg_Type *regCfg)
481 {
482 uint32_t tmpVal = 0;
483 uint32_t cnt = 0;
484 uint8_t regWriteList[] = { 0, 2 };
485 uint8_t i = 0;
486
487 CHECK_PARAM(IS_PSRAM_UHS_DRIVER_ST_TYPE(regCfg->driver_st));
488 CHECK_PARAM(IS_PSRAM_UHS_WARP_BURST_TYPE(regCfg->burst_size));
489 CHECK_PARAM(IS_PSRAM_UHS_LATENCY_TYPE(regCfg->lentency));
490
491 /* 1 congfi write reg*/
492 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_PSRAM_CONFIGURE);
493
494 switch (regCfg->burst_size) {
495 case PSRAM_UHS_WARP_BURST_64:
496 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_64);
497 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_32);
498 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_16);
499 break;
500 case PSRAM_UHS_WARP_BURST_32:
501 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_16);
502 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_32);
503 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_64);
504 break;
505 case PSRAM_UHS_WARP_BURST_16:
506 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_16);
507 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_32);
508 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_64);
509 break;
510 case PSRAM_UHS_WARP_BURST_NONE:
511 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_16);
512 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_32);
513 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_UHS_BL_64);
514 break;
515 default:
516 return -1;
517 }
518 if (regCfg->driver_st != PSRAM_UHS_DRIVER_ST_NO_CHANGE) {
519 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DRIVE_ST, regCfg->driver_st);
520 }
521 if (regCfg->lentency != PSRAM_UHS_LATENCY_NO_CHANGE) {
522 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_LATENCY, regCfg->lentency);
523 }
524
525 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_PSRAM_CONFIGURE, tmpVal);
526
527 /* 2 generate requeset and wait authorization */
528 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
529 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);
530 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
531
532 do {
533 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
534 cnt++;
535 if (cnt > PSRAM_UHS_RW_TIMEOUT)
536 return -1;
537 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_REG_CONFIG_GNT));
538
539 for (i = 0; i < sizeof(regWriteList) / sizeof(uint8_t); i++) {
540 /* 3 set mode reg */
541 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
542 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, regWriteList[i]);
543 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
544
545 /* 4 enable controller */
546 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
547 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGW_PULSE);
548 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);
549
550 cnt = 0;
551
552 /* 5 wait write done */
553 do {
554 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
555 cnt++;
556 if (cnt > PSRAM_UHS_RW_TIMEOUT)
557 return -1;
558 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE));
559 }
560
561 /* 6 cancel requeset singnal */
562 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
563 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);
564 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
565
566 return 0;
567 }
568
569 /****************************************************************************/ /**
570 * @brief Timing Reset
571 *
572 * @param reg_addr: reg_addr
573 * @param regCfg: wirte reg data
574 *
575 * @return None
576 *
577 *******************************************************************************/
PSram_UHS_Timing_Reset(void)578 int PSram_UHS_Timing_Reset(void)
579 {
580 uint32_t tmpVal = 0;
581
582 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40);
583 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY1, 0);
584 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY0, 1);
585
586 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal);
587
588 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
589 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_N_REG, 0);
590 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_P_REG, 0);
591
592 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
593
594 arch_delay_us(1000);
595
596 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40);
597 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY1, 3);
598 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_UHS_DMY0, 0);
599
600 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_40, tmpVal);
601
602 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50);
603 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_N_REG, 4);
604 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_DQ_OE_MID_P_REG, 4);
605
606 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
607
608 return 0;
609 }
610
611 /****************************************************************************/ /**
612 * @brief construct cmd wave for psram
613 *
614 * @param reg_addr: reg_addr
615 * @param regCfg: wirte reg data
616 *
617 * @return None
618 *
619 *******************************************************************************/
PSram_UHS_Construct_Cmd(PSRAM_UHS_CMD_Type cmd)620 int PSram_UHS_Construct_Cmd(PSRAM_UHS_CMD_Type cmd)
621 {
622 uint32_t tmpVal = 0;
623 uint32_t cnt = 0;
624
625 CHECK_PARAM(IS_PSRAM_UHS_CMD_TYPE(cmd));
626
627 /* generate requeset and wait authorization*/
628 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
629 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);
630 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
631
632 do {
633 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
634 cnt++;
635 if (cnt > PSRAM_UHS_RW_TIMEOUT)
636 goto exit;
637 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_REG_CONFIG_GNT));
638
639 /* enable cmd generate */
640 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
641
642 switch (cmd) {
643 case PSRAM_UHS_CMD_SELF_REFRESH_IN:
644 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_SRFI_PULSE);
645 break;
646 case PSRAM_UHS_CMD_SELF_REFRESH_EXIT:
647 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_SRFO_PULSE);
648 break;
649 case PSRAM_UHS_CMD_GLOBAL_RESET:
650 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_GLBR_PULSE);
651 /* Wait 15 us for reset */
652 arch_delay_us(15);
653 break;
654 case PSRAM_UHS_CMD_ZQ_CAL_LONG:
655
656 /* 3 set mode reg */
657 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
658 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, 5);
659 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
660
661 /* 4 enable controller */
662 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
663 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGW_PULSE);
664 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);
665
666 cnt = 0;
667
668 /* 5 wait write done */
669 do {
670 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
671 cnt++;
672 if (cnt > PSRAM_UHS_RW_TIMEOUT)
673 goto exit;
674 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE));
675
676 break;
677 case PSRAM_UHS_CMD_ZQ_CAL_SHORT:
678
679 /* 3 set mode reg */
680 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
681 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, 6);
682 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
683
684 /* 4 enable controller */
685 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
686 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGW_PULSE);
687 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);
688
689 cnt = 0;
690
691 /* 5 wait write done */
692 do {
693 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
694 cnt++;
695 if (cnt > PSRAM_UHS_RW_TIMEOUT)
696 goto exit;
697 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE));
698 break;
699 case PSRAM_UHS_CMD_ZQ_CAL_RESET:
700
701 /* 3 set mode reg */
702 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
703 tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_REG_MODE_REG, 7);
704 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
705
706 /* 4 enable controller */
707 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
708 tmpVal = BL_SET_REG_BIT(tmpVal, PSRAM_UHS_REG_REGW_PULSE);
709 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);
710
711 cnt = 0;
712
713 /* 5 wait write done */
714 do {
715 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
716 cnt++;
717 if (cnt > PSRAM_UHS_RW_TIMEOUT)
718 goto exit;
719 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_REGW_DONE));
720 break;
721 default:
722 goto exit;
723 break;
724 }
725
726 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD, tmpVal);
727
728 cnt = 0;
729
730 /* wait write done */
731 switch (cmd) {
732 case PSRAM_UHS_CMD_SELF_REFRESH_IN:
733 do {
734 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
735 cnt++;
736 if (cnt > PSRAM_UHS_RW_TIMEOUT)
737 goto exit;
738
739 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_SRFI_DONE));
740 break;
741 case PSRAM_UHS_CMD_SELF_REFRESH_EXIT:
742 do {
743 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
744 cnt++;
745 if (cnt > PSRAM_UHS_RW_TIMEOUT)
746 goto exit;
747
748 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_SRFO_DONE));
749 break;
750 case PSRAM_UHS_CMD_GLOBAL_RESET:
751 do {
752 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_CMD);
753 cnt++;
754 if (cnt > PSRAM_UHS_RW_TIMEOUT)
755 goto exit;
756
757 } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_UHS_STS_GLBR_DONE));
758 break;
759 default:
760 goto exit;
761 }
762
763 /* 6 cancel requeset singnal */
764 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
765 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);
766 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
767
768 return 0;
769
770 exit:
771 /* 6 cancel requeset singnal */
772 tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC);
773 tmpVal = BL_CLR_REG_BIT(tmpVal, PSRAM_UHS_REG_CONFIG_REQ);
774 BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_BASIC, tmpVal);
775
776 return -1;
777 }
778
779 /**
780 * @brief defualt init for 64MB x16 UHS PSRAM
781 * user should enable UHS PSRAM PLL before call this function
782 * @param uhs_pll_clk The uhs pll frequency used
783 */
Psram_UHS_x16_Init(uint32_t uhs_pll_clk)784 void Psram_UHS_x16_Init(uint32_t uhs_pll_clk)
785 {
786 PSRAM_UHS_Cfg_Type psramDefaultCfg = {
787 2000,
788 PSRAM_MEM_SIZE_64MB,
789 PSRAM_PAGE_SIZE_2KB,
790 PSRAM_UHS_NORMAL_TEMP,
791 };
792
793 PSRAM_UHS_Write_Reg_Cfg_Type writeReg = {
794 PSRAM_UHS_DRIVER_ST_40_PDPU,
795 PSRAM_UHS_WARP_BURST_NONE,
796 PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ,
797 };
798
799 psramDefaultCfg.pck_freq = uhs_pll_clk;
800
801 if ((uhs_pll_clk >= 2000) && (uhs_pll_clk <= 2300)) {
802 writeReg.lentency = PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ;
803 } else if ((uhs_pll_clk <= 1600) && (uhs_pll_clk > 1066)) {
804 writeReg.lentency = PSRAM_UHS_LATENCY_W14_R29_MAX_FRE_800_MHZ;
805 } else if ((uhs_pll_clk < 1067) && (uhs_pll_clk > 800)) {
806 writeReg.lentency = PSRAM_UHS_LATENCY_W10_R20_MAX_FRE_533_MHZ;
807 } else if ((uhs_pll_clk <= 800) && (uhs_pll_clk > 667)) {
808 writeReg.lentency = PSRAM_UHS_LATENCY_W6_R16_MAX_FRE_400_MHZ;
809 } else if ((uhs_pll_clk < 667) && (uhs_pll_clk > 400)) {
810 writeReg.lentency = PSRAM_UHS_LATENCY_W5_R13_MAX_FRE_333_MHZ;
811 } else if (uhs_pll_clk <= 400) {
812 writeReg.lentency = PSRAM_UHS_LATENCY_W5_R9_MAX_FRE_200_MHZ;
813 }
814
815 /* first initial psram controller*/
816 Psram_UHS_Init(&psramDefaultCfg);
817
818 /* reset psram device*/
819 PSram_UHS_Construct_Cmd(PSRAM_UHS_CMD_GLOBAL_RESET);
820
821 arch_delay_us(100);
822
823 /* write 1GHZ configuration to psram device */
824 PSram_UHS_Write_Reg(&writeReg);
825 }
826
Psram_UHS_x16_Init_Override(PSRAM_UHS_Cfg_Type * cfg)827 void Psram_UHS_x16_Init_Override(PSRAM_UHS_Cfg_Type *cfg)
828 {
829 /* first initial psram controller*/
830 Psram_UHS_Init(cfg);
831
832 uhs_phy_init(cfg);
833 }
834 /*@} end of group PSRAM_UHS_Public_Functions */
835
836 /*@} end of group PSRAM_UHS */
837
838 /*@} end of group BL808_Peripheral_Driver */
839