1 /* 2 * Copyright (c) 2021-2024 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_PWM_H 10 #define HPM_PWM_H 11 12 typedef struct { 13 __RW uint32_t UNLK; /* 0x0: Shadow registers unlock register */ 14 union { 15 __RW uint32_t STA; /* 0x4: Counter start register */ 16 __RW uint32_t STA_HRPWM; /* 0x4: Counter start register */ 17 }; 18 union { 19 __RW uint32_t RLD; /* 0x8: Counter reload register */ 20 __RW uint32_t RLD_HRPWM; /* 0x8: Counter reload register */ 21 }; 22 union { 23 __RW uint32_t CMP[16]; /* 0xC - 0x48: Comparator register */ 24 __RW uint32_t CMP_HRPWM[16]; /* 0xC - 0x48: Comparator register */ 25 }; 26 __R uint8_t RESERVED0[44]; /* 0x4C - 0x77: Reserved */ 27 __RW uint32_t FRCMD; /* 0x78: Force output mode register */ 28 __RW uint32_t SHLK; /* 0x7C: Shadow registers lock register */ 29 __RW uint32_t CHCFG[16]; /* 0x80 - 0xBC: Output channel configure register */ 30 __R uint8_t RESERVED1[48]; /* 0xC0 - 0xEF: Reserved */ 31 __RW uint32_t GCR; /* 0xF0: Global control register */ 32 __RW uint32_t SHCR; /* 0xF4: Shadow register control register */ 33 __R uint8_t RESERVED2[8]; /* 0xF8 - 0xFF: Reserved */ 34 __R uint32_t CAPPOS[16]; /* 0x100 - 0x13C: Capture rising edge register */ 35 __R uint8_t RESERVED3[48]; /* 0x140 - 0x16F: Reserved */ 36 __R uint32_t CNT; /* 0x170: Counter */ 37 __R uint8_t RESERVED4[12]; /* 0x174 - 0x17F: Reserved */ 38 __R uint32_t CAPNEG[16]; /* 0x180 - 0x1BC: Capture falling edge register */ 39 __R uint8_t RESERVED5[48]; /* 0x1C0 - 0x1EF: Reserved */ 40 __R uint32_t CNTCOPY; /* 0x1F0: Counter copy */ 41 __R uint8_t RESERVED6[12]; /* 0x1F4 - 0x1FF: Reserved */ 42 __RW uint32_t PWMCFG[8]; /* 0x200 - 0x21C: PWM channel configure register */ 43 __W uint32_t SR; /* 0x220: Status register */ 44 __RW uint32_t IRQEN; /* 0x224: Interrupt request enable register */ 45 __R uint8_t RESERVED7[4]; /* 0x228 - 0x22B: Reserved */ 46 __RW uint32_t DMAEN; /* 0x22C: DMA request enable register */ 47 __RW uint32_t CMPCFG[16]; /* 0x230 - 0x26C: Comparator configure register */ 48 __R uint8_t RESERVED8[400]; /* 0x270 - 0x3FF: Reserved */ 49 __R uint32_t ANASTS[8]; /* 0x400 - 0x41C: analog status register */ 50 __RW uint32_t HRPWM_CFG; /* 0x420: hrpwm config register */ 51 __RW uint32_t ANA_CFG0; /* 0x424: analog config register */ 52 } PWM_Type; 53 54 55 /* Bitfield definition for register: UNLK */ 56 /* 57 * SHUNLK (RW) 58 * 59 * write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, 60 * otherwise the shadow registers can not be written. 61 */ 62 #define PWM_UNLK_SHUNLK_MASK (0xFFFFFFFFUL) 63 #define PWM_UNLK_SHUNLK_SHIFT (0U) 64 #define PWM_UNLK_SHUNLK_SET(x) (((uint32_t)(x) << PWM_UNLK_SHUNLK_SHIFT) & PWM_UNLK_SHUNLK_MASK) 65 #define PWM_UNLK_SHUNLK_GET(x) (((uint32_t)(x) & PWM_UNLK_SHUNLK_MASK) >> PWM_UNLK_SHUNLK_SHIFT) 66 67 /* Bitfield definition for register: STA */ 68 /* 69 * XSTA (RW) 70 * 71 * pwm timer counter extended start point, should back to this value after reach xrld 72 */ 73 #define PWM_STA_XSTA_MASK (0xF0000000UL) 74 #define PWM_STA_XSTA_SHIFT (28U) 75 #define PWM_STA_XSTA_SET(x) (((uint32_t)(x) << PWM_STA_XSTA_SHIFT) & PWM_STA_XSTA_MASK) 76 #define PWM_STA_XSTA_GET(x) (((uint32_t)(x) & PWM_STA_XSTA_MASK) >> PWM_STA_XSTA_SHIFT) 77 78 /* 79 * STA (RW) 80 * 81 * pwm timer counter start value 82 * sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk 83 */ 84 #define PWM_STA_STA_MASK (0xFFFFFF0UL) 85 #define PWM_STA_STA_SHIFT (4U) 86 #define PWM_STA_STA_SET(x) (((uint32_t)(x) << PWM_STA_STA_SHIFT) & PWM_STA_STA_MASK) 87 #define PWM_STA_STA_GET(x) (((uint32_t)(x) & PWM_STA_STA_MASK) >> PWM_STA_STA_SHIFT) 88 89 /* Bitfield definition for register: STA_HRPWM */ 90 /* 91 * STA (RW) 92 * 93 */ 94 #define PWM_STA_HRPWM_STA_MASK (0xFFFFFF00UL) 95 #define PWM_STA_HRPWM_STA_SHIFT (8U) 96 #define PWM_STA_HRPWM_STA_SET(x) (((uint32_t)(x) << PWM_STA_HRPWM_STA_SHIFT) & PWM_STA_HRPWM_STA_MASK) 97 #define PWM_STA_HRPWM_STA_GET(x) (((uint32_t)(x) & PWM_STA_HRPWM_STA_MASK) >> PWM_STA_HRPWM_STA_SHIFT) 98 99 /* Bitfield definition for register: RLD */ 100 /* 101 * XRLD (RW) 102 * 103 * timeout counter extended reload point, counter will reload to xsta after reach this point 104 */ 105 #define PWM_RLD_XRLD_MASK (0xF0000000UL) 106 #define PWM_RLD_XRLD_SHIFT (28U) 107 #define PWM_RLD_XRLD_SET(x) (((uint32_t)(x) << PWM_RLD_XRLD_SHIFT) & PWM_RLD_XRLD_MASK) 108 #define PWM_RLD_XRLD_GET(x) (((uint32_t)(x) & PWM_RLD_XRLD_MASK) >> PWM_RLD_XRLD_SHIFT) 109 110 /* 111 * RLD (RW) 112 * 113 * pwm timer counter reload value 114 */ 115 #define PWM_RLD_RLD_MASK (0xFFFFFF0UL) 116 #define PWM_RLD_RLD_SHIFT (4U) 117 #define PWM_RLD_RLD_SET(x) (((uint32_t)(x) << PWM_RLD_RLD_SHIFT) & PWM_RLD_RLD_MASK) 118 #define PWM_RLD_RLD_GET(x) (((uint32_t)(x) & PWM_RLD_RLD_MASK) >> PWM_RLD_RLD_SHIFT) 119 120 /* Bitfield definition for register: RLD_HRPWM */ 121 /* 122 * RLD (RW) 123 * 124 */ 125 #define PWM_RLD_HRPWM_RLD_MASK (0xFFFFFF00UL) 126 #define PWM_RLD_HRPWM_RLD_SHIFT (8U) 127 #define PWM_RLD_HRPWM_RLD_SET(x) (((uint32_t)(x) << PWM_RLD_HRPWM_RLD_SHIFT) & PWM_RLD_HRPWM_RLD_MASK) 128 #define PWM_RLD_HRPWM_RLD_GET(x) (((uint32_t)(x) & PWM_RLD_HRPWM_RLD_MASK) >> PWM_RLD_HRPWM_RLD_SHIFT) 129 130 /* 131 * RLD_HR (RW) 132 * 133 * pwm timer counter reload value at high resolution, only exist if hwpwm is enabled. 134 */ 135 #define PWM_RLD_HRPWM_RLD_HR_MASK (0xFFU) 136 #define PWM_RLD_HRPWM_RLD_HR_SHIFT (0U) 137 #define PWM_RLD_HRPWM_RLD_HR_SET(x) (((uint32_t)(x) << PWM_RLD_HRPWM_RLD_HR_SHIFT) & PWM_RLD_HRPWM_RLD_HR_MASK) 138 #define PWM_RLD_HRPWM_RLD_HR_GET(x) (((uint32_t)(x) & PWM_RLD_HRPWM_RLD_HR_MASK) >> PWM_RLD_HRPWM_RLD_HR_SHIFT) 139 140 /* Bitfield definition for register: 0 */ 141 /* 142 * XCMP (RW) 143 * 144 * extended counter compare value 145 */ 146 #define PWM_CMP_XCMP_MASK (0xF0000000UL) 147 #define PWM_CMP_XCMP_SHIFT (28U) 148 #define PWM_CMP_XCMP_SET(x) (((uint32_t)(x) << PWM_CMP_XCMP_SHIFT) & PWM_CMP_XCMP_MASK) 149 #define PWM_CMP_XCMP_GET(x) (((uint32_t)(x) & PWM_CMP_XCMP_MASK) >> PWM_CMP_XCMP_SHIFT) 150 151 /* 152 * CMP (RW) 153 * 154 * clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, 155 * and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. 156 */ 157 #define PWM_CMP_CMP_MASK (0xFFFFFF0UL) 158 #define PWM_CMP_CMP_SHIFT (4U) 159 #define PWM_CMP_CMP_SET(x) (((uint32_t)(x) << PWM_CMP_CMP_SHIFT) & PWM_CMP_CMP_MASK) 160 #define PWM_CMP_CMP_GET(x) (((uint32_t)(x) & PWM_CMP_CMP_MASK) >> PWM_CMP_CMP_SHIFT) 161 162 /* 163 * CMPHLF (RW) 164 * 165 * half clock counter compare value 166 */ 167 #define PWM_CMP_CMPHLF_MASK (0x8U) 168 #define PWM_CMP_CMPHLF_SHIFT (3U) 169 #define PWM_CMP_CMPHLF_SET(x) (((uint32_t)(x) << PWM_CMP_CMPHLF_SHIFT) & PWM_CMP_CMPHLF_MASK) 170 #define PWM_CMP_CMPHLF_GET(x) (((uint32_t)(x) & PWM_CMP_CMPHLF_MASK) >> PWM_CMP_CMPHLF_SHIFT) 171 172 /* 173 * CMPJIT (RW) 174 * 175 * jitter counter compare value 176 */ 177 #define PWM_CMP_CMPJIT_MASK (0x7U) 178 #define PWM_CMP_CMPJIT_SHIFT (0U) 179 #define PWM_CMP_CMPJIT_SET(x) (((uint32_t)(x) << PWM_CMP_CMPJIT_SHIFT) & PWM_CMP_CMPJIT_MASK) 180 #define PWM_CMP_CMPJIT_GET(x) (((uint32_t)(x) & PWM_CMP_CMPJIT_MASK) >> PWM_CMP_CMPJIT_SHIFT) 181 182 /* Bitfield definition for register: 0 */ 183 /* 184 * CMP (RW) 185 * 186 */ 187 #define PWM_CMP_HRPWM_CMP_MASK (0xFFFFFF00UL) 188 #define PWM_CMP_HRPWM_CMP_SHIFT (8U) 189 #define PWM_CMP_HRPWM_CMP_SET(x) (((uint32_t)(x) << PWM_CMP_HRPWM_CMP_SHIFT) & PWM_CMP_HRPWM_CMP_MASK) 190 #define PWM_CMP_HRPWM_CMP_GET(x) (((uint32_t)(x) & PWM_CMP_HRPWM_CMP_MASK) >> PWM_CMP_HRPWM_CMP_SHIFT) 191 192 /* 193 * CMP_HR (RW) 194 * 195 * high resolution compare value 196 */ 197 #define PWM_CMP_HRPWM_CMP_HR_MASK (0xFFU) 198 #define PWM_CMP_HRPWM_CMP_HR_SHIFT (0U) 199 #define PWM_CMP_HRPWM_CMP_HR_SET(x) (((uint32_t)(x) << PWM_CMP_HRPWM_CMP_HR_SHIFT) & PWM_CMP_HRPWM_CMP_HR_MASK) 200 #define PWM_CMP_HRPWM_CMP_HR_GET(x) (((uint32_t)(x) & PWM_CMP_HRPWM_CMP_HR_MASK) >> PWM_CMP_HRPWM_CMP_HR_SHIFT) 201 202 /* Bitfield definition for register: FRCMD */ 203 /* 204 * FRCMD (RW) 205 * 206 * 2bit for each PWM output channel (0-7); 207 * 00: force output 0 208 * 01: force output 1 209 * 10: output highz 210 * 11: no force 211 */ 212 #define PWM_FRCMD_FRCMD_MASK (0xFFFFU) 213 #define PWM_FRCMD_FRCMD_SHIFT (0U) 214 #define PWM_FRCMD_FRCMD_SET(x) (((uint32_t)(x) << PWM_FRCMD_FRCMD_SHIFT) & PWM_FRCMD_FRCMD_MASK) 215 #define PWM_FRCMD_FRCMD_GET(x) (((uint32_t)(x) & PWM_FRCMD_FRCMD_MASK) >> PWM_FRCMD_FRCMD_SHIFT) 216 217 /* Bitfield definition for register: SHLK */ 218 /* 219 * SHLK (RW) 220 * 221 * write 1 to lock all shawdow register, write access is not permitted 222 */ 223 #define PWM_SHLK_SHLK_MASK (0x80000000UL) 224 #define PWM_SHLK_SHLK_SHIFT (31U) 225 #define PWM_SHLK_SHLK_SET(x) (((uint32_t)(x) << PWM_SHLK_SHLK_SHIFT) & PWM_SHLK_SHLK_MASK) 226 #define PWM_SHLK_SHLK_GET(x) (((uint32_t)(x) & PWM_SHLK_SHLK_MASK) >> PWM_SHLK_SHLK_SHIFT) 227 228 /* Bitfield definition for register array: CHCFG */ 229 /* 230 * CMPSELEND (RW) 231 * 232 * assign the last comparator for this output channel 233 */ 234 #define PWM_CHCFG_CMPSELEND_MASK (0x1F000000UL) 235 #define PWM_CHCFG_CMPSELEND_SHIFT (24U) 236 #define PWM_CHCFG_CMPSELEND_SET(x) (((uint32_t)(x) << PWM_CHCFG_CMPSELEND_SHIFT) & PWM_CHCFG_CMPSELEND_MASK) 237 #define PWM_CHCFG_CMPSELEND_GET(x) (((uint32_t)(x) & PWM_CHCFG_CMPSELEND_MASK) >> PWM_CHCFG_CMPSELEND_SHIFT) 238 239 /* 240 * CMPSELBEG (RW) 241 * 242 * assign the first comparator for this output channel 243 */ 244 #define PWM_CHCFG_CMPSELBEG_MASK (0x1F0000UL) 245 #define PWM_CHCFG_CMPSELBEG_SHIFT (16U) 246 #define PWM_CHCFG_CMPSELBEG_SET(x) (((uint32_t)(x) << PWM_CHCFG_CMPSELBEG_SHIFT) & PWM_CHCFG_CMPSELBEG_MASK) 247 #define PWM_CHCFG_CMPSELBEG_GET(x) (((uint32_t)(x) & PWM_CHCFG_CMPSELBEG_MASK) >> PWM_CHCFG_CMPSELBEG_SHIFT) 248 249 /* 250 * OUTPOL (RW) 251 * 252 * output polarity, set to 1 will invert the output 253 */ 254 #define PWM_CHCFG_OUTPOL_MASK (0x2U) 255 #define PWM_CHCFG_OUTPOL_SHIFT (1U) 256 #define PWM_CHCFG_OUTPOL_SET(x) (((uint32_t)(x) << PWM_CHCFG_OUTPOL_SHIFT) & PWM_CHCFG_OUTPOL_MASK) 257 #define PWM_CHCFG_OUTPOL_GET(x) (((uint32_t)(x) & PWM_CHCFG_OUTPOL_MASK) >> PWM_CHCFG_OUTPOL_SHIFT) 258 259 /* Bitfield definition for register: GCR */ 260 /* 261 * FAULTI3EN (RW) 262 * 263 * 1- enable the internal fault input 3 264 */ 265 #define PWM_GCR_FAULTI3EN_MASK (0x80000000UL) 266 #define PWM_GCR_FAULTI3EN_SHIFT (31U) 267 #define PWM_GCR_FAULTI3EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI3EN_SHIFT) & PWM_GCR_FAULTI3EN_MASK) 268 #define PWM_GCR_FAULTI3EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI3EN_MASK) >> PWM_GCR_FAULTI3EN_SHIFT) 269 270 /* 271 * FAULTI2EN (RW) 272 * 273 * 1- enable the internal fault input 2 274 */ 275 #define PWM_GCR_FAULTI2EN_MASK (0x40000000UL) 276 #define PWM_GCR_FAULTI2EN_SHIFT (30U) 277 #define PWM_GCR_FAULTI2EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI2EN_SHIFT) & PWM_GCR_FAULTI2EN_MASK) 278 #define PWM_GCR_FAULTI2EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI2EN_MASK) >> PWM_GCR_FAULTI2EN_SHIFT) 279 280 /* 281 * FAULTI1EN (RW) 282 * 283 * 1- enable the internal fault input 1 284 */ 285 #define PWM_GCR_FAULTI1EN_MASK (0x20000000UL) 286 #define PWM_GCR_FAULTI1EN_SHIFT (29U) 287 #define PWM_GCR_FAULTI1EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI1EN_SHIFT) & PWM_GCR_FAULTI1EN_MASK) 288 #define PWM_GCR_FAULTI1EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI1EN_MASK) >> PWM_GCR_FAULTI1EN_SHIFT) 289 290 /* 291 * FAULTI0EN (RW) 292 * 293 * 1- enable the internal fault input 0 294 */ 295 #define PWM_GCR_FAULTI0EN_MASK (0x10000000UL) 296 #define PWM_GCR_FAULTI0EN_SHIFT (28U) 297 #define PWM_GCR_FAULTI0EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI0EN_SHIFT) & PWM_GCR_FAULTI0EN_MASK) 298 #define PWM_GCR_FAULTI0EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI0EN_MASK) >> PWM_GCR_FAULTI0EN_SHIFT) 299 300 /* 301 * DEBUGFAULT (RW) 302 * 303 * 1- enable debug mode output protection 304 */ 305 #define PWM_GCR_DEBUGFAULT_MASK (0x8000000UL) 306 #define PWM_GCR_DEBUGFAULT_SHIFT (27U) 307 #define PWM_GCR_DEBUGFAULT_SET(x) (((uint32_t)(x) << PWM_GCR_DEBUGFAULT_SHIFT) & PWM_GCR_DEBUGFAULT_MASK) 308 #define PWM_GCR_DEBUGFAULT_GET(x) (((uint32_t)(x) & PWM_GCR_DEBUGFAULT_MASK) >> PWM_GCR_DEBUGFAULT_SHIFT) 309 310 /* 311 * FRCPOL (RW) 312 * 313 * polarity of input pwm_force, 314 * 1- active low 315 * 0- active high 316 */ 317 #define PWM_GCR_FRCPOL_MASK (0x4000000UL) 318 #define PWM_GCR_FRCPOL_SHIFT (26U) 319 #define PWM_GCR_FRCPOL_SET(x) (((uint32_t)(x) << PWM_GCR_FRCPOL_SHIFT) & PWM_GCR_FRCPOL_MASK) 320 #define PWM_GCR_FRCPOL_GET(x) (((uint32_t)(x) & PWM_GCR_FRCPOL_MASK) >> PWM_GCR_FRCPOL_SHIFT) 321 322 /* 323 * HWSHDWEDG (RW) 324 * 325 * When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. 326 * This bit assign its which edge is used as compare shadow register hardware load event. 327 * 1- Falling edge 328 * 0- Rising edge 329 */ 330 #define PWM_GCR_HWSHDWEDG_MASK (0x1000000UL) 331 #define PWM_GCR_HWSHDWEDG_SHIFT (24U) 332 #define PWM_GCR_HWSHDWEDG_SET(x) (((uint32_t)(x) << PWM_GCR_HWSHDWEDG_SHIFT) & PWM_GCR_HWSHDWEDG_MASK) 333 #define PWM_GCR_HWSHDWEDG_GET(x) (((uint32_t)(x) & PWM_GCR_HWSHDWEDG_MASK) >> PWM_GCR_HWSHDWEDG_SHIFT) 334 335 /* 336 * CMPSHDWSEL (RW) 337 * 338 * This bitfield select one of the comparators as hardware event time to load comparator shadow registers 339 */ 340 #define PWM_GCR_CMPSHDWSEL_MASK (0xF80000UL) 341 #define PWM_GCR_CMPSHDWSEL_SHIFT (19U) 342 #define PWM_GCR_CMPSHDWSEL_SET(x) (((uint32_t)(x) << PWM_GCR_CMPSHDWSEL_SHIFT) & PWM_GCR_CMPSHDWSEL_MASK) 343 #define PWM_GCR_CMPSHDWSEL_GET(x) (((uint32_t)(x) & PWM_GCR_CMPSHDWSEL_MASK) >> PWM_GCR_CMPSHDWSEL_SHIFT) 344 345 /* 346 * FAULTRECEDG (RW) 347 * 348 * When hardware load is selected as output fault recover trigger and the selected channel is capture mode. 349 * This bit assign its effective edge of fault recover trigger. 350 * 1- Falling edge 351 * 0- Rising edge 352 */ 353 #define PWM_GCR_FAULTRECEDG_MASK (0x40000UL) 354 #define PWM_GCR_FAULTRECEDG_SHIFT (18U) 355 #define PWM_GCR_FAULTRECEDG_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTRECEDG_SHIFT) & PWM_GCR_FAULTRECEDG_MASK) 356 #define PWM_GCR_FAULTRECEDG_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTRECEDG_MASK) >> PWM_GCR_FAULTRECEDG_SHIFT) 357 358 /* 359 * FAULTRECHWSEL (RW) 360 * 361 * Selec one of the 24 comparators as fault output recover trigger. 362 */ 363 #define PWM_GCR_FAULTRECHWSEL_MASK (0x3E000UL) 364 #define PWM_GCR_FAULTRECHWSEL_SHIFT (13U) 365 #define PWM_GCR_FAULTRECHWSEL_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTRECHWSEL_SHIFT) & PWM_GCR_FAULTRECHWSEL_MASK) 366 #define PWM_GCR_FAULTRECHWSEL_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTRECHWSEL_MASK) >> PWM_GCR_FAULTRECHWSEL_SHIFT) 367 368 /* 369 * FAULTE1EN (RW) 370 * 371 * 1- enable the external fault input 1 372 */ 373 #define PWM_GCR_FAULTE1EN_MASK (0x1000U) 374 #define PWM_GCR_FAULTE1EN_SHIFT (12U) 375 #define PWM_GCR_FAULTE1EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTE1EN_SHIFT) & PWM_GCR_FAULTE1EN_MASK) 376 #define PWM_GCR_FAULTE1EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTE1EN_MASK) >> PWM_GCR_FAULTE1EN_SHIFT) 377 378 /* 379 * FAULTE0EN (RW) 380 * 381 * 1- enable the external fault input 0 382 */ 383 #define PWM_GCR_FAULTE0EN_MASK (0x800U) 384 #define PWM_GCR_FAULTE0EN_SHIFT (11U) 385 #define PWM_GCR_FAULTE0EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTE0EN_SHIFT) & PWM_GCR_FAULTE0EN_MASK) 386 #define PWM_GCR_FAULTE0EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTE0EN_MASK) >> PWM_GCR_FAULTE0EN_SHIFT) 387 388 /* 389 * FAULTEXPOL (RW) 390 * 391 * external fault polarity 392 * 1-active low 393 * 0-active high 394 */ 395 #define PWM_GCR_FAULTEXPOL_MASK (0x600U) 396 #define PWM_GCR_FAULTEXPOL_SHIFT (9U) 397 #define PWM_GCR_FAULTEXPOL_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTEXPOL_SHIFT) & PWM_GCR_FAULTEXPOL_MASK) 398 #define PWM_GCR_FAULTEXPOL_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTEXPOL_MASK) >> PWM_GCR_FAULTEXPOL_SHIFT) 399 400 /* 401 * RLDSYNCEN (RW) 402 * 403 * 1- pwm timer counter reset to reload value (rld) by synci is enabled 404 */ 405 #define PWM_GCR_RLDSYNCEN_MASK (0x100U) 406 #define PWM_GCR_RLDSYNCEN_SHIFT (8U) 407 #define PWM_GCR_RLDSYNCEN_SET(x) (((uint32_t)(x) << PWM_GCR_RLDSYNCEN_SHIFT) & PWM_GCR_RLDSYNCEN_MASK) 408 #define PWM_GCR_RLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_RLDSYNCEN_MASK) >> PWM_GCR_RLDSYNCEN_SHIFT) 409 410 /* 411 * CEN (RW) 412 * 413 * 1- enable the pwm timer counter 414 * 0- stop the pwm timer counter 415 */ 416 #define PWM_GCR_CEN_MASK (0x80U) 417 #define PWM_GCR_CEN_SHIFT (7U) 418 #define PWM_GCR_CEN_SET(x) (((uint32_t)(x) << PWM_GCR_CEN_SHIFT) & PWM_GCR_CEN_MASK) 419 #define PWM_GCR_CEN_GET(x) (((uint32_t)(x) & PWM_GCR_CEN_MASK) >> PWM_GCR_CEN_SHIFT) 420 421 /* 422 * FAULTCLR (RW) 423 * 424 * 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. 425 * User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. 426 */ 427 #define PWM_GCR_FAULTCLR_MASK (0x40U) 428 #define PWM_GCR_FAULTCLR_SHIFT (6U) 429 #define PWM_GCR_FAULTCLR_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTCLR_SHIFT) & PWM_GCR_FAULTCLR_MASK) 430 #define PWM_GCR_FAULTCLR_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTCLR_MASK) >> PWM_GCR_FAULTCLR_SHIFT) 431 432 /* 433 * XRLDSYNCEN (RW) 434 * 435 * 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled 436 */ 437 #define PWM_GCR_XRLDSYNCEN_MASK (0x20U) 438 #define PWM_GCR_XRLDSYNCEN_SHIFT (5U) 439 #define PWM_GCR_XRLDSYNCEN_SET(x) (((uint32_t)(x) << PWM_GCR_XRLDSYNCEN_SHIFT) & PWM_GCR_XRLDSYNCEN_MASK) 440 #define PWM_GCR_XRLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_XRLDSYNCEN_MASK) >> PWM_GCR_XRLDSYNCEN_SHIFT) 441 442 /* 443 * HR_PWM_EN (RW) 444 * 445 * set to enable high resolution pwm, trig_cmp, start/reload register will have different definition. 446 */ 447 #define PWM_GCR_HR_PWM_EN_MASK (0x10U) 448 #define PWM_GCR_HR_PWM_EN_SHIFT (4U) 449 #define PWM_GCR_HR_PWM_EN_SET(x) (((uint32_t)(x) << PWM_GCR_HR_PWM_EN_SHIFT) & PWM_GCR_HR_PWM_EN_MASK) 450 #define PWM_GCR_HR_PWM_EN_GET(x) (((uint32_t)(x) & PWM_GCR_HR_PWM_EN_MASK) >> PWM_GCR_HR_PWM_EN_SHIFT) 451 452 /* 453 * TIMERRESET (RW) 454 * 455 * set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear 456 */ 457 #define PWM_GCR_TIMERRESET_MASK (0x8U) 458 #define PWM_GCR_TIMERRESET_SHIFT (3U) 459 #define PWM_GCR_TIMERRESET_SET(x) (((uint32_t)(x) << PWM_GCR_TIMERRESET_SHIFT) & PWM_GCR_TIMERRESET_MASK) 460 #define PWM_GCR_TIMERRESET_GET(x) (((uint32_t)(x) & PWM_GCR_TIMERRESET_MASK) >> PWM_GCR_TIMERRESET_SHIFT) 461 462 /* 463 * FRCTIME (WO) 464 * 465 * This bit field select the force effective time 466 * 00: force immediately 467 * 01: force at main counter reload time 468 * 10: force at FRCSYNCI 469 * 11: no force 470 */ 471 #define PWM_GCR_FRCTIME_MASK (0x6U) 472 #define PWM_GCR_FRCTIME_SHIFT (1U) 473 #define PWM_GCR_FRCTIME_SET(x) (((uint32_t)(x) << PWM_GCR_FRCTIME_SHIFT) & PWM_GCR_FRCTIME_MASK) 474 #define PWM_GCR_FRCTIME_GET(x) (((uint32_t)(x) & PWM_GCR_FRCTIME_MASK) >> PWM_GCR_FRCTIME_SHIFT) 475 476 /* 477 * SWFRC (RW) 478 * 479 * 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect 480 */ 481 #define PWM_GCR_SWFRC_MASK (0x1U) 482 #define PWM_GCR_SWFRC_SHIFT (0U) 483 #define PWM_GCR_SWFRC_SET(x) (((uint32_t)(x) << PWM_GCR_SWFRC_SHIFT) & PWM_GCR_SWFRC_MASK) 484 #define PWM_GCR_SWFRC_GET(x) (((uint32_t)(x) & PWM_GCR_SWFRC_MASK) >> PWM_GCR_SWFRC_SHIFT) 485 486 /* Bitfield definition for register: SHCR */ 487 /* 488 * CNT_UPDATE_RELOAD (RW) 489 * 490 * set to update counter working register at reload point, clear to use cnt_update_time as old version. 491 */ 492 #define PWM_SHCR_CNT_UPDATE_RELOAD_MASK (0x8000U) 493 #define PWM_SHCR_CNT_UPDATE_RELOAD_SHIFT (15U) 494 #define PWM_SHCR_CNT_UPDATE_RELOAD_SET(x) (((uint32_t)(x) << PWM_SHCR_CNT_UPDATE_RELOAD_SHIFT) & PWM_SHCR_CNT_UPDATE_RELOAD_MASK) 495 #define PWM_SHCR_CNT_UPDATE_RELOAD_GET(x) (((uint32_t)(x) & PWM_SHCR_CNT_UPDATE_RELOAD_MASK) >> PWM_SHCR_CNT_UPDATE_RELOAD_SHIFT) 496 497 /* 498 * CNT_UPDATE_EDGE (RW) 499 * 500 * 0 for posedge; 1 for negedge if hardware trigger time is selected for update_time, and selected channel is capture mode, for counter shadow registers 501 */ 502 #define PWM_SHCR_CNT_UPDATE_EDGE_MASK (0x4000U) 503 #define PWM_SHCR_CNT_UPDATE_EDGE_SHIFT (14U) 504 #define PWM_SHCR_CNT_UPDATE_EDGE_SET(x) (((uint32_t)(x) << PWM_SHCR_CNT_UPDATE_EDGE_SHIFT) & PWM_SHCR_CNT_UPDATE_EDGE_MASK) 505 #define PWM_SHCR_CNT_UPDATE_EDGE_GET(x) (((uint32_t)(x) & PWM_SHCR_CNT_UPDATE_EDGE_MASK) >> PWM_SHCR_CNT_UPDATE_EDGE_SHIFT) 506 507 /* 508 * FORCE_UPDATE_EDGE (RW) 509 * 510 * 0 for posedge; 1 for negedge if hardware trigger time is selected for update_time, and selected channel is capture mode, for FRCMD shadow registers 511 */ 512 #define PWM_SHCR_FORCE_UPDATE_EDGE_MASK (0x2000U) 513 #define PWM_SHCR_FORCE_UPDATE_EDGE_SHIFT (13U) 514 #define PWM_SHCR_FORCE_UPDATE_EDGE_SET(x) (((uint32_t)(x) << PWM_SHCR_FORCE_UPDATE_EDGE_SHIFT) & PWM_SHCR_FORCE_UPDATE_EDGE_MASK) 515 #define PWM_SHCR_FORCE_UPDATE_EDGE_GET(x) (((uint32_t)(x) & PWM_SHCR_FORCE_UPDATE_EDGE_MASK) >> PWM_SHCR_FORCE_UPDATE_EDGE_SHIFT) 516 517 /* 518 * FRCSHDWSEL (RW) 519 * 520 * This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers 521 */ 522 #define PWM_SHCR_FRCSHDWSEL_MASK (0x1F00U) 523 #define PWM_SHCR_FRCSHDWSEL_SHIFT (8U) 524 #define PWM_SHCR_FRCSHDWSEL_SET(x) (((uint32_t)(x) << PWM_SHCR_FRCSHDWSEL_SHIFT) & PWM_SHCR_FRCSHDWSEL_MASK) 525 #define PWM_SHCR_FRCSHDWSEL_GET(x) (((uint32_t)(x) & PWM_SHCR_FRCSHDWSEL_MASK) >> PWM_SHCR_FRCSHDWSEL_SHIFT) 526 527 /* 528 * CNTSHDWSEL (RW) 529 * 530 * This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) 531 */ 532 #define PWM_SHCR_CNTSHDWSEL_MASK (0xF8U) 533 #define PWM_SHCR_CNTSHDWSEL_SHIFT (3U) 534 #define PWM_SHCR_CNTSHDWSEL_SET(x) (((uint32_t)(x) << PWM_SHCR_CNTSHDWSEL_SHIFT) & PWM_SHCR_CNTSHDWSEL_MASK) 535 #define PWM_SHCR_CNTSHDWSEL_GET(x) (((uint32_t)(x) & PWM_SHCR_CNTSHDWSEL_MASK) >> PWM_SHCR_CNTSHDWSEL_SHIFT) 536 537 /* 538 * CNTSHDWUPT (RW) 539 * 540 * This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register 541 * 00: after software set shlk bit of shlk register 542 * 01: immediately after the register being modified 543 * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. 544 * The comparator can be either output compare mode or input capture mode. 545 * 11: after SHSYNCI assert 546 */ 547 #define PWM_SHCR_CNTSHDWUPT_MASK (0x6U) 548 #define PWM_SHCR_CNTSHDWUPT_SHIFT (1U) 549 #define PWM_SHCR_CNTSHDWUPT_SET(x) (((uint32_t)(x) << PWM_SHCR_CNTSHDWUPT_SHIFT) & PWM_SHCR_CNTSHDWUPT_MASK) 550 #define PWM_SHCR_CNTSHDWUPT_GET(x) (((uint32_t)(x) & PWM_SHCR_CNTSHDWUPT_MASK) >> PWM_SHCR_CNTSHDWUPT_SHIFT) 551 552 /* 553 * SHLKEN (RW) 554 * 555 * 1- enable shadow registers lock feature, 556 * 0- disable shadow registers lock, shlk bit will always be 0 557 */ 558 #define PWM_SHCR_SHLKEN_MASK (0x1U) 559 #define PWM_SHCR_SHLKEN_SHIFT (0U) 560 #define PWM_SHCR_SHLKEN_SET(x) (((uint32_t)(x) << PWM_SHCR_SHLKEN_SHIFT) & PWM_SHCR_SHLKEN_MASK) 561 #define PWM_SHCR_SHLKEN_GET(x) (((uint32_t)(x) & PWM_SHCR_SHLKEN_MASK) >> PWM_SHCR_SHLKEN_SHIFT) 562 563 /* Bitfield definition for register array: CAPPOS */ 564 /* 565 * CAPPOS (RO) 566 * 567 * counter value captured at input posedge 568 */ 569 #define PWM_CAPPOS_CAPPOS_MASK (0xFFFFFFF0UL) 570 #define PWM_CAPPOS_CAPPOS_SHIFT (4U) 571 #define PWM_CAPPOS_CAPPOS_GET(x) (((uint32_t)(x) & PWM_CAPPOS_CAPPOS_MASK) >> PWM_CAPPOS_CAPPOS_SHIFT) 572 573 /* Bitfield definition for register: CNT */ 574 /* 575 * XCNT (RO) 576 * 577 * current extended counter value 578 */ 579 #define PWM_CNT_XCNT_MASK (0xF0000000UL) 580 #define PWM_CNT_XCNT_SHIFT (28U) 581 #define PWM_CNT_XCNT_GET(x) (((uint32_t)(x) & PWM_CNT_XCNT_MASK) >> PWM_CNT_XCNT_SHIFT) 582 583 /* 584 * CNT (RO) 585 * 586 * current clock counter value 587 */ 588 #define PWM_CNT_CNT_MASK (0xFFFFFF0UL) 589 #define PWM_CNT_CNT_SHIFT (4U) 590 #define PWM_CNT_CNT_GET(x) (((uint32_t)(x) & PWM_CNT_CNT_MASK) >> PWM_CNT_CNT_SHIFT) 591 592 /* Bitfield definition for register array: CAPNEG */ 593 /* 594 * CAPNEG (RO) 595 * 596 * counter value captured at input signal falling edge 597 */ 598 #define PWM_CAPNEG_CAPNEG_MASK (0xFFFFFFFFUL) 599 #define PWM_CAPNEG_CAPNEG_SHIFT (0U) 600 #define PWM_CAPNEG_CAPNEG_GET(x) (((uint32_t)(x) & PWM_CAPNEG_CAPNEG_MASK) >> PWM_CAPNEG_CAPNEG_SHIFT) 601 602 /* Bitfield definition for register: CNTCOPY */ 603 /* 604 * XCNT (RO) 605 * 606 * current extended counter value 607 */ 608 #define PWM_CNTCOPY_XCNT_MASK (0xF0000000UL) 609 #define PWM_CNTCOPY_XCNT_SHIFT (28U) 610 #define PWM_CNTCOPY_XCNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_XCNT_MASK) >> PWM_CNTCOPY_XCNT_SHIFT) 611 612 /* 613 * CNT (RO) 614 * 615 * current clock counter value 616 */ 617 #define PWM_CNTCOPY_CNT_MASK (0xFFFFFF0UL) 618 #define PWM_CNTCOPY_CNT_SHIFT (4U) 619 #define PWM_CNTCOPY_CNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_CNT_MASK) >> PWM_CNTCOPY_CNT_SHIFT) 620 621 /* Bitfield definition for register array: PWMCFG */ 622 /* 623 * HR_UPDATE_MODE (RW) 624 * 625 * 0: update the hr value for the first edge at reload point; 626 * 1: update the hr value for the first edge at the last edge; 627 * all others will be updated at previous edge 628 * for pair mode, only pwm_cfg 0/2/4/6 are used 629 */ 630 #define PWM_PWMCFG_HR_UPDATE_MODE_MASK (0x20000000UL) 631 #define PWM_PWMCFG_HR_UPDATE_MODE_SHIFT (29U) 632 #define PWM_PWMCFG_HR_UPDATE_MODE_SET(x) (((uint32_t)(x) << PWM_PWMCFG_HR_UPDATE_MODE_SHIFT) & PWM_PWMCFG_HR_UPDATE_MODE_MASK) 633 #define PWM_PWMCFG_HR_UPDATE_MODE_GET(x) (((uint32_t)(x) & PWM_PWMCFG_HR_UPDATE_MODE_MASK) >> PWM_PWMCFG_HR_UPDATE_MODE_SHIFT) 634 635 /* 636 * OEN (RW) 637 * 638 * PWM output enable 639 * 1- output is enabled 640 * 0- output is disabled 641 */ 642 #define PWM_PWMCFG_OEN_MASK (0x10000000UL) 643 #define PWM_PWMCFG_OEN_SHIFT (28U) 644 #define PWM_PWMCFG_OEN_SET(x) (((uint32_t)(x) << PWM_PWMCFG_OEN_SHIFT) & PWM_PWMCFG_OEN_MASK) 645 #define PWM_PWMCFG_OEN_GET(x) (((uint32_t)(x) & PWM_PWMCFG_OEN_MASK) >> PWM_PWMCFG_OEN_SHIFT) 646 647 /* 648 * FRCSHDWUPT (RW) 649 * 650 * This bitfield select when the FRCMD shadow register will be loaded to its work register 651 * 00: after software set shlk bit of shlk register 652 * 01: immediately after the register being modified 653 * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. 654 * The comparator can be either output compare mode or input capture mode. 655 * 11: after SHSYNCI assert 656 */ 657 #define PWM_PWMCFG_FRCSHDWUPT_MASK (0xC000000UL) 658 #define PWM_PWMCFG_FRCSHDWUPT_SHIFT (26U) 659 #define PWM_PWMCFG_FRCSHDWUPT_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FRCSHDWUPT_SHIFT) & PWM_PWMCFG_FRCSHDWUPT_MASK) 660 #define PWM_PWMCFG_FRCSHDWUPT_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FRCSHDWUPT_MASK) >> PWM_PWMCFG_FRCSHDWUPT_SHIFT) 661 662 /* 663 * FAULTMODE (RW) 664 * 665 * This bitfield defines the PWM output status when fault condition happen 666 * 00: force output 0 667 * 01: force output 1 668 * 1x: output highz 669 */ 670 #define PWM_PWMCFG_FAULTMODE_MASK (0x3000000UL) 671 #define PWM_PWMCFG_FAULTMODE_SHIFT (24U) 672 #define PWM_PWMCFG_FAULTMODE_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FAULTMODE_SHIFT) & PWM_PWMCFG_FAULTMODE_MASK) 673 #define PWM_PWMCFG_FAULTMODE_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FAULTMODE_MASK) >> PWM_PWMCFG_FAULTMODE_SHIFT) 674 675 /* 676 * FAULTRECTIME (RW) 677 * 678 * This bitfield select when to recover PWM output after fault condition removed. 679 * 00: immediately 680 * 01: after pwm timer counter reload time 681 * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. 682 * The comparator can be either output compare mode or input capture mode. 683 * 11: after software write faultclr bit in GCR register 684 */ 685 #define PWM_PWMCFG_FAULTRECTIME_MASK (0xC00000UL) 686 #define PWM_PWMCFG_FAULTRECTIME_SHIFT (22U) 687 #define PWM_PWMCFG_FAULTRECTIME_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FAULTRECTIME_SHIFT) & PWM_PWMCFG_FAULTRECTIME_MASK) 688 #define PWM_PWMCFG_FAULTRECTIME_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FAULTRECTIME_MASK) >> PWM_PWMCFG_FAULTRECTIME_SHIFT) 689 690 /* 691 * FRCSRCSEL (RW) 692 * 693 * Select sources for force output 694 * 0- force output is enabled when FRCI assert 695 * 1- force output is enabled by software write swfrc to 1 696 */ 697 #define PWM_PWMCFG_FRCSRCSEL_MASK (0x200000UL) 698 #define PWM_PWMCFG_FRCSRCSEL_SHIFT (21U) 699 #define PWM_PWMCFG_FRCSRCSEL_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FRCSRCSEL_SHIFT) & PWM_PWMCFG_FRCSRCSEL_MASK) 700 #define PWM_PWMCFG_FRCSRCSEL_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FRCSRCSEL_MASK) >> PWM_PWMCFG_FRCSRCSEL_SHIFT) 701 702 /* 703 * PAIR (RW) 704 * 705 * 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. 706 * 0- PWM output is in indepandent mode. 707 */ 708 #define PWM_PWMCFG_PAIR_MASK (0x100000UL) 709 #define PWM_PWMCFG_PAIR_SHIFT (20U) 710 #define PWM_PWMCFG_PAIR_SET(x) (((uint32_t)(x) << PWM_PWMCFG_PAIR_SHIFT) & PWM_PWMCFG_PAIR_MASK) 711 #define PWM_PWMCFG_PAIR_GET(x) (((uint32_t)(x) & PWM_PWMCFG_PAIR_MASK) >> PWM_PWMCFG_PAIR_SHIFT) 712 713 /* 714 * DEADAREA (RW) 715 * 716 * This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. 717 * Note: user should configure pair bit and this bitfield before PWM output is enabled. 718 */ 719 #define PWM_PWMCFG_DEADAREA_MASK (0xFFFFFUL) 720 #define PWM_PWMCFG_DEADAREA_SHIFT (0U) 721 #define PWM_PWMCFG_DEADAREA_SET(x) (((uint32_t)(x) << PWM_PWMCFG_DEADAREA_SHIFT) & PWM_PWMCFG_DEADAREA_MASK) 722 #define PWM_PWMCFG_DEADAREA_GET(x) (((uint32_t)(x) & PWM_PWMCFG_DEADAREA_MASK) >> PWM_PWMCFG_DEADAREA_SHIFT) 723 724 /* Bitfield definition for register: SR */ 725 /* 726 * FAULTF (W1C) 727 * 728 * fault condition flag 729 */ 730 #define PWM_SR_FAULTF_MASK (0x8000000UL) 731 #define PWM_SR_FAULTF_SHIFT (27U) 732 #define PWM_SR_FAULTF_SET(x) (((uint32_t)(x) << PWM_SR_FAULTF_SHIFT) & PWM_SR_FAULTF_MASK) 733 #define PWM_SR_FAULTF_GET(x) (((uint32_t)(x) & PWM_SR_FAULTF_MASK) >> PWM_SR_FAULTF_SHIFT) 734 735 /* 736 * XRLDF (W1C) 737 * 738 * extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert 739 */ 740 #define PWM_SR_XRLDF_MASK (0x4000000UL) 741 #define PWM_SR_XRLDF_SHIFT (26U) 742 #define PWM_SR_XRLDF_SET(x) (((uint32_t)(x) << PWM_SR_XRLDF_SHIFT) & PWM_SR_XRLDF_MASK) 743 #define PWM_SR_XRLDF_GET(x) (((uint32_t)(x) & PWM_SR_XRLDF_MASK) >> PWM_SR_XRLDF_SHIFT) 744 745 /* 746 * HALFRLDF (W1C) 747 * 748 * half reload flag, this flag set when cnt count to rld/2 749 */ 750 #define PWM_SR_HALFRLDF_MASK (0x2000000UL) 751 #define PWM_SR_HALFRLDF_SHIFT (25U) 752 #define PWM_SR_HALFRLDF_SET(x) (((uint32_t)(x) << PWM_SR_HALFRLDF_SHIFT) & PWM_SR_HALFRLDF_MASK) 753 #define PWM_SR_HALFRLDF_GET(x) (((uint32_t)(x) & PWM_SR_HALFRLDF_MASK) >> PWM_SR_HALFRLDF_SHIFT) 754 755 /* 756 * RLDF (W1C) 757 * 758 * reload flag, this flag set when cnt count to rld value or when SYNCI assert 759 */ 760 #define PWM_SR_RLDF_MASK (0x1000000UL) 761 #define PWM_SR_RLDF_SHIFT (24U) 762 #define PWM_SR_RLDF_SET(x) (((uint32_t)(x) << PWM_SR_RLDF_SHIFT) & PWM_SR_RLDF_MASK) 763 #define PWM_SR_RLDF_GET(x) (((uint32_t)(x) & PWM_SR_RLDF_MASK) >> PWM_SR_RLDF_SHIFT) 764 765 /* 766 * CMPFX (W1C) 767 * 768 * comparator output compare or input capture flag 769 */ 770 #define PWM_SR_CMPFX_MASK (0xFFFFFFUL) 771 #define PWM_SR_CMPFX_SHIFT (0U) 772 #define PWM_SR_CMPFX_SET(x) (((uint32_t)(x) << PWM_SR_CMPFX_SHIFT) & PWM_SR_CMPFX_MASK) 773 #define PWM_SR_CMPFX_GET(x) (((uint32_t)(x) & PWM_SR_CMPFX_MASK) >> PWM_SR_CMPFX_SHIFT) 774 775 /* Bitfield definition for register: IRQEN */ 776 /* 777 * FAULTIRQE (RW) 778 * 779 * fault condition interrupt enable 780 */ 781 #define PWM_IRQEN_FAULTIRQE_MASK (0x8000000UL) 782 #define PWM_IRQEN_FAULTIRQE_SHIFT (27U) 783 #define PWM_IRQEN_FAULTIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_FAULTIRQE_SHIFT) & PWM_IRQEN_FAULTIRQE_MASK) 784 #define PWM_IRQEN_FAULTIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_FAULTIRQE_MASK) >> PWM_IRQEN_FAULTIRQE_SHIFT) 785 786 /* 787 * XRLDIRQE (RW) 788 * 789 * extended reload flag interrupt enable 790 */ 791 #define PWM_IRQEN_XRLDIRQE_MASK (0x4000000UL) 792 #define PWM_IRQEN_XRLDIRQE_SHIFT (26U) 793 #define PWM_IRQEN_XRLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_XRLDIRQE_SHIFT) & PWM_IRQEN_XRLDIRQE_MASK) 794 #define PWM_IRQEN_XRLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_XRLDIRQE_MASK) >> PWM_IRQEN_XRLDIRQE_SHIFT) 795 796 /* 797 * HALFRLDIRQE (RW) 798 * 799 * half reload flag interrupt enable 800 */ 801 #define PWM_IRQEN_HALFRLDIRQE_MASK (0x2000000UL) 802 #define PWM_IRQEN_HALFRLDIRQE_SHIFT (25U) 803 #define PWM_IRQEN_HALFRLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_HALFRLDIRQE_SHIFT) & PWM_IRQEN_HALFRLDIRQE_MASK) 804 #define PWM_IRQEN_HALFRLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_HALFRLDIRQE_MASK) >> PWM_IRQEN_HALFRLDIRQE_SHIFT) 805 806 /* 807 * RLDIRQE (RW) 808 * 809 * reload flag interrupt enable 810 */ 811 #define PWM_IRQEN_RLDIRQE_MASK (0x1000000UL) 812 #define PWM_IRQEN_RLDIRQE_SHIFT (24U) 813 #define PWM_IRQEN_RLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_RLDIRQE_SHIFT) & PWM_IRQEN_RLDIRQE_MASK) 814 #define PWM_IRQEN_RLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_RLDIRQE_MASK) >> PWM_IRQEN_RLDIRQE_SHIFT) 815 816 /* 817 * CMPIRQEX (RW) 818 * 819 * comparator output compare or input capture flag interrupt enable 820 */ 821 #define PWM_IRQEN_CMPIRQEX_MASK (0xFFFFFFUL) 822 #define PWM_IRQEN_CMPIRQEX_SHIFT (0U) 823 #define PWM_IRQEN_CMPIRQEX_SET(x) (((uint32_t)(x) << PWM_IRQEN_CMPIRQEX_SHIFT) & PWM_IRQEN_CMPIRQEX_MASK) 824 #define PWM_IRQEN_CMPIRQEX_GET(x) (((uint32_t)(x) & PWM_IRQEN_CMPIRQEX_MASK) >> PWM_IRQEN_CMPIRQEX_SHIFT) 825 826 /* Bitfield definition for register: DMAEN */ 827 /* 828 * FAULTEN (RW) 829 * 830 * fault condition DMA request enable 831 */ 832 #define PWM_DMAEN_FAULTEN_MASK (0x8000000UL) 833 #define PWM_DMAEN_FAULTEN_SHIFT (27U) 834 #define PWM_DMAEN_FAULTEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_FAULTEN_SHIFT) & PWM_DMAEN_FAULTEN_MASK) 835 #define PWM_DMAEN_FAULTEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_FAULTEN_MASK) >> PWM_DMAEN_FAULTEN_SHIFT) 836 837 /* 838 * XRLDEN (RW) 839 * 840 * extended reload flag DMA request enable 841 */ 842 #define PWM_DMAEN_XRLDEN_MASK (0x4000000UL) 843 #define PWM_DMAEN_XRLDEN_SHIFT (26U) 844 #define PWM_DMAEN_XRLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_XRLDEN_SHIFT) & PWM_DMAEN_XRLDEN_MASK) 845 #define PWM_DMAEN_XRLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_XRLDEN_MASK) >> PWM_DMAEN_XRLDEN_SHIFT) 846 847 /* 848 * HALFRLDEN (RW) 849 * 850 * half reload flag DMA request enable 851 */ 852 #define PWM_DMAEN_HALFRLDEN_MASK (0x2000000UL) 853 #define PWM_DMAEN_HALFRLDEN_SHIFT (25U) 854 #define PWM_DMAEN_HALFRLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_HALFRLDEN_SHIFT) & PWM_DMAEN_HALFRLDEN_MASK) 855 #define PWM_DMAEN_HALFRLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_HALFRLDEN_MASK) >> PWM_DMAEN_HALFRLDEN_SHIFT) 856 857 /* 858 * RLDEN (RW) 859 * 860 * reload flag DMA request enable 861 */ 862 #define PWM_DMAEN_RLDEN_MASK (0x1000000UL) 863 #define PWM_DMAEN_RLDEN_SHIFT (24U) 864 #define PWM_DMAEN_RLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_RLDEN_SHIFT) & PWM_DMAEN_RLDEN_MASK) 865 #define PWM_DMAEN_RLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_RLDEN_MASK) >> PWM_DMAEN_RLDEN_SHIFT) 866 867 /* 868 * CMPENX (RW) 869 * 870 * comparator output compare or input capture flag DMA request enable 871 */ 872 #define PWM_DMAEN_CMPENX_MASK (0xFFFFFFUL) 873 #define PWM_DMAEN_CMPENX_SHIFT (0U) 874 #define PWM_DMAEN_CMPENX_SET(x) (((uint32_t)(x) << PWM_DMAEN_CMPENX_SHIFT) & PWM_DMAEN_CMPENX_MASK) 875 #define PWM_DMAEN_CMPENX_GET(x) (((uint32_t)(x) & PWM_DMAEN_CMPENX_MASK) >> PWM_DMAEN_CMPENX_SHIFT) 876 877 /* Bitfield definition for register array: CMPCFG */ 878 /* 879 * XCNTCMPEN (RW) 880 * 881 * This bitfield enable the comparator to compare xcmp with xcnt. 882 */ 883 #define PWM_CMPCFG_XCNTCMPEN_MASK (0xF0U) 884 #define PWM_CMPCFG_XCNTCMPEN_SHIFT (4U) 885 #define PWM_CMPCFG_XCNTCMPEN_SET(x) (((uint32_t)(x) << PWM_CMPCFG_XCNTCMPEN_SHIFT) & PWM_CMPCFG_XCNTCMPEN_MASK) 886 #define PWM_CMPCFG_XCNTCMPEN_GET(x) (((uint32_t)(x) & PWM_CMPCFG_XCNTCMPEN_MASK) >> PWM_CMPCFG_XCNTCMPEN_SHIFT) 887 888 /* 889 * CMPSHDWUPT (RW) 890 * 891 * This bitfield select when the comparator shadow register will be loaded to its work register 892 * 00: after software set shlk bit of shlk register 893 * 01: immediately after the register being modified 894 * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. 895 * The comparator can be either output compare mode or input capture mode. 896 * 11: after SHSYNCI assert 897 */ 898 #define PWM_CMPCFG_CMPSHDWUPT_MASK (0xCU) 899 #define PWM_CMPCFG_CMPSHDWUPT_SHIFT (2U) 900 #define PWM_CMPCFG_CMPSHDWUPT_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPSHDWUPT_SHIFT) & PWM_CMPCFG_CMPSHDWUPT_MASK) 901 #define PWM_CMPCFG_CMPSHDWUPT_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPSHDWUPT_MASK) >> PWM_CMPCFG_CMPSHDWUPT_SHIFT) 902 903 /* 904 * CMPMODE (RW) 905 * 906 * comparator mode 907 * 0- output compare mode 908 * 1- input capture mode 909 */ 910 #define PWM_CMPCFG_CMPMODE_MASK (0x2U) 911 #define PWM_CMPCFG_CMPMODE_SHIFT (1U) 912 #define PWM_CMPCFG_CMPMODE_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPMODE_SHIFT) & PWM_CMPCFG_CMPMODE_MASK) 913 #define PWM_CMPCFG_CMPMODE_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPMODE_MASK) >> PWM_CMPCFG_CMPMODE_SHIFT) 914 915 /* Bitfield definition for register array: ANASTS */ 916 /* 917 * CALON (RO) 918 * 919 * calibration status. 920 * will be set by hardware after setting cal_start. 921 * cleared after calibration finished 922 */ 923 #define PWM_ANASTS_CALON_MASK (0x80000000UL) 924 #define PWM_ANASTS_CALON_SHIFT (31U) 925 #define PWM_ANASTS_CALON_GET(x) (((uint32_t)(x) & PWM_ANASTS_CALON_MASK) >> PWM_ANASTS_CALON_SHIFT) 926 927 /* Bitfield definition for register: HRPWM_CFG */ 928 /* 929 * CAL_SW_EN (RW) 930 * 931 * software calibration enable, internal use only 932 */ 933 #define PWM_HRPWM_CFG_CAL_SW_EN_MASK (0xFF00U) 934 #define PWM_HRPWM_CFG_CAL_SW_EN_SHIFT (8U) 935 #define PWM_HRPWM_CFG_CAL_SW_EN_SET(x) (((uint32_t)(x) << PWM_HRPWM_CFG_CAL_SW_EN_SHIFT) & PWM_HRPWM_CFG_CAL_SW_EN_MASK) 936 #define PWM_HRPWM_CFG_CAL_SW_EN_GET(x) (((uint32_t)(x) & PWM_HRPWM_CFG_CAL_SW_EN_MASK) >> PWM_HRPWM_CFG_CAL_SW_EN_SHIFT) 937 938 /* 939 * CAL_START (WO) 940 * 941 * calibration start. 942 * software setting this bit to start calibration process. 943 * each bit for one channel. 944 */ 945 #define PWM_HRPWM_CFG_CAL_START_MASK (0xFFU) 946 #define PWM_HRPWM_CFG_CAL_START_SHIFT (0U) 947 #define PWM_HRPWM_CFG_CAL_START_SET(x) (((uint32_t)(x) << PWM_HRPWM_CFG_CAL_START_SHIFT) & PWM_HRPWM_CFG_CAL_START_MASK) 948 #define PWM_HRPWM_CFG_CAL_START_GET(x) (((uint32_t)(x) & PWM_HRPWM_CFG_CAL_START_MASK) >> PWM_HRPWM_CFG_CAL_START_SHIFT) 949 950 /* Bitfield definition for register: ANA_CFG0 */ 951 /* 952 * CAL_SW_TRIG_H (RW) 953 * 954 */ 955 #define PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK (0x10000UL) 956 #define PWM_ANA_CFG0_CAL_SW_TRIG_H_SHIFT (16U) 957 #define PWM_ANA_CFG0_CAL_SW_TRIG_H_SET(x) (((uint32_t)(x) << PWM_ANA_CFG0_CAL_SW_TRIG_H_SHIFT) & PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK) 958 #define PWM_ANA_CFG0_CAL_SW_TRIG_H_GET(x) (((uint32_t)(x) & PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK) >> PWM_ANA_CFG0_CAL_SW_TRIG_H_SHIFT) 959 960 961 962 /* CMP register group index macro definition */ 963 #define PWM_CMP_0 (0UL) 964 #define PWM_CMP_1 (1UL) 965 #define PWM_CMP_2 (2UL) 966 #define PWM_CMP_3 (3UL) 967 #define PWM_CMP_4 (4UL) 968 #define PWM_CMP_5 (5UL) 969 #define PWM_CMP_6 (6UL) 970 #define PWM_CMP_7 (7UL) 971 #define PWM_CMP_8 (8UL) 972 #define PWM_CMP_9 (9UL) 973 #define PWM_CMP_10 (10UL) 974 #define PWM_CMP_11 (11UL) 975 #define PWM_CMP_12 (12UL) 976 #define PWM_CMP_13 (13UL) 977 #define PWM_CMP_14 (14UL) 978 #define PWM_CMP_15 (15UL) 979 980 /* CMP_HRPWM register group index macro definition */ 981 #define PWM_CMP_HRPWM_0 (0UL) 982 #define PWM_CMP_HRPWM_1 (1UL) 983 #define PWM_CMP_HRPWM_2 (2UL) 984 #define PWM_CMP_HRPWM_3 (3UL) 985 #define PWM_CMP_HRPWM_4 (4UL) 986 #define PWM_CMP_HRPWM_5 (5UL) 987 #define PWM_CMP_HRPWM_6 (6UL) 988 #define PWM_CMP_HRPWM_7 (7UL) 989 #define PWM_CMP_HRPWM_8 (8UL) 990 #define PWM_CMP_HRPWM_9 (9UL) 991 #define PWM_CMP_HRPWM_10 (10UL) 992 #define PWM_CMP_HRPWM_11 (11UL) 993 #define PWM_CMP_HRPWM_12 (12UL) 994 #define PWM_CMP_HRPWM_13 (13UL) 995 #define PWM_CMP_HRPWM_14 (14UL) 996 #define PWM_CMP_HRPWM_15 (15UL) 997 998 /* CHCFG register group index macro definition */ 999 #define PWM_CHCFG_0 (0UL) 1000 #define PWM_CHCFG_1 (1UL) 1001 #define PWM_CHCFG_2 (2UL) 1002 #define PWM_CHCFG_3 (3UL) 1003 #define PWM_CHCFG_4 (4UL) 1004 #define PWM_CHCFG_5 (5UL) 1005 #define PWM_CHCFG_6 (6UL) 1006 #define PWM_CHCFG_7 (7UL) 1007 #define PWM_CHCFG_8 (8UL) 1008 #define PWM_CHCFG_9 (9UL) 1009 #define PWM_CHCFG_10 (10UL) 1010 #define PWM_CHCFG_11 (11UL) 1011 #define PWM_CHCFG_12 (12UL) 1012 #define PWM_CHCFG_13 (13UL) 1013 #define PWM_CHCFG_14 (14UL) 1014 #define PWM_CHCFG_15 (15UL) 1015 1016 /* CAPPOS register group index macro definition */ 1017 #define PWM_CAPPOS_0 (0UL) 1018 #define PWM_CAPPOS_1 (1UL) 1019 #define PWM_CAPPOS_2 (2UL) 1020 #define PWM_CAPPOS_3 (3UL) 1021 #define PWM_CAPPOS_4 (4UL) 1022 #define PWM_CAPPOS_5 (5UL) 1023 #define PWM_CAPPOS_6 (6UL) 1024 #define PWM_CAPPOS_7 (7UL) 1025 #define PWM_CAPPOS_8 (8UL) 1026 #define PWM_CAPPOS_9 (9UL) 1027 #define PWM_CAPPOS_10 (10UL) 1028 #define PWM_CAPPOS_11 (11UL) 1029 #define PWM_CAPPOS_12 (12UL) 1030 #define PWM_CAPPOS_13 (13UL) 1031 #define PWM_CAPPOS_14 (14UL) 1032 #define PWM_CAPPOS_15 (15UL) 1033 1034 /* CAPNEG register group index macro definition */ 1035 #define PWM_CAPNEG_0 (0UL) 1036 #define PWM_CAPNEG_1 (1UL) 1037 #define PWM_CAPNEG_2 (2UL) 1038 #define PWM_CAPNEG_3 (3UL) 1039 #define PWM_CAPNEG_4 (4UL) 1040 #define PWM_CAPNEG_5 (5UL) 1041 #define PWM_CAPNEG_6 (6UL) 1042 #define PWM_CAPNEG_7 (7UL) 1043 #define PWM_CAPNEG_8 (8UL) 1044 #define PWM_CAPNEG_9 (9UL) 1045 #define PWM_CAPNEG_10 (10UL) 1046 #define PWM_CAPNEG_11 (11UL) 1047 #define PWM_CAPNEG_12 (12UL) 1048 #define PWM_CAPNEG_13 (13UL) 1049 #define PWM_CAPNEG_14 (14UL) 1050 #define PWM_CAPNEG_15 (15UL) 1051 1052 /* PWMCFG register group index macro definition */ 1053 #define PWM_PWMCFG_0 (0UL) 1054 #define PWM_PWMCFG_1 (1UL) 1055 #define PWM_PWMCFG_2 (2UL) 1056 #define PWM_PWMCFG_3 (3UL) 1057 #define PWM_PWMCFG_4 (4UL) 1058 #define PWM_PWMCFG_5 (5UL) 1059 #define PWM_PWMCFG_6 (6UL) 1060 #define PWM_PWMCFG_7 (7UL) 1061 1062 /* CMPCFG register group index macro definition */ 1063 #define PWM_CMPCFG_CMPCFG0 (0UL) 1064 #define PWM_CMPCFG_1 (1UL) 1065 #define PWM_CMPCFG_2 (2UL) 1066 #define PWM_CMPCFG_3 (3UL) 1067 #define PWM_CMPCFG_4 (4UL) 1068 #define PWM_CMPCFG_5 (5UL) 1069 #define PWM_CMPCFG_6 (6UL) 1070 #define PWM_CMPCFG_7 (7UL) 1071 #define PWM_CMPCFG_8 (8UL) 1072 #define PWM_CMPCFG_9 (9UL) 1073 #define PWM_CMPCFG_10 (10UL) 1074 #define PWM_CMPCFG_11 (11UL) 1075 #define PWM_CMPCFG_12 (12UL) 1076 #define PWM_CMPCFG_13 (13UL) 1077 #define PWM_CMPCFG_14 (14UL) 1078 #define PWM_CMPCFG_15 (15UL) 1079 1080 /* ANASTS register group index macro definition */ 1081 #define PWM_ANASTS_0 (0UL) 1082 #define PWM_ANASTS_1 (1UL) 1083 #define PWM_ANASTS_2 (2UL) 1084 #define PWM_ANASTS_3 (3UL) 1085 #define PWM_ANASTS_4 (4UL) 1086 #define PWM_ANASTS_5 (5UL) 1087 #define PWM_ANASTS_6 (6UL) 1088 #define PWM_ANASTS_7 (7UL) 1089 1090 1091 #endif /* HPM_PWM_H */ 1092