1 /* 2 * Copyright (c) 2021-2024 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_QEIV2_H 10 #define HPM_QEIV2_H 11 12 typedef struct { 13 __RW uint32_t CR; /* 0x0: Control register */ 14 __RW uint32_t PHCFG; /* 0x4: Phase configure register */ 15 __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */ 16 __RW uint32_t PHIDX; /* 0xC: Phase index register */ 17 __RW uint32_t TRGOEN; /* 0x10: Tigger output enable register */ 18 __RW uint32_t READEN; /* 0x14: Read event enable register */ 19 __RW uint32_t ZCMP; /* 0x18: Z comparator */ 20 __RW uint32_t PHCMP; /* 0x1C: Phase comparator */ 21 __RW uint32_t SPDCMP; /* 0x20: Speed comparator */ 22 __RW uint32_t DMAEN; /* 0x24: DMA request enable register */ 23 __RW uint32_t SR; /* 0x28: Status register */ 24 __RW uint32_t IRQEN; /* 0x2C: Interrupt request register */ 25 struct { 26 __RW uint32_t Z; /* 0x30: Z counter */ 27 __R uint32_t PH; /* 0x34: Phase counter */ 28 __RW uint32_t SPD; /* 0x38: Speed counter */ 29 __R uint32_t TMR; /* 0x3C: Timer counter */ 30 } COUNT[4]; 31 __R uint8_t RESERVED0[16]; /* 0x70 - 0x7F: Reserved */ 32 __RW uint32_t ZCMP2; /* 0x80: Z comparator */ 33 __RW uint32_t PHCMP2; /* 0x84: Phase comparator */ 34 __RW uint32_t SPDCMP2; /* 0x88: Speed comparator */ 35 __RW uint32_t MATCH_CFG; /* 0x8C: */ 36 __RW uint32_t FILT_CFG[6]; /* 0x90 - 0xA4: A signal filter config */ 37 __R uint8_t RESERVED1[88]; /* 0xA8 - 0xFF: Reserved */ 38 __RW uint32_t QEI_CFG; /* 0x100: qei config register */ 39 __R uint8_t RESERVED2[12]; /* 0x104 - 0x10F: Reserved */ 40 __RW uint32_t PULSE0_NUM; /* 0x110: pulse0_num */ 41 __RW uint32_t PULSE1_NUM; /* 0x114: pulse1_num */ 42 __R uint32_t CYCLE0_CNT; /* 0x118: cycle0_cnt */ 43 __R uint32_t CYCLE0PULSE_CNT; /* 0x11C: cycle0pulse_cnt */ 44 __R uint32_t CYCLE1_CNT; /* 0x120: cycle1_cnt */ 45 __R uint32_t CYCLE1PULSE_CNT; /* 0x124: cycle1pulse_cnt */ 46 __R uint32_t CYCLE0_SNAP0; /* 0x128: cycle0_snap0 */ 47 __R uint32_t CYCLE0_SNAP1; /* 0x12C: cycle0_snap1 */ 48 __R uint32_t CYCLE1_SNAP0; /* 0x130: cycle1_snap0 */ 49 __R uint32_t CYCLE1_SNAP1; /* 0x134: cycle1_snap1 */ 50 __R uint8_t RESERVED3[8]; /* 0x138 - 0x13F: Reserved */ 51 __RW uint32_t CYCLE0_NUM; /* 0x140: cycle0_num */ 52 __RW uint32_t CYCLE1_NUM; /* 0x144: cycle1_num */ 53 __R uint32_t PULSE0_CNT; /* 0x148: pulse0_cnt */ 54 __R uint32_t PULSE0CYCLE_CNT; /* 0x14C: pulse0cycle_cnt */ 55 __R uint32_t PULSE1_CNT; /* 0x150: pulse1_cnt */ 56 __R uint32_t PULSE1CYCLE_CNT; /* 0x154: pulse1cycle_cnt */ 57 __R uint32_t PULSE0_SNAP0; /* 0x158: pulse0_snap0 */ 58 __R uint32_t PULSE0CYCLE_SNAP0; /* 0x15C: pulse0cycle_snap0 */ 59 __R uint32_t PULSE0_SNAP1; /* 0x160: pulse0_snap1 */ 60 __R uint32_t PULSE0CYCLE_SNAP1; /* 0x164: pulse0cycle_snap1 */ 61 __R uint32_t PULSE1_SNAP0; /* 0x168: pulse1_snap0 */ 62 __R uint32_t PULSE1CYCLE_SNAP0; /* 0x16C: pulse1cycle_snap0 */ 63 __R uint32_t PULSE1_SNAP1; /* 0x170: pulse1_snap1 */ 64 __R uint32_t PULSE1CYCLE_SNAP1; /* 0x174: pulse1cycle_snap1 */ 65 __R uint8_t RESERVED4[104]; /* 0x178 - 0x1DF: Reserved */ 66 __R uint32_t TIMESTAMP; /* 0x1E0: timestamp */ 67 __R uint8_t RESERVED5[12]; /* 0x1E4 - 0x1EF: Reserved */ 68 __RW uint32_t ADC_THRESHOLD; /* 0x1F0: adc_threshold */ 69 __R uint8_t RESERVED6[12]; /* 0x1F4 - 0x1FF: Reserved */ 70 __RW uint32_t ADCX_CFG0; /* 0x200: adcx_cfg0 */ 71 __RW uint32_t ADCX_CFG1; /* 0x204: adcx_cfg1 */ 72 __RW uint32_t ADCX_CFG2; /* 0x208: adcx_cfg2 */ 73 __R uint8_t RESERVED7[4]; /* 0x20C - 0x20F: Reserved */ 74 __RW uint32_t ADCY_CFG0; /* 0x210: adcy_cfg0 */ 75 __RW uint32_t ADCY_CFG1; /* 0x214: adcy_cfg1 */ 76 __RW uint32_t ADCY_CFG2; /* 0x218: adcy_cfg2 */ 77 __R uint8_t RESERVED8[4]; /* 0x21C - 0x21F: Reserved */ 78 __RW uint32_t CAL_CFG; /* 0x220: cal_cfg */ 79 __R uint8_t RESERVED9[12]; /* 0x224 - 0x22F: Reserved */ 80 __RW uint32_t PHASE_PARAM; /* 0x230: phase_param */ 81 __R uint8_t RESERVED10[4]; /* 0x234 - 0x237: Reserved */ 82 __RW uint32_t POS_THRESHOLD; /* 0x238: pos_threshold */ 83 __R uint8_t RESERVED11[4]; /* 0x23C - 0x23F: Reserved */ 84 __RW uint32_t UVW_POS[6]; /* 0x240 - 0x254: uvw_pos0 */ 85 __RW uint32_t UVW_POS_CFG[6]; /* 0x258 - 0x26C: uvw_pos0_cfg */ 86 __R uint8_t RESERVED12[16]; /* 0x270 - 0x27F: Reserved */ 87 __RW uint32_t PHASE_CNT; /* 0x280: phase_cnt */ 88 __W uint32_t PHASE_UPDATE; /* 0x284: phase_update */ 89 __RW uint32_t POSITION; /* 0x288: position */ 90 __W uint32_t POSITION_UPDATE; /* 0x28C: position_update */ 91 __R uint32_t ANGLE; /* 0x290: */ 92 __RW uint32_t POS_TIMEOUT; /* 0x294: pos_timeout */ 93 } QEIV2_Type; 94 95 96 /* Bitfield definition for register: CR */ 97 /* 98 * READ (WO) 99 * 100 * 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 101 */ 102 #define QEIV2_CR_READ_MASK (0x80000000UL) 103 #define QEIV2_CR_READ_SHIFT (31U) 104 #define QEIV2_CR_READ_SET(x) (((uint32_t)(x) << QEIV2_CR_READ_SHIFT) & QEIV2_CR_READ_MASK) 105 #define QEIV2_CR_READ_GET(x) (((uint32_t)(x) & QEIV2_CR_READ_MASK) >> QEIV2_CR_READ_SHIFT) 106 107 /* 108 * ZCNTCFG (RW) 109 * 110 * 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 111 * 0- zcnt will increment or decrement when Z input assert 112 */ 113 #define QEIV2_CR_ZCNTCFG_MASK (0x400000UL) 114 #define QEIV2_CR_ZCNTCFG_SHIFT (22U) 115 #define QEIV2_CR_ZCNTCFG_SET(x) (((uint32_t)(x) << QEIV2_CR_ZCNTCFG_SHIFT) & QEIV2_CR_ZCNTCFG_MASK) 116 #define QEIV2_CR_ZCNTCFG_GET(x) (((uint32_t)(x) & QEIV2_CR_ZCNTCFG_MASK) >> QEIV2_CR_ZCNTCFG_SHIFT) 117 118 /* 119 * PHCALIZ (RW) 120 * 121 * 1- phcnt will set to phidx when Z input assert(for abz digital signsl) 122 */ 123 #define QEIV2_CR_PHCALIZ_MASK (0x200000UL) 124 #define QEIV2_CR_PHCALIZ_SHIFT (21U) 125 #define QEIV2_CR_PHCALIZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PHCALIZ_SHIFT) & QEIV2_CR_PHCALIZ_MASK) 126 #define QEIV2_CR_PHCALIZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PHCALIZ_MASK) >> QEIV2_CR_PHCALIZ_SHIFT) 127 128 /* 129 * Z_ONLY_EN (RW) 130 * 131 * 1- phcnt will set to phidx when Z input assert(for xy analog signal and digital z, also need set phcaliz) 132 */ 133 #define QEIV2_CR_Z_ONLY_EN_MASK (0x100000UL) 134 #define QEIV2_CR_Z_ONLY_EN_SHIFT (20U) 135 #define QEIV2_CR_Z_ONLY_EN_SET(x) (((uint32_t)(x) << QEIV2_CR_Z_ONLY_EN_SHIFT) & QEIV2_CR_Z_ONLY_EN_MASK) 136 #define QEIV2_CR_Z_ONLY_EN_GET(x) (((uint32_t)(x) & QEIV2_CR_Z_ONLY_EN_MASK) >> QEIV2_CR_Z_ONLY_EN_SHIFT) 137 138 /* 139 * H2FDIR0 (RW) 140 * 141 */ 142 #define QEIV2_CR_H2FDIR0_MASK (0x80000UL) 143 #define QEIV2_CR_H2FDIR0_SHIFT (19U) 144 #define QEIV2_CR_H2FDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR0_SHIFT) & QEIV2_CR_H2FDIR0_MASK) 145 #define QEIV2_CR_H2FDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR0_MASK) >> QEIV2_CR_H2FDIR0_SHIFT) 146 147 /* 148 * H2FDIR1 (RW) 149 * 150 */ 151 #define QEIV2_CR_H2FDIR1_MASK (0x40000UL) 152 #define QEIV2_CR_H2FDIR1_SHIFT (18U) 153 #define QEIV2_CR_H2FDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR1_SHIFT) & QEIV2_CR_H2FDIR1_MASK) 154 #define QEIV2_CR_H2FDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR1_MASK) >> QEIV2_CR_H2FDIR1_SHIFT) 155 156 /* 157 * H2RDIR0 (RW) 158 * 159 */ 160 #define QEIV2_CR_H2RDIR0_MASK (0x20000UL) 161 #define QEIV2_CR_H2RDIR0_SHIFT (17U) 162 #define QEIV2_CR_H2RDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR0_SHIFT) & QEIV2_CR_H2RDIR0_MASK) 163 #define QEIV2_CR_H2RDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR0_MASK) >> QEIV2_CR_H2RDIR0_SHIFT) 164 165 /* 166 * H2RDIR1 (RW) 167 * 168 */ 169 #define QEIV2_CR_H2RDIR1_MASK (0x10000UL) 170 #define QEIV2_CR_H2RDIR1_SHIFT (16U) 171 #define QEIV2_CR_H2RDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR1_SHIFT) & QEIV2_CR_H2RDIR1_MASK) 172 #define QEIV2_CR_H2RDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR1_MASK) >> QEIV2_CR_H2RDIR1_SHIFT) 173 174 /* 175 * PAUSEPOS (RW) 176 * 177 * 1- pause position output valid when PAUSE assert 178 */ 179 #define QEIV2_CR_PAUSEPOS_MASK (0x8000U) 180 #define QEIV2_CR_PAUSEPOS_SHIFT (15U) 181 #define QEIV2_CR_PAUSEPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPOS_SHIFT) & QEIV2_CR_PAUSEPOS_MASK) 182 #define QEIV2_CR_PAUSEPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPOS_MASK) >> QEIV2_CR_PAUSEPOS_SHIFT) 183 184 /* 185 * PAUSESPD (RW) 186 * 187 * 1- pause spdcnt when PAUSE assert 188 */ 189 #define QEIV2_CR_PAUSESPD_MASK (0x4000U) 190 #define QEIV2_CR_PAUSESPD_SHIFT (14U) 191 #define QEIV2_CR_PAUSESPD_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSESPD_SHIFT) & QEIV2_CR_PAUSESPD_MASK) 192 #define QEIV2_CR_PAUSESPD_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSESPD_MASK) >> QEIV2_CR_PAUSESPD_SHIFT) 193 194 /* 195 * PAUSEPH (RW) 196 * 197 * 1- pause phcnt when PAUSE assert 198 */ 199 #define QEIV2_CR_PAUSEPH_MASK (0x2000U) 200 #define QEIV2_CR_PAUSEPH_SHIFT (13U) 201 #define QEIV2_CR_PAUSEPH_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPH_SHIFT) & QEIV2_CR_PAUSEPH_MASK) 202 #define QEIV2_CR_PAUSEPH_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPH_MASK) >> QEIV2_CR_PAUSEPH_SHIFT) 203 204 /* 205 * PAUSEZ (RW) 206 * 207 * 1- pause zcnt when PAUSE assert 208 */ 209 #define QEIV2_CR_PAUSEZ_MASK (0x1000U) 210 #define QEIV2_CR_PAUSEZ_SHIFT (12U) 211 #define QEIV2_CR_PAUSEZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEZ_SHIFT) & QEIV2_CR_PAUSEZ_MASK) 212 #define QEIV2_CR_PAUSEZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEZ_MASK) >> QEIV2_CR_PAUSEZ_SHIFT) 213 214 /* 215 * HFDIR0 (RW) 216 * 217 * 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) 218 */ 219 #define QEIV2_CR_HFDIR0_MASK (0x800U) 220 #define QEIV2_CR_HFDIR0_SHIFT (11U) 221 #define QEIV2_CR_HFDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR0_SHIFT) & QEIV2_CR_HFDIR0_MASK) 222 #define QEIV2_CR_HFDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR0_MASK) >> QEIV2_CR_HFDIR0_SHIFT) 223 224 /* 225 * HFDIR1 (RW) 226 * 227 * 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) 228 */ 229 #define QEIV2_CR_HFDIR1_MASK (0x400U) 230 #define QEIV2_CR_HFDIR1_SHIFT (10U) 231 #define QEIV2_CR_HFDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR1_SHIFT) & QEIV2_CR_HFDIR1_MASK) 232 #define QEIV2_CR_HFDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR1_MASK) >> QEIV2_CR_HFDIR1_SHIFT) 233 234 /* 235 * HRDIR0 (RW) 236 * 237 * 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) 238 */ 239 #define QEIV2_CR_HRDIR0_MASK (0x200U) 240 #define QEIV2_CR_HRDIR0_SHIFT (9U) 241 #define QEIV2_CR_HRDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR0_SHIFT) & QEIV2_CR_HRDIR0_MASK) 242 #define QEIV2_CR_HRDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR0_MASK) >> QEIV2_CR_HRDIR0_SHIFT) 243 244 /* 245 * HRDIR1 (RW) 246 * 247 * 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) 248 */ 249 #define QEIV2_CR_HRDIR1_MASK (0x100U) 250 #define QEIV2_CR_HRDIR1_SHIFT (8U) 251 #define QEIV2_CR_HRDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR1_SHIFT) & QEIV2_CR_HRDIR1_MASK) 252 #define QEIV2_CR_HRDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR1_MASK) >> QEIV2_CR_HRDIR1_SHIFT) 253 254 /* 255 * FAULTPOS (RW) 256 * 257 */ 258 #define QEIV2_CR_FAULTPOS_MASK (0x40U) 259 #define QEIV2_CR_FAULTPOS_SHIFT (6U) 260 #define QEIV2_CR_FAULTPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_FAULTPOS_SHIFT) & QEIV2_CR_FAULTPOS_MASK) 261 #define QEIV2_CR_FAULTPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_FAULTPOS_MASK) >> QEIV2_CR_FAULTPOS_SHIFT) 262 263 /* 264 * SNAPEN (RW) 265 * 266 * 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert 267 */ 268 #define QEIV2_CR_SNAPEN_MASK (0x20U) 269 #define QEIV2_CR_SNAPEN_SHIFT (5U) 270 #define QEIV2_CR_SNAPEN_SET(x) (((uint32_t)(x) << QEIV2_CR_SNAPEN_SHIFT) & QEIV2_CR_SNAPEN_MASK) 271 #define QEIV2_CR_SNAPEN_GET(x) (((uint32_t)(x) & QEIV2_CR_SNAPEN_MASK) >> QEIV2_CR_SNAPEN_SHIFT) 272 273 /* 274 * RSTCNT (RW) 275 * 276 * 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx 277 */ 278 #define QEIV2_CR_RSTCNT_MASK (0x10U) 279 #define QEIV2_CR_RSTCNT_SHIFT (4U) 280 #define QEIV2_CR_RSTCNT_SET(x) (((uint32_t)(x) << QEIV2_CR_RSTCNT_SHIFT) & QEIV2_CR_RSTCNT_MASK) 281 #define QEIV2_CR_RSTCNT_GET(x) (((uint32_t)(x) & QEIV2_CR_RSTCNT_MASK) >> QEIV2_CR_RSTCNT_SHIFT) 282 283 /* 284 * RD_SEL (RW) 285 * 286 * define the width/counter value(affect width_match, width_match2, width_cur, timer_cur, width_read, timer_read, 287 * width_snap0,width_snap1, timer_snap0, timer_snap1) 288 * 0 : same as hpm1000/500/500s; 289 * 1: use width for position; use timer for angle 290 */ 291 #define QEIV2_CR_RD_SEL_MASK (0x8U) 292 #define QEIV2_CR_RD_SEL_SHIFT (3U) 293 #define QEIV2_CR_RD_SEL_SET(x) (((uint32_t)(x) << QEIV2_CR_RD_SEL_SHIFT) & QEIV2_CR_RD_SEL_MASK) 294 #define QEIV2_CR_RD_SEL_GET(x) (((uint32_t)(x) & QEIV2_CR_RD_SEL_MASK) >> QEIV2_CR_RD_SEL_SHIFT) 295 296 /* 297 * ENCTYP (RW) 298 * 299 * 000-abz; 001-pd; 010-ud; 011-UVW(hal) 300 * 100-single A; 101-single sin; 110: sin&cos 301 */ 302 #define QEIV2_CR_ENCTYP_MASK (0x7U) 303 #define QEIV2_CR_ENCTYP_SHIFT (0U) 304 #define QEIV2_CR_ENCTYP_SET(x) (((uint32_t)(x) << QEIV2_CR_ENCTYP_SHIFT) & QEIV2_CR_ENCTYP_MASK) 305 #define QEIV2_CR_ENCTYP_GET(x) (((uint32_t)(x) & QEIV2_CR_ENCTYP_MASK) >> QEIV2_CR_ENCTYP_SHIFT) 306 307 /* Bitfield definition for register: PHCFG */ 308 /* 309 * PHMAX (RW) 310 * 311 * maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax 312 */ 313 #define QEIV2_PHCFG_PHMAX_MASK (0xFFFFFFFFUL) 314 #define QEIV2_PHCFG_PHMAX_SHIFT (0U) 315 #define QEIV2_PHCFG_PHMAX_SET(x) (((uint32_t)(x) << QEIV2_PHCFG_PHMAX_SHIFT) & QEIV2_PHCFG_PHMAX_MASK) 316 #define QEIV2_PHCFG_PHMAX_GET(x) (((uint32_t)(x) & QEIV2_PHCFG_PHMAX_MASK) >> QEIV2_PHCFG_PHMAX_SHIFT) 317 318 /* Bitfield definition for register: WDGCFG */ 319 /* 320 * WDGEN (RW) 321 * 322 * 1- enable wdog counter 323 */ 324 #define QEIV2_WDGCFG_WDGEN_MASK (0x80000000UL) 325 #define QEIV2_WDGCFG_WDGEN_SHIFT (31U) 326 #define QEIV2_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGEN_SHIFT) & QEIV2_WDGCFG_WDGEN_MASK) 327 #define QEIV2_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGEN_MASK) >> QEIV2_WDGCFG_WDGEN_SHIFT) 328 329 /* 330 * WDOG_CFG (RW) 331 * 332 * define as stop if phase_cnt change is less than it 333 * if 0, then each change of phase_cnt will clear wdog counter; 334 * if 2, then phase_cnt change larger than 2 will clear wdog counter 335 */ 336 #define QEIV2_WDGCFG_WDOG_CFG_MASK (0x70000000UL) 337 #define QEIV2_WDGCFG_WDOG_CFG_SHIFT (28U) 338 #define QEIV2_WDGCFG_WDOG_CFG_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDOG_CFG_SHIFT) & QEIV2_WDGCFG_WDOG_CFG_MASK) 339 #define QEIV2_WDGCFG_WDOG_CFG_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDOG_CFG_MASK) >> QEIV2_WDGCFG_WDOG_CFG_SHIFT) 340 341 /* 342 * WDGTO (RW) 343 * 344 * watch dog timeout value 345 */ 346 #define QEIV2_WDGCFG_WDGTO_MASK (0xFFFFFFFUL) 347 #define QEIV2_WDGCFG_WDGTO_SHIFT (0U) 348 #define QEIV2_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGTO_SHIFT) & QEIV2_WDGCFG_WDGTO_MASK) 349 #define QEIV2_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGTO_MASK) >> QEIV2_WDGCFG_WDGTO_SHIFT) 350 351 /* Bitfield definition for register: PHIDX */ 352 /* 353 * PHIDX (RW) 354 * 355 * phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 356 */ 357 #define QEIV2_PHIDX_PHIDX_MASK (0xFFFFFFFFUL) 358 #define QEIV2_PHIDX_PHIDX_SHIFT (0U) 359 #define QEIV2_PHIDX_PHIDX_SET(x) (((uint32_t)(x) << QEIV2_PHIDX_PHIDX_SHIFT) & QEIV2_PHIDX_PHIDX_MASK) 360 #define QEIV2_PHIDX_PHIDX_GET(x) (((uint32_t)(x) & QEIV2_PHIDX_PHIDX_MASK) >> QEIV2_PHIDX_PHIDX_SHIFT) 361 362 /* Bitfield definition for register: TRGOEN */ 363 /* 364 * WDGFEN (RW) 365 * 366 * 1- enable trigger output when wdg flag set 367 */ 368 #define QEIV2_TRGOEN_WDGFEN_MASK (0x80000000UL) 369 #define QEIV2_TRGOEN_WDGFEN_SHIFT (31U) 370 #define QEIV2_TRGOEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WDGFEN_SHIFT) & QEIV2_TRGOEN_WDGFEN_MASK) 371 #define QEIV2_TRGOEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WDGFEN_MASK) >> QEIV2_TRGOEN_WDGFEN_SHIFT) 372 373 /* 374 * HOMEFEN (RW) 375 * 376 * 1- enable trigger output when homef flag set 377 */ 378 #define QEIV2_TRGOEN_HOMEFEN_MASK (0x40000000UL) 379 #define QEIV2_TRGOEN_HOMEFEN_SHIFT (30U) 380 #define QEIV2_TRGOEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOMEFEN_SHIFT) & QEIV2_TRGOEN_HOMEFEN_MASK) 381 #define QEIV2_TRGOEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOMEFEN_MASK) >> QEIV2_TRGOEN_HOMEFEN_SHIFT) 382 383 /* 384 * POSCMPFEN (RW) 385 * 386 * 1- enable trigger output when poscmpf flag set 387 */ 388 #define QEIV2_TRGOEN_POSCMPFEN_MASK (0x20000000UL) 389 #define QEIV2_TRGOEN_POSCMPFEN_SHIFT (29U) 390 #define QEIV2_TRGOEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POSCMPFEN_SHIFT) & QEIV2_TRGOEN_POSCMPFEN_MASK) 391 #define QEIV2_TRGOEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POSCMPFEN_MASK) >> QEIV2_TRGOEN_POSCMPFEN_SHIFT) 392 393 /* 394 * ZPHFEN (RW) 395 * 396 * 1- enable trigger output when zphf flag set 397 */ 398 #define QEIV2_TRGOEN_ZPHFEN_MASK (0x10000000UL) 399 #define QEIV2_TRGOEN_ZPHFEN_SHIFT (28U) 400 #define QEIV2_TRGOEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZPHFEN_SHIFT) & QEIV2_TRGOEN_ZPHFEN_MASK) 401 #define QEIV2_TRGOEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZPHFEN_MASK) >> QEIV2_TRGOEN_ZPHFEN_SHIFT) 402 403 /* 404 * ZMISSFEN (RW) 405 * 406 */ 407 #define QEIV2_TRGOEN_ZMISSFEN_MASK (0x8000000UL) 408 #define QEIV2_TRGOEN_ZMISSFEN_SHIFT (27U) 409 #define QEIV2_TRGOEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZMISSFEN_SHIFT) & QEIV2_TRGOEN_ZMISSFEN_MASK) 410 #define QEIV2_TRGOEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZMISSFEN_MASK) >> QEIV2_TRGOEN_ZMISSFEN_SHIFT) 411 412 /* 413 * WIDTHTMFEN (RW) 414 * 415 */ 416 #define QEIV2_TRGOEN_WIDTHTMFEN_MASK (0x4000000UL) 417 #define QEIV2_TRGOEN_WIDTHTMFEN_SHIFT (26U) 418 #define QEIV2_TRGOEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WIDTHTMFEN_SHIFT) & QEIV2_TRGOEN_WIDTHTMFEN_MASK) 419 #define QEIV2_TRGOEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WIDTHTMFEN_MASK) >> QEIV2_TRGOEN_WIDTHTMFEN_SHIFT) 420 421 /* 422 * POS2CMPFEN (RW) 423 * 424 */ 425 #define QEIV2_TRGOEN_POS2CMPFEN_MASK (0x2000000UL) 426 #define QEIV2_TRGOEN_POS2CMPFEN_SHIFT (25U) 427 #define QEIV2_TRGOEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POS2CMPFEN_SHIFT) & QEIV2_TRGOEN_POS2CMPFEN_MASK) 428 #define QEIV2_TRGOEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POS2CMPFEN_MASK) >> QEIV2_TRGOEN_POS2CMPFEN_SHIFT) 429 430 /* 431 * DIRCHGFEN (RW) 432 * 433 */ 434 #define QEIV2_TRGOEN_DIRCHGFEN_MASK (0x1000000UL) 435 #define QEIV2_TRGOEN_DIRCHGFEN_SHIFT (24U) 436 #define QEIV2_TRGOEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_DIRCHGFEN_SHIFT) & QEIV2_TRGOEN_DIRCHGFEN_MASK) 437 #define QEIV2_TRGOEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_DIRCHGFEN_MASK) >> QEIV2_TRGOEN_DIRCHGFEN_SHIFT) 438 439 /* 440 * CYCLE0FEN (RW) 441 * 442 */ 443 #define QEIV2_TRGOEN_CYCLE0FEN_MASK (0x800000UL) 444 #define QEIV2_TRGOEN_CYCLE0FEN_SHIFT (23U) 445 #define QEIV2_TRGOEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE0FEN_SHIFT) & QEIV2_TRGOEN_CYCLE0FEN_MASK) 446 #define QEIV2_TRGOEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE0FEN_MASK) >> QEIV2_TRGOEN_CYCLE0FEN_SHIFT) 447 448 /* 449 * CYCLE1FEN (RW) 450 * 451 */ 452 #define QEIV2_TRGOEN_CYCLE1FEN_MASK (0x400000UL) 453 #define QEIV2_TRGOEN_CYCLE1FEN_SHIFT (22U) 454 #define QEIV2_TRGOEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE1FEN_SHIFT) & QEIV2_TRGOEN_CYCLE1FEN_MASK) 455 #define QEIV2_TRGOEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE1FEN_MASK) >> QEIV2_TRGOEN_CYCLE1FEN_SHIFT) 456 457 /* 458 * PULSE0FEN (RW) 459 * 460 */ 461 #define QEIV2_TRGOEN_PULSE0FEN_MASK (0x200000UL) 462 #define QEIV2_TRGOEN_PULSE0FEN_SHIFT (21U) 463 #define QEIV2_TRGOEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE0FEN_SHIFT) & QEIV2_TRGOEN_PULSE0FEN_MASK) 464 #define QEIV2_TRGOEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE0FEN_MASK) >> QEIV2_TRGOEN_PULSE0FEN_SHIFT) 465 466 /* 467 * PULSE1FEN (RW) 468 * 469 */ 470 #define QEIV2_TRGOEN_PULSE1FEN_MASK (0x100000UL) 471 #define QEIV2_TRGOEN_PULSE1FEN_SHIFT (20U) 472 #define QEIV2_TRGOEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE1FEN_SHIFT) & QEIV2_TRGOEN_PULSE1FEN_MASK) 473 #define QEIV2_TRGOEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE1FEN_MASK) >> QEIV2_TRGOEN_PULSE1FEN_SHIFT) 474 475 /* 476 * HOME2FEN (RW) 477 * 478 */ 479 #define QEIV2_TRGOEN_HOME2FEN_MASK (0x80000UL) 480 #define QEIV2_TRGOEN_HOME2FEN_SHIFT (19U) 481 #define QEIV2_TRGOEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOME2FEN_SHIFT) & QEIV2_TRGOEN_HOME2FEN_MASK) 482 #define QEIV2_TRGOEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOME2FEN_MASK) >> QEIV2_TRGOEN_HOME2FEN_SHIFT) 483 484 /* 485 * FAULTFEN (RW) 486 * 487 */ 488 #define QEIV2_TRGOEN_FAULTFEN_MASK (0x40000UL) 489 #define QEIV2_TRGOEN_FAULTFEN_SHIFT (18U) 490 #define QEIV2_TRGOEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_FAULTFEN_SHIFT) & QEIV2_TRGOEN_FAULTFEN_MASK) 491 #define QEIV2_TRGOEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_FAULTFEN_MASK) >> QEIV2_TRGOEN_FAULTFEN_SHIFT) 492 493 /* Bitfield definition for register: READEN */ 494 /* 495 * WDGFEN (RW) 496 * 497 * 1- load counters to their read registers when wdg flag set 498 */ 499 #define QEIV2_READEN_WDGFEN_MASK (0x80000000UL) 500 #define QEIV2_READEN_WDGFEN_SHIFT (31U) 501 #define QEIV2_READEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WDGFEN_SHIFT) & QEIV2_READEN_WDGFEN_MASK) 502 #define QEIV2_READEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WDGFEN_MASK) >> QEIV2_READEN_WDGFEN_SHIFT) 503 504 /* 505 * HOMEFEN (RW) 506 * 507 * 1- load counters to their read registers when homef flag set 508 */ 509 #define QEIV2_READEN_HOMEFEN_MASK (0x40000000UL) 510 #define QEIV2_READEN_HOMEFEN_SHIFT (30U) 511 #define QEIV2_READEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOMEFEN_SHIFT) & QEIV2_READEN_HOMEFEN_MASK) 512 #define QEIV2_READEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOMEFEN_MASK) >> QEIV2_READEN_HOMEFEN_SHIFT) 513 514 /* 515 * POSCMPFEN (RW) 516 * 517 * 1- load counters to their read registers when poscmpf flag set 518 */ 519 #define QEIV2_READEN_POSCMPFEN_MASK (0x20000000UL) 520 #define QEIV2_READEN_POSCMPFEN_SHIFT (29U) 521 #define QEIV2_READEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POSCMPFEN_SHIFT) & QEIV2_READEN_POSCMPFEN_MASK) 522 #define QEIV2_READEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POSCMPFEN_MASK) >> QEIV2_READEN_POSCMPFEN_SHIFT) 523 524 /* 525 * ZPHFEN (RW) 526 * 527 * 1- load counters to their read registers when zphf flag set 528 */ 529 #define QEIV2_READEN_ZPHFEN_MASK (0x10000000UL) 530 #define QEIV2_READEN_ZPHFEN_SHIFT (28U) 531 #define QEIV2_READEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZPHFEN_SHIFT) & QEIV2_READEN_ZPHFEN_MASK) 532 #define QEIV2_READEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZPHFEN_MASK) >> QEIV2_READEN_ZPHFEN_SHIFT) 533 534 /* 535 * ZMISSFEN (RW) 536 * 537 */ 538 #define QEIV2_READEN_ZMISSFEN_MASK (0x8000000UL) 539 #define QEIV2_READEN_ZMISSFEN_SHIFT (27U) 540 #define QEIV2_READEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZMISSFEN_SHIFT) & QEIV2_READEN_ZMISSFEN_MASK) 541 #define QEIV2_READEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZMISSFEN_MASK) >> QEIV2_READEN_ZMISSFEN_SHIFT) 542 543 /* 544 * WIDTHTMFEN (RW) 545 * 546 */ 547 #define QEIV2_READEN_WIDTHTMFEN_MASK (0x4000000UL) 548 #define QEIV2_READEN_WIDTHTMFEN_SHIFT (26U) 549 #define QEIV2_READEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WIDTHTMFEN_SHIFT) & QEIV2_READEN_WIDTHTMFEN_MASK) 550 #define QEIV2_READEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WIDTHTMFEN_MASK) >> QEIV2_READEN_WIDTHTMFEN_SHIFT) 551 552 /* 553 * POS2CMPFEN (RW) 554 * 555 */ 556 #define QEIV2_READEN_POS2CMPFEN_MASK (0x2000000UL) 557 #define QEIV2_READEN_POS2CMPFEN_SHIFT (25U) 558 #define QEIV2_READEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POS2CMPFEN_SHIFT) & QEIV2_READEN_POS2CMPFEN_MASK) 559 #define QEIV2_READEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POS2CMPFEN_MASK) >> QEIV2_READEN_POS2CMPFEN_SHIFT) 560 561 /* 562 * DIRCHGFEN (RW) 563 * 564 */ 565 #define QEIV2_READEN_DIRCHGFEN_MASK (0x1000000UL) 566 #define QEIV2_READEN_DIRCHGFEN_SHIFT (24U) 567 #define QEIV2_READEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_DIRCHGFEN_SHIFT) & QEIV2_READEN_DIRCHGFEN_MASK) 568 #define QEIV2_READEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_DIRCHGFEN_MASK) >> QEIV2_READEN_DIRCHGFEN_SHIFT) 569 570 /* 571 * CYCLE0FEN (RW) 572 * 573 */ 574 #define QEIV2_READEN_CYCLE0FEN_MASK (0x800000UL) 575 #define QEIV2_READEN_CYCLE0FEN_SHIFT (23U) 576 #define QEIV2_READEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE0FEN_SHIFT) & QEIV2_READEN_CYCLE0FEN_MASK) 577 #define QEIV2_READEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE0FEN_MASK) >> QEIV2_READEN_CYCLE0FEN_SHIFT) 578 579 /* 580 * CYCLE1FEN (RW) 581 * 582 */ 583 #define QEIV2_READEN_CYCLE1FEN_MASK (0x400000UL) 584 #define QEIV2_READEN_CYCLE1FEN_SHIFT (22U) 585 #define QEIV2_READEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE1FEN_SHIFT) & QEIV2_READEN_CYCLE1FEN_MASK) 586 #define QEIV2_READEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE1FEN_MASK) >> QEIV2_READEN_CYCLE1FEN_SHIFT) 587 588 /* 589 * PULSE0FEN (RW) 590 * 591 */ 592 #define QEIV2_READEN_PULSE0FEN_MASK (0x200000UL) 593 #define QEIV2_READEN_PULSE0FEN_SHIFT (21U) 594 #define QEIV2_READEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE0FEN_SHIFT) & QEIV2_READEN_PULSE0FEN_MASK) 595 #define QEIV2_READEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE0FEN_MASK) >> QEIV2_READEN_PULSE0FEN_SHIFT) 596 597 /* 598 * PULSE1FEN (RW) 599 * 600 */ 601 #define QEIV2_READEN_PULSE1FEN_MASK (0x100000UL) 602 #define QEIV2_READEN_PULSE1FEN_SHIFT (20U) 603 #define QEIV2_READEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE1FEN_SHIFT) & QEIV2_READEN_PULSE1FEN_MASK) 604 #define QEIV2_READEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE1FEN_MASK) >> QEIV2_READEN_PULSE1FEN_SHIFT) 605 606 /* 607 * HOME2FEN (RW) 608 * 609 */ 610 #define QEIV2_READEN_HOME2FEN_MASK (0x80000UL) 611 #define QEIV2_READEN_HOME2FEN_SHIFT (19U) 612 #define QEIV2_READEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOME2FEN_SHIFT) & QEIV2_READEN_HOME2FEN_MASK) 613 #define QEIV2_READEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOME2FEN_MASK) >> QEIV2_READEN_HOME2FEN_SHIFT) 614 615 /* 616 * FAULTFEN (RW) 617 * 618 */ 619 #define QEIV2_READEN_FAULTFEN_MASK (0x40000UL) 620 #define QEIV2_READEN_FAULTFEN_SHIFT (18U) 621 #define QEIV2_READEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_FAULTFEN_SHIFT) & QEIV2_READEN_FAULTFEN_MASK) 622 #define QEIV2_READEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_FAULTFEN_MASK) >> QEIV2_READEN_FAULTFEN_SHIFT) 623 624 /* Bitfield definition for register: ZCMP */ 625 /* 626 * ZCMP (RW) 627 * 628 * zcnt postion compare value 629 */ 630 #define QEIV2_ZCMP_ZCMP_MASK (0xFFFFFFFFUL) 631 #define QEIV2_ZCMP_ZCMP_SHIFT (0U) 632 #define QEIV2_ZCMP_ZCMP_SET(x) (((uint32_t)(x) << QEIV2_ZCMP_ZCMP_SHIFT) & QEIV2_ZCMP_ZCMP_MASK) 633 #define QEIV2_ZCMP_ZCMP_GET(x) (((uint32_t)(x) & QEIV2_ZCMP_ZCMP_MASK) >> QEIV2_ZCMP_ZCMP_SHIFT) 634 635 /* Bitfield definition for register: PHCMP */ 636 /* 637 * PHCMP (RW) 638 * 639 * phcnt position compare value 640 */ 641 #define QEIV2_PHCMP_PHCMP_MASK (0xFFFFFFFFUL) 642 #define QEIV2_PHCMP_PHCMP_SHIFT (0U) 643 #define QEIV2_PHCMP_PHCMP_SET(x) (((uint32_t)(x) << QEIV2_PHCMP_PHCMP_SHIFT) & QEIV2_PHCMP_PHCMP_MASK) 644 #define QEIV2_PHCMP_PHCMP_GET(x) (((uint32_t)(x) & QEIV2_PHCMP_PHCMP_MASK) >> QEIV2_PHCMP_PHCMP_SHIFT) 645 646 /* Bitfield definition for register: SPDCMP */ 647 /* 648 * SPDCMP (RW) 649 * 650 * spdcnt position compare value 651 */ 652 #define QEIV2_SPDCMP_SPDCMP_MASK (0xFFFFFFFFUL) 653 #define QEIV2_SPDCMP_SPDCMP_SHIFT (0U) 654 #define QEIV2_SPDCMP_SPDCMP_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP_SPDCMP_SHIFT) & QEIV2_SPDCMP_SPDCMP_MASK) 655 #define QEIV2_SPDCMP_SPDCMP_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP_SPDCMP_MASK) >> QEIV2_SPDCMP_SPDCMP_SHIFT) 656 657 /* Bitfield definition for register: DMAEN */ 658 /* 659 * WDGFEN (RW) 660 * 661 * 1- generate dma request when wdg flag set 662 */ 663 #define QEIV2_DMAEN_WDGFEN_MASK (0x80000000UL) 664 #define QEIV2_DMAEN_WDGFEN_SHIFT (31U) 665 #define QEIV2_DMAEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WDGFEN_SHIFT) & QEIV2_DMAEN_WDGFEN_MASK) 666 #define QEIV2_DMAEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WDGFEN_MASK) >> QEIV2_DMAEN_WDGFEN_SHIFT) 667 668 /* 669 * HOMEFEN (RW) 670 * 671 * 1- generate dma request when homef flag set 672 */ 673 #define QEIV2_DMAEN_HOMEFEN_MASK (0x40000000UL) 674 #define QEIV2_DMAEN_HOMEFEN_SHIFT (30U) 675 #define QEIV2_DMAEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOMEFEN_SHIFT) & QEIV2_DMAEN_HOMEFEN_MASK) 676 #define QEIV2_DMAEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOMEFEN_MASK) >> QEIV2_DMAEN_HOMEFEN_SHIFT) 677 678 /* 679 * POSCMPFEN (RW) 680 * 681 * 1- generate dma request when poscmpf flag set 682 */ 683 #define QEIV2_DMAEN_POSCMPFEN_MASK (0x20000000UL) 684 #define QEIV2_DMAEN_POSCMPFEN_SHIFT (29U) 685 #define QEIV2_DMAEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POSCMPFEN_SHIFT) & QEIV2_DMAEN_POSCMPFEN_MASK) 686 #define QEIV2_DMAEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POSCMPFEN_MASK) >> QEIV2_DMAEN_POSCMPFEN_SHIFT) 687 688 /* 689 * ZPHFEN (RW) 690 * 691 * 1- generate dma request when zphf flag set 692 */ 693 #define QEIV2_DMAEN_ZPHFEN_MASK (0x10000000UL) 694 #define QEIV2_DMAEN_ZPHFEN_SHIFT (28U) 695 #define QEIV2_DMAEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZPHFEN_SHIFT) & QEIV2_DMAEN_ZPHFEN_MASK) 696 #define QEIV2_DMAEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZPHFEN_MASK) >> QEIV2_DMAEN_ZPHFEN_SHIFT) 697 698 /* 699 * ZMISSFEN (RW) 700 * 701 */ 702 #define QEIV2_DMAEN_ZMISSFEN_MASK (0x8000000UL) 703 #define QEIV2_DMAEN_ZMISSFEN_SHIFT (27U) 704 #define QEIV2_DMAEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZMISSFEN_SHIFT) & QEIV2_DMAEN_ZMISSFEN_MASK) 705 #define QEIV2_DMAEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZMISSFEN_MASK) >> QEIV2_DMAEN_ZMISSFEN_SHIFT) 706 707 /* 708 * WIDTHTMFEN (RW) 709 * 710 */ 711 #define QEIV2_DMAEN_WIDTHTMFEN_MASK (0x4000000UL) 712 #define QEIV2_DMAEN_WIDTHTMFEN_SHIFT (26U) 713 #define QEIV2_DMAEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WIDTHTMFEN_SHIFT) & QEIV2_DMAEN_WIDTHTMFEN_MASK) 714 #define QEIV2_DMAEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WIDTHTMFEN_MASK) >> QEIV2_DMAEN_WIDTHTMFEN_SHIFT) 715 716 /* 717 * POS2CMPFEN (RW) 718 * 719 */ 720 #define QEIV2_DMAEN_POS2CMPFEN_MASK (0x2000000UL) 721 #define QEIV2_DMAEN_POS2CMPFEN_SHIFT (25U) 722 #define QEIV2_DMAEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POS2CMPFEN_SHIFT) & QEIV2_DMAEN_POS2CMPFEN_MASK) 723 #define QEIV2_DMAEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POS2CMPFEN_MASK) >> QEIV2_DMAEN_POS2CMPFEN_SHIFT) 724 725 /* 726 * DIRCHGFEN (RW) 727 * 728 */ 729 #define QEIV2_DMAEN_DIRCHGFEN_MASK (0x1000000UL) 730 #define QEIV2_DMAEN_DIRCHGFEN_SHIFT (24U) 731 #define QEIV2_DMAEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_DIRCHGFEN_SHIFT) & QEIV2_DMAEN_DIRCHGFEN_MASK) 732 #define QEIV2_DMAEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_DIRCHGFEN_MASK) >> QEIV2_DMAEN_DIRCHGFEN_SHIFT) 733 734 /* 735 * CYCLE0FEN (RW) 736 * 737 */ 738 #define QEIV2_DMAEN_CYCLE0FEN_MASK (0x800000UL) 739 #define QEIV2_DMAEN_CYCLE0FEN_SHIFT (23U) 740 #define QEIV2_DMAEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE0FEN_SHIFT) & QEIV2_DMAEN_CYCLE0FEN_MASK) 741 #define QEIV2_DMAEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE0FEN_MASK) >> QEIV2_DMAEN_CYCLE0FEN_SHIFT) 742 743 /* 744 * CYCLE1FEN (RW) 745 * 746 */ 747 #define QEIV2_DMAEN_CYCLE1FEN_MASK (0x400000UL) 748 #define QEIV2_DMAEN_CYCLE1FEN_SHIFT (22U) 749 #define QEIV2_DMAEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE1FEN_SHIFT) & QEIV2_DMAEN_CYCLE1FEN_MASK) 750 #define QEIV2_DMAEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE1FEN_MASK) >> QEIV2_DMAEN_CYCLE1FEN_SHIFT) 751 752 /* 753 * PULSE0FEN (RW) 754 * 755 */ 756 #define QEIV2_DMAEN_PULSE0FEN_MASK (0x200000UL) 757 #define QEIV2_DMAEN_PULSE0FEN_SHIFT (21U) 758 #define QEIV2_DMAEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE0FEN_SHIFT) & QEIV2_DMAEN_PULSE0FEN_MASK) 759 #define QEIV2_DMAEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE0FEN_MASK) >> QEIV2_DMAEN_PULSE0FEN_SHIFT) 760 761 /* 762 * PULSE1FEN (RW) 763 * 764 */ 765 #define QEIV2_DMAEN_PULSE1FEN_MASK (0x100000UL) 766 #define QEIV2_DMAEN_PULSE1FEN_SHIFT (20U) 767 #define QEIV2_DMAEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE1FEN_SHIFT) & QEIV2_DMAEN_PULSE1FEN_MASK) 768 #define QEIV2_DMAEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE1FEN_MASK) >> QEIV2_DMAEN_PULSE1FEN_SHIFT) 769 770 /* 771 * HOME2FEN (RW) 772 * 773 */ 774 #define QEIV2_DMAEN_HOME2FEN_MASK (0x80000UL) 775 #define QEIV2_DMAEN_HOME2FEN_SHIFT (19U) 776 #define QEIV2_DMAEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOME2FEN_SHIFT) & QEIV2_DMAEN_HOME2FEN_MASK) 777 #define QEIV2_DMAEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOME2FEN_MASK) >> QEIV2_DMAEN_HOME2FEN_SHIFT) 778 779 /* 780 * FAULTFEN (RW) 781 * 782 */ 783 #define QEIV2_DMAEN_FAULTFEN_MASK (0x40000UL) 784 #define QEIV2_DMAEN_FAULTFEN_SHIFT (18U) 785 #define QEIV2_DMAEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_FAULTFEN_SHIFT) & QEIV2_DMAEN_FAULTFEN_MASK) 786 #define QEIV2_DMAEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_FAULTFEN_MASK) >> QEIV2_DMAEN_FAULTFEN_SHIFT) 787 788 /* Bitfield definition for register: SR */ 789 /* 790 * WDGF (RW) 791 * 792 * watchdog flag 793 */ 794 #define QEIV2_SR_WDGF_MASK (0x80000000UL) 795 #define QEIV2_SR_WDGF_SHIFT (31U) 796 #define QEIV2_SR_WDGF_SET(x) (((uint32_t)(x) << QEIV2_SR_WDGF_SHIFT) & QEIV2_SR_WDGF_MASK) 797 #define QEIV2_SR_WDGF_GET(x) (((uint32_t)(x) & QEIV2_SR_WDGF_MASK) >> QEIV2_SR_WDGF_SHIFT) 798 799 /* 800 * HOMEF (RW) 801 * 802 * home flag 803 */ 804 #define QEIV2_SR_HOMEF_MASK (0x40000000UL) 805 #define QEIV2_SR_HOMEF_SHIFT (30U) 806 #define QEIV2_SR_HOMEF_SET(x) (((uint32_t)(x) << QEIV2_SR_HOMEF_SHIFT) & QEIV2_SR_HOMEF_MASK) 807 #define QEIV2_SR_HOMEF_GET(x) (((uint32_t)(x) & QEIV2_SR_HOMEF_MASK) >> QEIV2_SR_HOMEF_SHIFT) 808 809 /* 810 * POSCMPF (RW) 811 * 812 * postion compare match flag 813 */ 814 #define QEIV2_SR_POSCMPF_MASK (0x20000000UL) 815 #define QEIV2_SR_POSCMPF_SHIFT (29U) 816 #define QEIV2_SR_POSCMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POSCMPF_SHIFT) & QEIV2_SR_POSCMPF_MASK) 817 #define QEIV2_SR_POSCMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POSCMPF_MASK) >> QEIV2_SR_POSCMPF_SHIFT) 818 819 /* 820 * ZPHF (RW) 821 * 822 * z input flag 823 */ 824 #define QEIV2_SR_ZPHF_MASK (0x10000000UL) 825 #define QEIV2_SR_ZPHF_SHIFT (28U) 826 #define QEIV2_SR_ZPHF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZPHF_SHIFT) & QEIV2_SR_ZPHF_MASK) 827 #define QEIV2_SR_ZPHF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZPHF_MASK) >> QEIV2_SR_ZPHF_SHIFT) 828 829 /* 830 * ZMISSF (RW) 831 * 832 */ 833 #define QEIV2_SR_ZMISSF_MASK (0x8000000UL) 834 #define QEIV2_SR_ZMISSF_SHIFT (27U) 835 #define QEIV2_SR_ZMISSF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZMISSF_SHIFT) & QEIV2_SR_ZMISSF_MASK) 836 #define QEIV2_SR_ZMISSF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZMISSF_MASK) >> QEIV2_SR_ZMISSF_SHIFT) 837 838 /* 839 * WIDTHTMF (RW) 840 * 841 */ 842 #define QEIV2_SR_WIDTHTMF_MASK (0x4000000UL) 843 #define QEIV2_SR_WIDTHTMF_SHIFT (26U) 844 #define QEIV2_SR_WIDTHTMF_SET(x) (((uint32_t)(x) << QEIV2_SR_WIDTHTMF_SHIFT) & QEIV2_SR_WIDTHTMF_MASK) 845 #define QEIV2_SR_WIDTHTMF_GET(x) (((uint32_t)(x) & QEIV2_SR_WIDTHTMF_MASK) >> QEIV2_SR_WIDTHTMF_SHIFT) 846 847 /* 848 * POS2CMPF (RW) 849 * 850 */ 851 #define QEIV2_SR_POS2CMPF_MASK (0x2000000UL) 852 #define QEIV2_SR_POS2CMPF_SHIFT (25U) 853 #define QEIV2_SR_POS2CMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POS2CMPF_SHIFT) & QEIV2_SR_POS2CMPF_MASK) 854 #define QEIV2_SR_POS2CMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POS2CMPF_MASK) >> QEIV2_SR_POS2CMPF_SHIFT) 855 856 /* 857 * DIRCHGF (RW) 858 * 859 */ 860 #define QEIV2_SR_DIRCHGF_MASK (0x1000000UL) 861 #define QEIV2_SR_DIRCHGF_SHIFT (24U) 862 #define QEIV2_SR_DIRCHGF_SET(x) (((uint32_t)(x) << QEIV2_SR_DIRCHGF_SHIFT) & QEIV2_SR_DIRCHGF_MASK) 863 #define QEIV2_SR_DIRCHGF_GET(x) (((uint32_t)(x) & QEIV2_SR_DIRCHGF_MASK) >> QEIV2_SR_DIRCHGF_SHIFT) 864 865 /* 866 * CYCLE0F (RW) 867 * 868 */ 869 #define QEIV2_SR_CYCLE0F_MASK (0x800000UL) 870 #define QEIV2_SR_CYCLE0F_SHIFT (23U) 871 #define QEIV2_SR_CYCLE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE0F_SHIFT) & QEIV2_SR_CYCLE0F_MASK) 872 #define QEIV2_SR_CYCLE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE0F_MASK) >> QEIV2_SR_CYCLE0F_SHIFT) 873 874 /* 875 * CYCLE1F (RW) 876 * 877 */ 878 #define QEIV2_SR_CYCLE1F_MASK (0x400000UL) 879 #define QEIV2_SR_CYCLE1F_SHIFT (22U) 880 #define QEIV2_SR_CYCLE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE1F_SHIFT) & QEIV2_SR_CYCLE1F_MASK) 881 #define QEIV2_SR_CYCLE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE1F_MASK) >> QEIV2_SR_CYCLE1F_SHIFT) 882 883 /* 884 * PULSE0F (RW) 885 * 886 */ 887 #define QEIV2_SR_PULSE0F_MASK (0x200000UL) 888 #define QEIV2_SR_PULSE0F_SHIFT (21U) 889 #define QEIV2_SR_PULSE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE0F_SHIFT) & QEIV2_SR_PULSE0F_MASK) 890 #define QEIV2_SR_PULSE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE0F_MASK) >> QEIV2_SR_PULSE0F_SHIFT) 891 892 /* 893 * PULSE1F (RW) 894 * 895 */ 896 #define QEIV2_SR_PULSE1F_MASK (0x100000UL) 897 #define QEIV2_SR_PULSE1F_SHIFT (20U) 898 #define QEIV2_SR_PULSE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE1F_SHIFT) & QEIV2_SR_PULSE1F_MASK) 899 #define QEIV2_SR_PULSE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE1F_MASK) >> QEIV2_SR_PULSE1F_SHIFT) 900 901 /* 902 * HOME2F (RW) 903 * 904 */ 905 #define QEIV2_SR_HOME2F_MASK (0x80000UL) 906 #define QEIV2_SR_HOME2F_SHIFT (19U) 907 #define QEIV2_SR_HOME2F_SET(x) (((uint32_t)(x) << QEIV2_SR_HOME2F_SHIFT) & QEIV2_SR_HOME2F_MASK) 908 #define QEIV2_SR_HOME2F_GET(x) (((uint32_t)(x) & QEIV2_SR_HOME2F_MASK) >> QEIV2_SR_HOME2F_SHIFT) 909 910 /* 911 * FAULTF (RW) 912 * 913 */ 914 #define QEIV2_SR_FAULTF_MASK (0x40000UL) 915 #define QEIV2_SR_FAULTF_SHIFT (18U) 916 #define QEIV2_SR_FAULTF_SET(x) (((uint32_t)(x) << QEIV2_SR_FAULTF_SHIFT) & QEIV2_SR_FAULTF_MASK) 917 #define QEIV2_SR_FAULTF_GET(x) (((uint32_t)(x) & QEIV2_SR_FAULTF_MASK) >> QEIV2_SR_FAULTF_SHIFT) 918 919 /* Bitfield definition for register: IRQEN */ 920 /* 921 * WDGIE (RW) 922 * 923 * 1- generate interrupt when wdg flag set 924 */ 925 #define QEIV2_IRQEN_WDGIE_MASK (0x80000000UL) 926 #define QEIV2_IRQEN_WDGIE_SHIFT (31U) 927 #define QEIV2_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WDGIE_SHIFT) & QEIV2_IRQEN_WDGIE_MASK) 928 #define QEIV2_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WDGIE_MASK) >> QEIV2_IRQEN_WDGIE_SHIFT) 929 930 /* 931 * HOMEIE (RW) 932 * 933 * 1- generate interrupt when homef flag set 934 */ 935 #define QEIV2_IRQEN_HOMEIE_MASK (0x40000000UL) 936 #define QEIV2_IRQEN_HOMEIE_SHIFT (30U) 937 #define QEIV2_IRQEN_HOMEIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOMEIE_SHIFT) & QEIV2_IRQEN_HOMEIE_MASK) 938 #define QEIV2_IRQEN_HOMEIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOMEIE_MASK) >> QEIV2_IRQEN_HOMEIE_SHIFT) 939 940 /* 941 * POSCMPIE (RW) 942 * 943 * 1- generate interrupt when poscmpf flag set 944 */ 945 #define QEIV2_IRQEN_POSCMPIE_MASK (0x20000000UL) 946 #define QEIV2_IRQEN_POSCMPIE_SHIFT (29U) 947 #define QEIV2_IRQEN_POSCMPIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POSCMPIE_SHIFT) & QEIV2_IRQEN_POSCMPIE_MASK) 948 #define QEIV2_IRQEN_POSCMPIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POSCMPIE_MASK) >> QEIV2_IRQEN_POSCMPIE_SHIFT) 949 950 /* 951 * ZPHIE (RW) 952 * 953 * 1- generate interrupt when zphf flag set 954 */ 955 #define QEIV2_IRQEN_ZPHIE_MASK (0x10000000UL) 956 #define QEIV2_IRQEN_ZPHIE_SHIFT (28U) 957 #define QEIV2_IRQEN_ZPHIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZPHIE_SHIFT) & QEIV2_IRQEN_ZPHIE_MASK) 958 #define QEIV2_IRQEN_ZPHIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZPHIE_MASK) >> QEIV2_IRQEN_ZPHIE_SHIFT) 959 960 /* 961 * ZMISSE (RW) 962 * 963 */ 964 #define QEIV2_IRQEN_ZMISSE_MASK (0x8000000UL) 965 #define QEIV2_IRQEN_ZMISSE_SHIFT (27U) 966 #define QEIV2_IRQEN_ZMISSE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZMISSE_SHIFT) & QEIV2_IRQEN_ZMISSE_MASK) 967 #define QEIV2_IRQEN_ZMISSE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZMISSE_MASK) >> QEIV2_IRQEN_ZMISSE_SHIFT) 968 969 /* 970 * WIDTHTME (RW) 971 * 972 */ 973 #define QEIV2_IRQEN_WIDTHTME_MASK (0x4000000UL) 974 #define QEIV2_IRQEN_WIDTHTME_SHIFT (26U) 975 #define QEIV2_IRQEN_WIDTHTME_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WIDTHTME_SHIFT) & QEIV2_IRQEN_WIDTHTME_MASK) 976 #define QEIV2_IRQEN_WIDTHTME_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WIDTHTME_MASK) >> QEIV2_IRQEN_WIDTHTME_SHIFT) 977 978 /* 979 * POS2CMPE (RW) 980 * 981 */ 982 #define QEIV2_IRQEN_POS2CMPE_MASK (0x2000000UL) 983 #define QEIV2_IRQEN_POS2CMPE_SHIFT (25U) 984 #define QEIV2_IRQEN_POS2CMPE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POS2CMPE_SHIFT) & QEIV2_IRQEN_POS2CMPE_MASK) 985 #define QEIV2_IRQEN_POS2CMPE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POS2CMPE_MASK) >> QEIV2_IRQEN_POS2CMPE_SHIFT) 986 987 /* 988 * DIRCHGE (RW) 989 * 990 */ 991 #define QEIV2_IRQEN_DIRCHGE_MASK (0x1000000UL) 992 #define QEIV2_IRQEN_DIRCHGE_SHIFT (24U) 993 #define QEIV2_IRQEN_DIRCHGE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_DIRCHGE_SHIFT) & QEIV2_IRQEN_DIRCHGE_MASK) 994 #define QEIV2_IRQEN_DIRCHGE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_DIRCHGE_MASK) >> QEIV2_IRQEN_DIRCHGE_SHIFT) 995 996 /* 997 * CYCLE0E (RW) 998 * 999 */ 1000 #define QEIV2_IRQEN_CYCLE0E_MASK (0x800000UL) 1001 #define QEIV2_IRQEN_CYCLE0E_SHIFT (23U) 1002 #define QEIV2_IRQEN_CYCLE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE0E_SHIFT) & QEIV2_IRQEN_CYCLE0E_MASK) 1003 #define QEIV2_IRQEN_CYCLE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE0E_MASK) >> QEIV2_IRQEN_CYCLE0E_SHIFT) 1004 1005 /* 1006 * CYCLE1E (RW) 1007 * 1008 */ 1009 #define QEIV2_IRQEN_CYCLE1E_MASK (0x400000UL) 1010 #define QEIV2_IRQEN_CYCLE1E_SHIFT (22U) 1011 #define QEIV2_IRQEN_CYCLE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE1E_SHIFT) & QEIV2_IRQEN_CYCLE1E_MASK) 1012 #define QEIV2_IRQEN_CYCLE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE1E_MASK) >> QEIV2_IRQEN_CYCLE1E_SHIFT) 1013 1014 /* 1015 * PULSE0E (RW) 1016 * 1017 */ 1018 #define QEIV2_IRQEN_PULSE0E_MASK (0x200000UL) 1019 #define QEIV2_IRQEN_PULSE0E_SHIFT (21U) 1020 #define QEIV2_IRQEN_PULSE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE0E_SHIFT) & QEIV2_IRQEN_PULSE0E_MASK) 1021 #define QEIV2_IRQEN_PULSE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE0E_MASK) >> QEIV2_IRQEN_PULSE0E_SHIFT) 1022 1023 /* 1024 * PULSE1E (RW) 1025 * 1026 */ 1027 #define QEIV2_IRQEN_PULSE1E_MASK (0x100000UL) 1028 #define QEIV2_IRQEN_PULSE1E_SHIFT (20U) 1029 #define QEIV2_IRQEN_PULSE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE1E_SHIFT) & QEIV2_IRQEN_PULSE1E_MASK) 1030 #define QEIV2_IRQEN_PULSE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE1E_MASK) >> QEIV2_IRQEN_PULSE1E_SHIFT) 1031 1032 /* 1033 * HOME2E (RW) 1034 * 1035 */ 1036 #define QEIV2_IRQEN_HOME2E_MASK (0x80000UL) 1037 #define QEIV2_IRQEN_HOME2E_SHIFT (19U) 1038 #define QEIV2_IRQEN_HOME2E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOME2E_SHIFT) & QEIV2_IRQEN_HOME2E_MASK) 1039 #define QEIV2_IRQEN_HOME2E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOME2E_MASK) >> QEIV2_IRQEN_HOME2E_SHIFT) 1040 1041 /* 1042 * FAULTE (RW) 1043 * 1044 */ 1045 #define QEIV2_IRQEN_FAULTE_MASK (0x40000UL) 1046 #define QEIV2_IRQEN_FAULTE_SHIFT (18U) 1047 #define QEIV2_IRQEN_FAULTE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_FAULTE_SHIFT) & QEIV2_IRQEN_FAULTE_MASK) 1048 #define QEIV2_IRQEN_FAULTE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_FAULTE_MASK) >> QEIV2_IRQEN_FAULTE_SHIFT) 1049 1050 /* Bitfield definition for register of struct array COUNT: Z */ 1051 /* 1052 * ZCNT (RW) 1053 * 1054 * zcnt value 1055 */ 1056 #define QEIV2_COUNT_Z_ZCNT_MASK (0xFFFFFFFFUL) 1057 #define QEIV2_COUNT_Z_ZCNT_SHIFT (0U) 1058 #define QEIV2_COUNT_Z_ZCNT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_Z_ZCNT_SHIFT) & QEIV2_COUNT_Z_ZCNT_MASK) 1059 #define QEIV2_COUNT_Z_ZCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_Z_ZCNT_MASK) >> QEIV2_COUNT_Z_ZCNT_SHIFT) 1060 1061 /* Bitfield definition for register of struct array COUNT: PH */ 1062 /* 1063 * DIR (RO) 1064 * 1065 * 1- reverse rotation 1066 * 0- forward rotation 1067 */ 1068 #define QEIV2_COUNT_PH_DIR_MASK (0x40000000UL) 1069 #define QEIV2_COUNT_PH_DIR_SHIFT (30U) 1070 #define QEIV2_COUNT_PH_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_DIR_MASK) >> QEIV2_COUNT_PH_DIR_SHIFT) 1071 1072 /* 1073 * ASTAT (RO) 1074 * 1075 * 1- a input is high 1076 * 0- a input is low 1077 */ 1078 #define QEIV2_COUNT_PH_ASTAT_MASK (0x4000000UL) 1079 #define QEIV2_COUNT_PH_ASTAT_SHIFT (26U) 1080 #define QEIV2_COUNT_PH_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_ASTAT_MASK) >> QEIV2_COUNT_PH_ASTAT_SHIFT) 1081 1082 /* 1083 * BSTAT (RO) 1084 * 1085 * 1- b input is high 1086 * 0- b input is low 1087 */ 1088 #define QEIV2_COUNT_PH_BSTAT_MASK (0x2000000UL) 1089 #define QEIV2_COUNT_PH_BSTAT_SHIFT (25U) 1090 #define QEIV2_COUNT_PH_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_BSTAT_MASK) >> QEIV2_COUNT_PH_BSTAT_SHIFT) 1091 1092 /* 1093 * PHCNT (RO) 1094 * 1095 * phcnt value 1096 */ 1097 #define QEIV2_COUNT_PH_PHCNT_MASK (0x1FFFFFUL) 1098 #define QEIV2_COUNT_PH_PHCNT_SHIFT (0U) 1099 #define QEIV2_COUNT_PH_PHCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_PHCNT_MASK) >> QEIV2_COUNT_PH_PHCNT_SHIFT) 1100 1101 /* Bitfield definition for register of struct array COUNT: SPD */ 1102 /* 1103 * DIR (RO) 1104 * 1105 * 1- reverse rotation 1106 * 0- forward rotation 1107 */ 1108 #define QEIV2_COUNT_SPD_DIR_MASK (0x80000000UL) 1109 #define QEIV2_COUNT_SPD_DIR_SHIFT (31U) 1110 #define QEIV2_COUNT_SPD_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_DIR_MASK) >> QEIV2_COUNT_SPD_DIR_SHIFT) 1111 1112 /* 1113 * ASTAT (RO) 1114 * 1115 * 1- a input is high 1116 * 0- a input is low 1117 */ 1118 #define QEIV2_COUNT_SPD_ASTAT_MASK (0x40000000UL) 1119 #define QEIV2_COUNT_SPD_ASTAT_SHIFT (30U) 1120 #define QEIV2_COUNT_SPD_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_ASTAT_MASK) >> QEIV2_COUNT_SPD_ASTAT_SHIFT) 1121 1122 /* 1123 * BSTAT (RW) 1124 * 1125 * 1- b input is high 1126 * 0- b input is low 1127 */ 1128 #define QEIV2_COUNT_SPD_BSTAT_MASK (0x20000000UL) 1129 #define QEIV2_COUNT_SPD_BSTAT_SHIFT (29U) 1130 #define QEIV2_COUNT_SPD_BSTAT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_SPD_BSTAT_SHIFT) & QEIV2_COUNT_SPD_BSTAT_MASK) 1131 #define QEIV2_COUNT_SPD_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_BSTAT_MASK) >> QEIV2_COUNT_SPD_BSTAT_SHIFT) 1132 1133 /* 1134 * SPDCNT (RO) 1135 * 1136 * spdcnt value 1137 */ 1138 #define QEIV2_COUNT_SPD_SPDCNT_MASK (0xFFFFFFFUL) 1139 #define QEIV2_COUNT_SPD_SPDCNT_SHIFT (0U) 1140 #define QEIV2_COUNT_SPD_SPDCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_SPDCNT_MASK) >> QEIV2_COUNT_SPD_SPDCNT_SHIFT) 1141 1142 /* Bitfield definition for register of struct array COUNT: TMR */ 1143 /* 1144 * TMRCNT (RO) 1145 * 1146 * 32 bit free run timer 1147 */ 1148 #define QEIV2_COUNT_TMR_TMRCNT_MASK (0xFFFFFFFFUL) 1149 #define QEIV2_COUNT_TMR_TMRCNT_SHIFT (0U) 1150 #define QEIV2_COUNT_TMR_TMRCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_TMR_TMRCNT_MASK) >> QEIV2_COUNT_TMR_TMRCNT_SHIFT) 1151 1152 /* Bitfield definition for register: ZCMP2 */ 1153 /* 1154 * ZCMP2 (RW) 1155 * 1156 */ 1157 #define QEIV2_ZCMP2_ZCMP2_MASK (0xFFFFFFFFUL) 1158 #define QEIV2_ZCMP2_ZCMP2_SHIFT (0U) 1159 #define QEIV2_ZCMP2_ZCMP2_SET(x) (((uint32_t)(x) << QEIV2_ZCMP2_ZCMP2_SHIFT) & QEIV2_ZCMP2_ZCMP2_MASK) 1160 #define QEIV2_ZCMP2_ZCMP2_GET(x) (((uint32_t)(x) & QEIV2_ZCMP2_ZCMP2_MASK) >> QEIV2_ZCMP2_ZCMP2_SHIFT) 1161 1162 /* Bitfield definition for register: PHCMP2 */ 1163 /* 1164 * PHCMP2 (RW) 1165 * 1166 */ 1167 #define QEIV2_PHCMP2_PHCMP2_MASK (0xFFFFFFFFUL) 1168 #define QEIV2_PHCMP2_PHCMP2_SHIFT (0U) 1169 #define QEIV2_PHCMP2_PHCMP2_SET(x) (((uint32_t)(x) << QEIV2_PHCMP2_PHCMP2_SHIFT) & QEIV2_PHCMP2_PHCMP2_MASK) 1170 #define QEIV2_PHCMP2_PHCMP2_GET(x) (((uint32_t)(x) & QEIV2_PHCMP2_PHCMP2_MASK) >> QEIV2_PHCMP2_PHCMP2_SHIFT) 1171 1172 /* Bitfield definition for register: SPDCMP2 */ 1173 /* 1174 * SPDCMP2 (RW) 1175 * 1176 */ 1177 #define QEIV2_SPDCMP2_SPDCMP2_MASK (0xFFFFFFFFUL) 1178 #define QEIV2_SPDCMP2_SPDCMP2_SHIFT (0U) 1179 #define QEIV2_SPDCMP2_SPDCMP2_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP2_SPDCMP2_SHIFT) & QEIV2_SPDCMP2_SPDCMP2_MASK) 1180 #define QEIV2_SPDCMP2_SPDCMP2_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP2_SPDCMP2_MASK) >> QEIV2_SPDCMP2_SPDCMP2_SHIFT) 1181 1182 /* Bitfield definition for register: MATCH_CFG */ 1183 /* 1184 * ZCMPDIS (RW) 1185 * 1186 * 1- postion compare not include zcnt 1187 */ 1188 #define QEIV2_MATCH_CFG_ZCMPDIS_MASK (0x80000000UL) 1189 #define QEIV2_MATCH_CFG_ZCMPDIS_SHIFT (31U) 1190 #define QEIV2_MATCH_CFG_ZCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMPDIS_SHIFT) & QEIV2_MATCH_CFG_ZCMPDIS_MASK) 1191 #define QEIV2_MATCH_CFG_ZCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMPDIS_MASK) >> QEIV2_MATCH_CFG_ZCMPDIS_SHIFT) 1192 1193 /* 1194 * DIRCMPDIS (RW) 1195 * 1196 * 1- postion compare not include rotation direction 1197 */ 1198 #define QEIV2_MATCH_CFG_DIRCMPDIS_MASK (0x40000000UL) 1199 #define QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT (30U) 1200 #define QEIV2_MATCH_CFG_DIRCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK) 1201 #define QEIV2_MATCH_CFG_DIRCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK) >> QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT) 1202 1203 /* 1204 * DIRCMP (RW) 1205 * 1206 * 0- position compare need positive rotation 1207 * 1- position compare need negative rotation 1208 */ 1209 #define QEIV2_MATCH_CFG_DIRCMP_MASK (0x20000000UL) 1210 #define QEIV2_MATCH_CFG_DIRCMP_SHIFT (29U) 1211 #define QEIV2_MATCH_CFG_DIRCMP_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP_SHIFT) & QEIV2_MATCH_CFG_DIRCMP_MASK) 1212 #define QEIV2_MATCH_CFG_DIRCMP_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP_MASK) >> QEIV2_MATCH_CFG_DIRCMP_SHIFT) 1213 1214 /* 1215 * SPDCMPDIS (RW) 1216 * 1217 */ 1218 #define QEIV2_MATCH_CFG_SPDCMPDIS_MASK (0x10000000UL) 1219 #define QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT (28U) 1220 #define QEIV2_MATCH_CFG_SPDCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK) 1221 #define QEIV2_MATCH_CFG_SPDCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK) >> QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT) 1222 1223 /* 1224 * PHASE_MATCH_DIS (RW) 1225 * 1226 */ 1227 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK (0x8000000UL) 1228 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT (27U) 1229 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK) 1230 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT) 1231 1232 /* 1233 * POS_MATCH_DIR (RW) 1234 * 1235 */ 1236 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK (0x4000000UL) 1237 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT (26U) 1238 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK) 1239 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT) 1240 1241 /* 1242 * POS_MATCH_OPT (RW) 1243 * 1244 */ 1245 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK (0x2000000UL) 1246 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT (25U) 1247 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK) 1248 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT) 1249 1250 /* 1251 * ZCMP2DIS (RW) 1252 * 1253 */ 1254 #define QEIV2_MATCH_CFG_ZCMP2DIS_MASK (0x8000U) 1255 #define QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT (15U) 1256 #define QEIV2_MATCH_CFG_ZCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK) 1257 #define QEIV2_MATCH_CFG_ZCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK) >> QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT) 1258 1259 /* 1260 * DIRCMP2DIS (RW) 1261 * 1262 */ 1263 #define QEIV2_MATCH_CFG_DIRCMP2DIS_MASK (0x4000U) 1264 #define QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT (14U) 1265 #define QEIV2_MATCH_CFG_DIRCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK) 1266 #define QEIV2_MATCH_CFG_DIRCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK) >> QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT) 1267 1268 /* 1269 * DIRCMP2 (RW) 1270 * 1271 */ 1272 #define QEIV2_MATCH_CFG_DIRCMP2_MASK (0x2000U) 1273 #define QEIV2_MATCH_CFG_DIRCMP2_SHIFT (13U) 1274 #define QEIV2_MATCH_CFG_DIRCMP2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2_MASK) 1275 #define QEIV2_MATCH_CFG_DIRCMP2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2_MASK) >> QEIV2_MATCH_CFG_DIRCMP2_SHIFT) 1276 1277 /* 1278 * SPDCMP2DIS (RW) 1279 * 1280 */ 1281 #define QEIV2_MATCH_CFG_SPDCMP2DIS_MASK (0x1000U) 1282 #define QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT (12U) 1283 #define QEIV2_MATCH_CFG_SPDCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK) 1284 #define QEIV2_MATCH_CFG_SPDCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK) >> QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT) 1285 1286 /* 1287 * PHASE_MATCH_DIS2 (RW) 1288 * 1289 */ 1290 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK (0x800U) 1291 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT (11U) 1292 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK) 1293 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT) 1294 1295 /* 1296 * POS_MATCH2_DIR (RW) 1297 * 1298 */ 1299 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK (0x400U) 1300 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT (10U) 1301 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK) 1302 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT) 1303 1304 /* 1305 * POS_MATCH2_OPT (RW) 1306 * 1307 */ 1308 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK (0x200U) 1309 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT (9U) 1310 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK) 1311 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT) 1312 1313 /* Bitfield definition for register array: FILT_CFG */ 1314 /* 1315 * OUTINV (RW) 1316 * 1317 * 1- Filter will invert the output 1318 * 0- Filter will not invert the output 1319 */ 1320 #define QEIV2_FILT_CFG_OUTINV_MASK (0x10000UL) 1321 #define QEIV2_FILT_CFG_OUTINV_SHIFT (16U) 1322 #define QEIV2_FILT_CFG_OUTINV_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_OUTINV_SHIFT) & QEIV2_FILT_CFG_OUTINV_MASK) 1323 #define QEIV2_FILT_CFG_OUTINV_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_OUTINV_MASK) >> QEIV2_FILT_CFG_OUTINV_SHIFT) 1324 1325 /* 1326 * MODE (RW) 1327 * 1328 * This bitfields defines the filter mode 1329 * 000-bypass; 1330 * 100-rapid change mode; 1331 * 101-delay filter mode; 1332 * 110-stable low mode; 1333 * 111-stable high mode 1334 */ 1335 #define QEIV2_FILT_CFG_MODE_MASK (0xE000U) 1336 #define QEIV2_FILT_CFG_MODE_SHIFT (13U) 1337 #define QEIV2_FILT_CFG_MODE_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_MODE_SHIFT) & QEIV2_FILT_CFG_MODE_MASK) 1338 #define QEIV2_FILT_CFG_MODE_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_MODE_MASK) >> QEIV2_FILT_CFG_MODE_SHIFT) 1339 1340 /* 1341 * SYNCEN (RW) 1342 * 1343 * set to enable sychronization input signal with TRGM clock 1344 */ 1345 #define QEIV2_FILT_CFG_SYNCEN_MASK (0x1000U) 1346 #define QEIV2_FILT_CFG_SYNCEN_SHIFT (12U) 1347 #define QEIV2_FILT_CFG_SYNCEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_SYNCEN_SHIFT) & QEIV2_FILT_CFG_SYNCEN_MASK) 1348 #define QEIV2_FILT_CFG_SYNCEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_SYNCEN_MASK) >> QEIV2_FILT_CFG_SYNCEN_SHIFT) 1349 1350 /* 1351 * FILTLEN (RW) 1352 * 1353 * This bitfields defines the filter counter length. 1354 */ 1355 #define QEIV2_FILT_CFG_FILTLEN_MASK (0xFFFU) 1356 #define QEIV2_FILT_CFG_FILTLEN_SHIFT (0U) 1357 #define QEIV2_FILT_CFG_FILTLEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_FILTLEN_SHIFT) & QEIV2_FILT_CFG_FILTLEN_MASK) 1358 #define QEIV2_FILT_CFG_FILTLEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_FILTLEN_MASK) >> QEIV2_FILT_CFG_FILTLEN_SHIFT) 1359 1360 /* Bitfield definition for register: QEI_CFG */ 1361 /* 1362 * SW_PULSE0_RESTART (RW) 1363 * 1364 * set to restart cycle counter for configed pulse_num. HW auto clear 1365 */ 1366 #define QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK (0x80000000UL) 1367 #define QEIV2_QEI_CFG_SW_PULSE0_RESTART_SHIFT (31U) 1368 #define QEIV2_QEI_CFG_SW_PULSE0_RESTART_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SW_PULSE0_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK) 1369 #define QEIV2_QEI_CFG_SW_PULSE0_RESTART_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK) >> QEIV2_QEI_CFG_SW_PULSE0_RESTART_SHIFT) 1370 1371 /* 1372 * SW_PULSE1_RESTART (RW) 1373 * 1374 */ 1375 #define QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK (0x40000000UL) 1376 #define QEIV2_QEI_CFG_SW_PULSE1_RESTART_SHIFT (30U) 1377 #define QEIV2_QEI_CFG_SW_PULSE1_RESTART_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SW_PULSE1_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK) 1378 #define QEIV2_QEI_CFG_SW_PULSE1_RESTART_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK) >> QEIV2_QEI_CFG_SW_PULSE1_RESTART_SHIFT) 1379 1380 /* 1381 * SW_CYCLE0_RESTART (RW) 1382 * 1383 * set to restart pulse counter for configed cycle_num. HW auto clear 1384 */ 1385 #define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK (0x20000000UL) 1386 #define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SHIFT (29U) 1387 #define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK) 1388 #define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK) >> QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SHIFT) 1389 1390 /* 1391 * SW_CYCLE1_RESTART (RW) 1392 * 1393 */ 1394 #define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK (0x10000000UL) 1395 #define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SHIFT (28U) 1396 #define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK) 1397 #define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK) >> QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SHIFT) 1398 1399 /* 1400 * PULSE0_ONESHOT (RW) 1401 * 1402 * set to use oneshot mode for configed pulse_num 1403 */ 1404 #define QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK (0x80000UL) 1405 #define QEIV2_QEI_CFG_PULSE0_ONESHOT_SHIFT (19U) 1406 #define QEIV2_QEI_CFG_PULSE0_ONESHOT_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_PULSE0_ONESHOT_SHIFT) & QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK) 1407 #define QEIV2_QEI_CFG_PULSE0_ONESHOT_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK) >> QEIV2_QEI_CFG_PULSE0_ONESHOT_SHIFT) 1408 1409 /* 1410 * PULSE1_ONESHOT (RW) 1411 * 1412 */ 1413 #define QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK (0x40000UL) 1414 #define QEIV2_QEI_CFG_PULSE1_ONESHOT_SHIFT (18U) 1415 #define QEIV2_QEI_CFG_PULSE1_ONESHOT_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_PULSE1_ONESHOT_SHIFT) & QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK) 1416 #define QEIV2_QEI_CFG_PULSE1_ONESHOT_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK) >> QEIV2_QEI_CFG_PULSE1_ONESHOT_SHIFT) 1417 1418 /* 1419 * CYCLE0_ONESHOT (RW) 1420 * 1421 * set to use oneshot mode for configed cycle_num 1422 */ 1423 #define QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK (0x20000UL) 1424 #define QEIV2_QEI_CFG_CYCLE0_ONESHOT_SHIFT (17U) 1425 #define QEIV2_QEI_CFG_CYCLE0_ONESHOT_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_CYCLE0_ONESHOT_SHIFT) & QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK) 1426 #define QEIV2_QEI_CFG_CYCLE0_ONESHOT_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK) >> QEIV2_QEI_CFG_CYCLE0_ONESHOT_SHIFT) 1427 1428 /* 1429 * CYCLE1_ONESHOT (RW) 1430 * 1431 */ 1432 #define QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK (0x10000UL) 1433 #define QEIV2_QEI_CFG_CYCLE1_ONESHOT_SHIFT (16U) 1434 #define QEIV2_QEI_CFG_CYCLE1_ONESHOT_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_CYCLE1_ONESHOT_SHIFT) & QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK) 1435 #define QEIV2_QEI_CFG_CYCLE1_ONESHOT_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK) >> QEIV2_QEI_CFG_CYCLE1_ONESHOT_SHIFT) 1436 1437 /* 1438 * SPEED_DIR_CHG_EN (RW) 1439 * 1440 * clear counter if detect direction change 1441 */ 1442 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK (0x1000U) 1443 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT (12U) 1444 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK) 1445 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK) >> QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT) 1446 1447 /* 1448 * TRIG_PULSE0_EN (RW) 1449 * 1450 * set to enable trigger start cycle counter for configed pulse_num(from the selected edge) 1451 */ 1452 #define QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK (0x800U) 1453 #define QEIV2_QEI_CFG_TRIG_PULSE0_EN_SHIFT (11U) 1454 #define QEIV2_QEI_CFG_TRIG_PULSE0_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_PULSE0_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK) 1455 #define QEIV2_QEI_CFG_TRIG_PULSE0_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK) >> QEIV2_QEI_CFG_TRIG_PULSE0_EN_SHIFT) 1456 1457 /* 1458 * TRIG_PULSE1_EN (RW) 1459 * 1460 */ 1461 #define QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK (0x400U) 1462 #define QEIV2_QEI_CFG_TRIG_PULSE1_EN_SHIFT (10U) 1463 #define QEIV2_QEI_CFG_TRIG_PULSE1_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_PULSE1_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK) 1464 #define QEIV2_QEI_CFG_TRIG_PULSE1_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK) >> QEIV2_QEI_CFG_TRIG_PULSE1_EN_SHIFT) 1465 1466 /* 1467 * TRIG_CYCLE0_EN (RW) 1468 * 1469 * set to enable trigger start pulse counter for configed cycle_num 1470 */ 1471 #define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK (0x200U) 1472 #define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SHIFT (9U) 1473 #define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK) 1474 #define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK) >> QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SHIFT) 1475 1476 /* 1477 * TRIG_CYCLE1_EN (RW) 1478 * 1479 */ 1480 #define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK (0x100U) 1481 #define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SHIFT (8U) 1482 #define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK) 1483 #define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK) >> QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SHIFT) 1484 1485 /* 1486 * UVW_POS_OPT0 (RW) 1487 * 1488 * set to output next area position for QEO use; 1489 * clr to output exact point position for MMC use 1490 */ 1491 #define QEIV2_QEI_CFG_UVW_POS_OPT0_MASK (0x20U) 1492 #define QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT (5U) 1493 #define QEIV2_QEI_CFG_UVW_POS_OPT0_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) 1494 #define QEIV2_QEI_CFG_UVW_POS_OPT0_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) >> QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT) 1495 1496 /* 1497 * NEGEDGE_EN (RW) 1498 * 1499 * bit4: negedge enable 1500 * bit3: posedge enable 1501 * bit2: W in hal enable 1502 * bit1: signal b(or V in hal) enable 1503 * bit0: signal a(or U in hal) enable 1504 * such as: 1505 * 01001: use posedge A 1506 * 11010: use both edge of signal B 1507 * 11111: use both edge of all HAL siganls 1508 */ 1509 #define QEIV2_QEI_CFG_NEGEDGE_EN_MASK (0x10U) 1510 #define QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT (4U) 1511 #define QEIV2_QEI_CFG_NEGEDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK) 1512 #define QEIV2_QEI_CFG_NEGEDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK) >> QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT) 1513 1514 /* 1515 * POSIDGE_EN (RW) 1516 * 1517 */ 1518 #define QEIV2_QEI_CFG_POSIDGE_EN_MASK (0x8U) 1519 #define QEIV2_QEI_CFG_POSIDGE_EN_SHIFT (3U) 1520 #define QEIV2_QEI_CFG_POSIDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_POSIDGE_EN_SHIFT) & QEIV2_QEI_CFG_POSIDGE_EN_MASK) 1521 #define QEIV2_QEI_CFG_POSIDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_POSIDGE_EN_MASK) >> QEIV2_QEI_CFG_POSIDGE_EN_SHIFT) 1522 1523 /* 1524 * SIGZ_EN (RW) 1525 * 1526 */ 1527 #define QEIV2_QEI_CFG_SIGZ_EN_MASK (0x4U) 1528 #define QEIV2_QEI_CFG_SIGZ_EN_SHIFT (2U) 1529 #define QEIV2_QEI_CFG_SIGZ_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGZ_EN_SHIFT) & QEIV2_QEI_CFG_SIGZ_EN_MASK) 1530 #define QEIV2_QEI_CFG_SIGZ_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGZ_EN_MASK) >> QEIV2_QEI_CFG_SIGZ_EN_SHIFT) 1531 1532 /* 1533 * SIGB_EN (RW) 1534 * 1535 */ 1536 #define QEIV2_QEI_CFG_SIGB_EN_MASK (0x2U) 1537 #define QEIV2_QEI_CFG_SIGB_EN_SHIFT (1U) 1538 #define QEIV2_QEI_CFG_SIGB_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGB_EN_SHIFT) & QEIV2_QEI_CFG_SIGB_EN_MASK) 1539 #define QEIV2_QEI_CFG_SIGB_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGB_EN_MASK) >> QEIV2_QEI_CFG_SIGB_EN_SHIFT) 1540 1541 /* 1542 * SIGA_EN (RW) 1543 * 1544 */ 1545 #define QEIV2_QEI_CFG_SIGA_EN_MASK (0x1U) 1546 #define QEIV2_QEI_CFG_SIGA_EN_SHIFT (0U) 1547 #define QEIV2_QEI_CFG_SIGA_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGA_EN_SHIFT) & QEIV2_QEI_CFG_SIGA_EN_MASK) 1548 #define QEIV2_QEI_CFG_SIGA_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGA_EN_MASK) >> QEIV2_QEI_CFG_SIGA_EN_SHIFT) 1549 1550 /* Bitfield definition for register: PULSE0_NUM */ 1551 /* 1552 * PULSE0_NUM (RW) 1553 * 1554 * for speed detection, will count the cycle number for configed pulse_num 1555 */ 1556 #define QEIV2_PULSE0_NUM_PULSE0_NUM_MASK (0xFFFFFFFFUL) 1557 #define QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT (0U) 1558 #define QEIV2_PULSE0_NUM_PULSE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK) 1559 #define QEIV2_PULSE0_NUM_PULSE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK) >> QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT) 1560 1561 /* Bitfield definition for register: PULSE1_NUM */ 1562 /* 1563 * PULSE1_NUM (RW) 1564 * 1565 */ 1566 #define QEIV2_PULSE1_NUM_PULSE1_NUM_MASK (0xFFFFFFFFUL) 1567 #define QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT (0U) 1568 #define QEIV2_PULSE1_NUM_PULSE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK) 1569 #define QEIV2_PULSE1_NUM_PULSE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK) >> QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT) 1570 1571 /* Bitfield definition for register: CYCLE0_CNT */ 1572 /* 1573 * CYCLE0_CNT (RO) 1574 * 1575 */ 1576 #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK (0xFFFFFFFFUL) 1577 #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT (0U) 1578 #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK) >> QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT) 1579 1580 /* Bitfield definition for register: CYCLE0PULSE_CNT */ 1581 /* 1582 * CYCLE0PULSE_CNT (RO) 1583 * 1584 */ 1585 #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK (0xFFFFFFFFUL) 1586 #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT (0U) 1587 #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK) >> QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT) 1588 1589 /* Bitfield definition for register: CYCLE1_CNT */ 1590 /* 1591 * CYCLE1_CNT (RO) 1592 * 1593 */ 1594 #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK (0xFFFFFFFFUL) 1595 #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT (0U) 1596 #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK) >> QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT) 1597 1598 /* Bitfield definition for register: CYCLE1PULSE_CNT */ 1599 /* 1600 * CYCLE1PULSE_CNT (RO) 1601 * 1602 */ 1603 #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK (0xFFFFFFFFUL) 1604 #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT (0U) 1605 #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK) >> QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT) 1606 1607 /* Bitfield definition for register: CYCLE0_SNAP0 */ 1608 /* 1609 * CYCLE0_SNAP0 (RO) 1610 * 1611 */ 1612 #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK (0xFFFFFFFFUL) 1613 #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT (0U) 1614 #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK) >> QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT) 1615 1616 /* Bitfield definition for register: CYCLE0_SNAP1 */ 1617 /* 1618 * CYCLE0_SNAP1 (RO) 1619 * 1620 */ 1621 #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK (0xFFFFFFFFUL) 1622 #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT (0U) 1623 #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK) >> QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT) 1624 1625 /* Bitfield definition for register: CYCLE1_SNAP0 */ 1626 /* 1627 * CYCLE1_SNAP0 (RO) 1628 * 1629 */ 1630 #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK (0xFFFFFFFFUL) 1631 #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT (0U) 1632 #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK) >> QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT) 1633 1634 /* Bitfield definition for register: CYCLE1_SNAP1 */ 1635 /* 1636 * CYCLE1_SNAP1 (RO) 1637 * 1638 */ 1639 #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK (0xFFFFFFFFUL) 1640 #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT (0U) 1641 #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK) >> QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT) 1642 1643 /* Bitfield definition for register: CYCLE0_NUM */ 1644 /* 1645 * CYCLE0_NUM (RW) 1646 * 1647 */ 1648 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK (0xFFFFFFFFUL) 1649 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT (0U) 1650 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK) 1651 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK) >> QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT) 1652 1653 /* Bitfield definition for register: CYCLE1_NUM */ 1654 /* 1655 * CYCLE1_NUM (RW) 1656 * 1657 */ 1658 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK (0xFFFFFFFFUL) 1659 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT (0U) 1660 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK) 1661 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK) >> QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT) 1662 1663 /* Bitfield definition for register: PULSE0_CNT */ 1664 /* 1665 * PULSE0_CNT (RO) 1666 * 1667 */ 1668 #define QEIV2_PULSE0_CNT_PULSE0_CNT_MASK (0xFFFFFFFFUL) 1669 #define QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT (0U) 1670 #define QEIV2_PULSE0_CNT_PULSE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_CNT_PULSE0_CNT_MASK) >> QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT) 1671 1672 /* Bitfield definition for register: PULSE0CYCLE_CNT */ 1673 /* 1674 * PULSE0CYCLE_CNT (RO) 1675 * 1676 */ 1677 #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK (0xFFFFFFFFUL) 1678 #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT (0U) 1679 #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK) >> QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT) 1680 1681 /* Bitfield definition for register: PULSE1_CNT */ 1682 /* 1683 * PULSE1_CNT (RO) 1684 * 1685 */ 1686 #define QEIV2_PULSE1_CNT_PULSE1_CNT_MASK (0xFFFFFFFFUL) 1687 #define QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT (0U) 1688 #define QEIV2_PULSE1_CNT_PULSE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_CNT_PULSE1_CNT_MASK) >> QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT) 1689 1690 /* Bitfield definition for register: PULSE1CYCLE_CNT */ 1691 /* 1692 * PULSE1CYCLE_CNT (RO) 1693 * 1694 */ 1695 #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK (0xFFFFFFFFUL) 1696 #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT (0U) 1697 #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK) >> QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT) 1698 1699 /* Bitfield definition for register: PULSE0_SNAP0 */ 1700 /* 1701 * PULSE0_SNAP0 (RO) 1702 * 1703 */ 1704 #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK (0xFFFFFFFFUL) 1705 #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT (0U) 1706 #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK) >> QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT) 1707 1708 /* Bitfield definition for register: PULSE0CYCLE_SNAP0 */ 1709 /* 1710 * PULSE0CYCLE_SNAP0 (RO) 1711 * 1712 */ 1713 #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK (0xFFFFFFFFUL) 1714 #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT (0U) 1715 #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK) >> QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT) 1716 1717 /* Bitfield definition for register: PULSE0_SNAP1 */ 1718 /* 1719 * PULSE0_SNAP1 (RO) 1720 * 1721 */ 1722 #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK (0xFFFFFFFFUL) 1723 #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT (0U) 1724 #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK) >> QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT) 1725 1726 /* Bitfield definition for register: PULSE0CYCLE_SNAP1 */ 1727 /* 1728 * PULSE0CYCLE_SNAP1 (RO) 1729 * 1730 */ 1731 #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK (0xFFFFFFFFUL) 1732 #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT (0U) 1733 #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK) >> QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT) 1734 1735 /* Bitfield definition for register: PULSE1_SNAP0 */ 1736 /* 1737 * PULSE1_SNAP0 (RO) 1738 * 1739 */ 1740 #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK (0xFFFFFFFFUL) 1741 #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT (0U) 1742 #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK) >> QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT) 1743 1744 /* Bitfield definition for register: PULSE1CYCLE_SNAP0 */ 1745 /* 1746 * PULSE1CYCLE_SNAP0 (RO) 1747 * 1748 */ 1749 #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK (0xFFFFFFFFUL) 1750 #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT (0U) 1751 #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK) >> QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT) 1752 1753 /* Bitfield definition for register: PULSE1_SNAP1 */ 1754 /* 1755 * PULSE1_SNAP1 (RO) 1756 * 1757 */ 1758 #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK (0xFFFFFFFFUL) 1759 #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT (0U) 1760 #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK) >> QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT) 1761 1762 /* Bitfield definition for register: PULSE1CYCLE_SNAP1 */ 1763 /* 1764 * PULSE1CYCLE_SNAP1 (RO) 1765 * 1766 */ 1767 #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK (0xFFFFFFFFUL) 1768 #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT (0U) 1769 #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK) >> QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT) 1770 1771 /* Bitfield definition for register: TIMESTAMP */ 1772 /* 1773 * TIMESTAMP (RO) 1774 * 1775 * for SIN/COS mode, it saves the timestampe of the begining of first ADC sample time; 1776 * for ABZ mode, it saves the timestampe of edge of input signals 1777 */ 1778 #define QEIV2_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFFFUL) 1779 #define QEIV2_TIMESTAMP_TIMESTAMP_SHIFT (0U) 1780 #define QEIV2_TIMESTAMP_TIMESTAMP_GET(x) (((uint32_t)(x) & QEIV2_TIMESTAMP_TIMESTAMP_MASK) >> QEIV2_TIMESTAMP_TIMESTAMP_SHIFT) 1781 1782 /* Bitfield definition for register: ADC_THRESHOLD */ 1783 /* 1784 * LOW_LIMIT (RW) 1785 * 1786 * for SINCOS mode, if (max+min/2) of the two adc result, is small than limit, 1787 * then this value is treated as unvalid, no position output. 1788 * this is uesd to avoid wrong adc resule(such as 0 or same sin cos value) 1789 */ 1790 #define QEIV2_ADC_THRESHOLD_LOW_LIMIT_MASK (0xFFFF0000UL) 1791 #define QEIV2_ADC_THRESHOLD_LOW_LIMIT_SHIFT (16U) 1792 #define QEIV2_ADC_THRESHOLD_LOW_LIMIT_SET(x) (((uint32_t)(x) << QEIV2_ADC_THRESHOLD_LOW_LIMIT_SHIFT) & QEIV2_ADC_THRESHOLD_LOW_LIMIT_MASK) 1793 #define QEIV2_ADC_THRESHOLD_LOW_LIMIT_GET(x) (((uint32_t)(x) & QEIV2_ADC_THRESHOLD_LOW_LIMIT_MASK) >> QEIV2_ADC_THRESHOLD_LOW_LIMIT_SHIFT) 1794 1795 /* 1796 * HIGH_LIMIT (RW) 1797 * 1798 * high limit for SINCOS mode adc result 1799 */ 1800 #define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_MASK (0xFFFFU) 1801 #define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SHIFT (0U) 1802 #define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SET(x) (((uint32_t)(x) << QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SHIFT) & QEIV2_ADC_THRESHOLD_HIGH_LIMIT_MASK) 1803 #define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_GET(x) (((uint32_t)(x) & QEIV2_ADC_THRESHOLD_HIGH_LIMIT_MASK) >> QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SHIFT) 1804 1805 /* Bitfield definition for register: ADCX_CFG0 */ 1806 /* 1807 * X_ADCSEL (RW) 1808 * 1809 */ 1810 #define QEIV2_ADCX_CFG0_X_ADCSEL_MASK (0x100U) 1811 #define QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT (8U) 1812 #define QEIV2_ADCX_CFG0_X_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK) 1813 #define QEIV2_ADCX_CFG0_X_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK) >> QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT) 1814 1815 /* 1816 * X_ADC_ENABLE (RW) 1817 * 1818 */ 1819 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK (0x80U) 1820 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT (7U) 1821 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK) 1822 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK) >> QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT) 1823 1824 /* 1825 * X_CHAN (RW) 1826 * 1827 */ 1828 #define QEIV2_ADCX_CFG0_X_CHAN_MASK (0x1FU) 1829 #define QEIV2_ADCX_CFG0_X_CHAN_SHIFT (0U) 1830 #define QEIV2_ADCX_CFG0_X_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_CHAN_SHIFT) & QEIV2_ADCX_CFG0_X_CHAN_MASK) 1831 #define QEIV2_ADCX_CFG0_X_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_CHAN_MASK) >> QEIV2_ADCX_CFG0_X_CHAN_SHIFT) 1832 1833 /* Bitfield definition for register: ADCX_CFG1 */ 1834 /* 1835 * X_PARAM1 (RW) 1836 * 1837 */ 1838 #define QEIV2_ADCX_CFG1_X_PARAM1_MASK (0xFFFF0000UL) 1839 #define QEIV2_ADCX_CFG1_X_PARAM1_SHIFT (16U) 1840 #define QEIV2_ADCX_CFG1_X_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM1_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM1_MASK) 1841 #define QEIV2_ADCX_CFG1_X_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM1_MASK) >> QEIV2_ADCX_CFG1_X_PARAM1_SHIFT) 1842 1843 /* 1844 * X_PARAM0 (RW) 1845 * 1846 */ 1847 #define QEIV2_ADCX_CFG1_X_PARAM0_MASK (0xFFFFU) 1848 #define QEIV2_ADCX_CFG1_X_PARAM0_SHIFT (0U) 1849 #define QEIV2_ADCX_CFG1_X_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM0_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM0_MASK) 1850 #define QEIV2_ADCX_CFG1_X_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM0_MASK) >> QEIV2_ADCX_CFG1_X_PARAM0_SHIFT) 1851 1852 /* Bitfield definition for register: ADCX_CFG2 */ 1853 /* 1854 * X_OFFSET (RW) 1855 * 1856 */ 1857 #define QEIV2_ADCX_CFG2_X_OFFSET_MASK (0xFFFFFFFFUL) 1858 #define QEIV2_ADCX_CFG2_X_OFFSET_SHIFT (0U) 1859 #define QEIV2_ADCX_CFG2_X_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG2_X_OFFSET_SHIFT) & QEIV2_ADCX_CFG2_X_OFFSET_MASK) 1860 #define QEIV2_ADCX_CFG2_X_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG2_X_OFFSET_MASK) >> QEIV2_ADCX_CFG2_X_OFFSET_SHIFT) 1861 1862 /* Bitfield definition for register: ADCY_CFG0 */ 1863 /* 1864 * Y_ADCSEL (RW) 1865 * 1866 */ 1867 #define QEIV2_ADCY_CFG0_Y_ADCSEL_MASK (0x100U) 1868 #define QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT (8U) 1869 #define QEIV2_ADCY_CFG0_Y_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK) 1870 #define QEIV2_ADCY_CFG0_Y_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK) >> QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT) 1871 1872 /* 1873 * Y_ADC_ENABLE (RW) 1874 * 1875 */ 1876 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK (0x80U) 1877 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT (7U) 1878 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK) 1879 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK) >> QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT) 1880 1881 /* 1882 * Y_CHAN (RW) 1883 * 1884 */ 1885 #define QEIV2_ADCY_CFG0_Y_CHAN_MASK (0x1FU) 1886 #define QEIV2_ADCY_CFG0_Y_CHAN_SHIFT (0U) 1887 #define QEIV2_ADCY_CFG0_Y_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_CHAN_SHIFT) & QEIV2_ADCY_CFG0_Y_CHAN_MASK) 1888 #define QEIV2_ADCY_CFG0_Y_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_CHAN_MASK) >> QEIV2_ADCY_CFG0_Y_CHAN_SHIFT) 1889 1890 /* Bitfield definition for register: ADCY_CFG1 */ 1891 /* 1892 * Y_PARAM1 (RW) 1893 * 1894 */ 1895 #define QEIV2_ADCY_CFG1_Y_PARAM1_MASK (0xFFFF0000UL) 1896 #define QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT (16U) 1897 #define QEIV2_ADCY_CFG1_Y_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK) 1898 #define QEIV2_ADCY_CFG1_Y_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT) 1899 1900 /* 1901 * Y_PARAM0 (RW) 1902 * 1903 */ 1904 #define QEIV2_ADCY_CFG1_Y_PARAM0_MASK (0xFFFFU) 1905 #define QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT (0U) 1906 #define QEIV2_ADCY_CFG1_Y_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK) 1907 #define QEIV2_ADCY_CFG1_Y_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT) 1908 1909 /* Bitfield definition for register: ADCY_CFG2 */ 1910 /* 1911 * Y_OFFSET (RW) 1912 * 1913 */ 1914 #define QEIV2_ADCY_CFG2_Y_OFFSET_MASK (0xFFFFFFFFUL) 1915 #define QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT (0U) 1916 #define QEIV2_ADCY_CFG2_Y_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK) 1917 #define QEIV2_ADCY_CFG2_Y_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK) >> QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT) 1918 1919 /* Bitfield definition for register: CAL_CFG */ 1920 /* 1921 * XY_DELAY (RW) 1922 * 1923 * valid x/y delay, larger than this delay will be treated as invalid data. 1924 * Default 1.25us@200MHz; max 80ms; 1925 */ 1926 #define QEIV2_CAL_CFG_XY_DELAY_MASK (0xFFFFFFUL) 1927 #define QEIV2_CAL_CFG_XY_DELAY_SHIFT (0U) 1928 #define QEIV2_CAL_CFG_XY_DELAY_SET(x) (((uint32_t)(x) << QEIV2_CAL_CFG_XY_DELAY_SHIFT) & QEIV2_CAL_CFG_XY_DELAY_MASK) 1929 #define QEIV2_CAL_CFG_XY_DELAY_GET(x) (((uint32_t)(x) & QEIV2_CAL_CFG_XY_DELAY_MASK) >> QEIV2_CAL_CFG_XY_DELAY_SHIFT) 1930 1931 /* Bitfield definition for register: PHASE_PARAM */ 1932 /* 1933 * PHASE_PARAM (RW) 1934 * 1935 */ 1936 #define QEIV2_PHASE_PARAM_PHASE_PARAM_MASK (0xFFFFFFFFUL) 1937 #define QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT (0U) 1938 #define QEIV2_PHASE_PARAM_PHASE_PARAM_SET(x) (((uint32_t)(x) << QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK) 1939 #define QEIV2_PHASE_PARAM_PHASE_PARAM_GET(x) (((uint32_t)(x) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK) >> QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT) 1940 1941 /* Bitfield definition for register: POS_THRESHOLD */ 1942 /* 1943 * POS_THRESHOLD (RW) 1944 * 1945 */ 1946 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK (0xFFFFFFFFUL) 1947 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT (0U) 1948 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SET(x) (((uint32_t)(x) << QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK) 1949 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_GET(x) (((uint32_t)(x) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK) >> QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT) 1950 1951 /* Bitfield definition for register array: UVW_POS */ 1952 /* 1953 * UVW_POS0 (RW) 1954 * 1955 */ 1956 #define QEIV2_UVW_POS_UVW_POS0_MASK (0xFFFFFFFFUL) 1957 #define QEIV2_UVW_POS_UVW_POS0_SHIFT (0U) 1958 #define QEIV2_UVW_POS_UVW_POS0_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_UVW_POS0_SHIFT) & QEIV2_UVW_POS_UVW_POS0_MASK) 1959 #define QEIV2_UVW_POS_UVW_POS0_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_UVW_POS0_MASK) >> QEIV2_UVW_POS_UVW_POS0_SHIFT) 1960 1961 /* Bitfield definition for register array: UVW_POS_CFG */ 1962 /* 1963 * POS_EN (RW) 1964 * 1965 */ 1966 #define QEIV2_UVW_POS_CFG_POS_EN_MASK (0x40U) 1967 #define QEIV2_UVW_POS_CFG_POS_EN_SHIFT (6U) 1968 #define QEIV2_UVW_POS_CFG_POS_EN_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_POS_EN_SHIFT) & QEIV2_UVW_POS_CFG_POS_EN_MASK) 1969 #define QEIV2_UVW_POS_CFG_POS_EN_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_POS_EN_MASK) >> QEIV2_UVW_POS_CFG_POS_EN_SHIFT) 1970 1971 /* 1972 * U_POS_SEL (RW) 1973 * 1974 */ 1975 #define QEIV2_UVW_POS_CFG_U_POS_SEL_MASK (0x30U) 1976 #define QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT (4U) 1977 #define QEIV2_UVW_POS_CFG_U_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK) 1978 #define QEIV2_UVW_POS_CFG_U_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT) 1979 1980 /* 1981 * V_POS_SEL (RW) 1982 * 1983 */ 1984 #define QEIV2_UVW_POS_CFG_V_POS_SEL_MASK (0xCU) 1985 #define QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT (2U) 1986 #define QEIV2_UVW_POS_CFG_V_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK) 1987 #define QEIV2_UVW_POS_CFG_V_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT) 1988 1989 /* 1990 * W_POS_SEL (RW) 1991 * 1992 */ 1993 #define QEIV2_UVW_POS_CFG_W_POS_SEL_MASK (0x3U) 1994 #define QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT (0U) 1995 #define QEIV2_UVW_POS_CFG_W_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK) 1996 #define QEIV2_UVW_POS_CFG_W_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT) 1997 1998 /* Bitfield definition for register: PHASE_CNT */ 1999 /* 2000 * PHASE_CNT (RW) 2001 * 2002 */ 2003 #define QEIV2_PHASE_CNT_PHASE_CNT_MASK (0xFFFFFFFFUL) 2004 #define QEIV2_PHASE_CNT_PHASE_CNT_SHIFT (0U) 2005 #define QEIV2_PHASE_CNT_PHASE_CNT_SET(x) (((uint32_t)(x) << QEIV2_PHASE_CNT_PHASE_CNT_SHIFT) & QEIV2_PHASE_CNT_PHASE_CNT_MASK) 2006 #define QEIV2_PHASE_CNT_PHASE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PHASE_CNT_PHASE_CNT_MASK) >> QEIV2_PHASE_CNT_PHASE_CNT_SHIFT) 2007 2008 /* Bitfield definition for register: PHASE_UPDATE */ 2009 /* 2010 * INC (WO) 2011 * 2012 * set to add value to phase_cnt 2013 */ 2014 #define QEIV2_PHASE_UPDATE_INC_MASK (0x80000000UL) 2015 #define QEIV2_PHASE_UPDATE_INC_SHIFT (31U) 2016 #define QEIV2_PHASE_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_INC_SHIFT) & QEIV2_PHASE_UPDATE_INC_MASK) 2017 #define QEIV2_PHASE_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_INC_MASK) >> QEIV2_PHASE_UPDATE_INC_SHIFT) 2018 2019 /* 2020 * DEC (WO) 2021 * 2022 * set to minus value from phase_cnt(set inc and dec same time willl act inc) 2023 */ 2024 #define QEIV2_PHASE_UPDATE_DEC_MASK (0x40000000UL) 2025 #define QEIV2_PHASE_UPDATE_DEC_SHIFT (30U) 2026 #define QEIV2_PHASE_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_DEC_SHIFT) & QEIV2_PHASE_UPDATE_DEC_MASK) 2027 #define QEIV2_PHASE_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_DEC_MASK) >> QEIV2_PHASE_UPDATE_DEC_SHIFT) 2028 2029 /* 2030 * VALUE (WO) 2031 * 2032 * value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation 2033 */ 2034 #define QEIV2_PHASE_UPDATE_VALUE_MASK (0x3FFFFFFFUL) 2035 #define QEIV2_PHASE_UPDATE_VALUE_SHIFT (0U) 2036 #define QEIV2_PHASE_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_VALUE_SHIFT) & QEIV2_PHASE_UPDATE_VALUE_MASK) 2037 #define QEIV2_PHASE_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_VALUE_MASK) >> QEIV2_PHASE_UPDATE_VALUE_SHIFT) 2038 2039 /* Bitfield definition for register: POSITION */ 2040 /* 2041 * POSITION (RW) 2042 * 2043 */ 2044 #define QEIV2_POSITION_POSITION_MASK (0xFFFFFFFFUL) 2045 #define QEIV2_POSITION_POSITION_SHIFT (0U) 2046 #define QEIV2_POSITION_POSITION_SET(x) (((uint32_t)(x) << QEIV2_POSITION_POSITION_SHIFT) & QEIV2_POSITION_POSITION_MASK) 2047 #define QEIV2_POSITION_POSITION_GET(x) (((uint32_t)(x) & QEIV2_POSITION_POSITION_MASK) >> QEIV2_POSITION_POSITION_SHIFT) 2048 2049 /* Bitfield definition for register: POSITION_UPDATE */ 2050 /* 2051 * INC (WO) 2052 * 2053 * set to add value to position 2054 */ 2055 #define QEIV2_POSITION_UPDATE_INC_MASK (0x80000000UL) 2056 #define QEIV2_POSITION_UPDATE_INC_SHIFT (31U) 2057 #define QEIV2_POSITION_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_INC_SHIFT) & QEIV2_POSITION_UPDATE_INC_MASK) 2058 #define QEIV2_POSITION_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_INC_MASK) >> QEIV2_POSITION_UPDATE_INC_SHIFT) 2059 2060 /* 2061 * DEC (WO) 2062 * 2063 * set to minus value from position(set inc and dec same time willl act inc) 2064 */ 2065 #define QEIV2_POSITION_UPDATE_DEC_MASK (0x40000000UL) 2066 #define QEIV2_POSITION_UPDATE_DEC_SHIFT (30U) 2067 #define QEIV2_POSITION_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_DEC_SHIFT) & QEIV2_POSITION_UPDATE_DEC_MASK) 2068 #define QEIV2_POSITION_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_DEC_MASK) >> QEIV2_POSITION_UPDATE_DEC_SHIFT) 2069 2070 /* 2071 * VALUE (WO) 2072 * 2073 * value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation 2074 */ 2075 #define QEIV2_POSITION_UPDATE_VALUE_MASK (0x3FFFFFFFUL) 2076 #define QEIV2_POSITION_UPDATE_VALUE_SHIFT (0U) 2077 #define QEIV2_POSITION_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_VALUE_SHIFT) & QEIV2_POSITION_UPDATE_VALUE_MASK) 2078 #define QEIV2_POSITION_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_VALUE_MASK) >> QEIV2_POSITION_UPDATE_VALUE_SHIFT) 2079 2080 /* Bitfield definition for register: ANGLE */ 2081 /* 2082 * ANGLE (RO) 2083 * 2084 */ 2085 #define QEIV2_ANGLE_ANGLE_MASK (0xFFFFFFFFUL) 2086 #define QEIV2_ANGLE_ANGLE_SHIFT (0U) 2087 #define QEIV2_ANGLE_ANGLE_GET(x) (((uint32_t)(x) & QEIV2_ANGLE_ANGLE_MASK) >> QEIV2_ANGLE_ANGLE_SHIFT) 2088 2089 /* Bitfield definition for register: POS_TIMEOUT */ 2090 /* 2091 * ENABLE (RW) 2092 * 2093 * enable position timeout feature, if timeout, send valid again 2094 */ 2095 #define QEIV2_POS_TIMEOUT_ENABLE_MASK (0x80000000UL) 2096 #define QEIV2_POS_TIMEOUT_ENABLE_SHIFT (31U) 2097 #define QEIV2_POS_TIMEOUT_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_ENABLE_SHIFT) & QEIV2_POS_TIMEOUT_ENABLE_MASK) 2098 #define QEIV2_POS_TIMEOUT_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_ENABLE_MASK) >> QEIV2_POS_TIMEOUT_ENABLE_SHIFT) 2099 2100 /* 2101 * TIMEOUT (RW) 2102 * 2103 * postion timeout value 2104 */ 2105 #define QEIV2_POS_TIMEOUT_TIMEOUT_MASK (0x7FFFFFFFUL) 2106 #define QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT (0U) 2107 #define QEIV2_POS_TIMEOUT_TIMEOUT_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK) 2108 #define QEIV2_POS_TIMEOUT_TIMEOUT_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK) >> QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT) 2109 2110 2111 2112 /* COUNT register group index macro definition */ 2113 #define QEIV2_COUNT_CURRENT (0UL) 2114 #define QEIV2_COUNT_READ (1UL) 2115 #define QEIV2_COUNT_SNAP0 (2UL) 2116 #define QEIV2_COUNT_SNAP1 (3UL) 2117 2118 /* FILT_CFG register group index macro definition */ 2119 #define QEIV2_FILT_CFG_FILT_CFG_A (0UL) 2120 #define QEIV2_FILT_CFG_FILT_CFG_B (1UL) 2121 #define QEIV2_FILT_CFG_FILT_CFG_Z (2UL) 2122 #define QEIV2_FILT_CFG_FILT_CFG_H (3UL) 2123 #define QEIV2_FILT_CFG_FILT_CFG_H2 (4UL) 2124 #define QEIV2_FILT_CFG_FILT_CFG_F (5UL) 2125 2126 /* UVW_POS register group index macro definition */ 2127 #define QEIV2_UVW_POS_UVW_POS0 (0UL) 2128 #define QEIV2_UVW_POS_UVW_POS1 (1UL) 2129 #define QEIV2_UVW_POS_UVW_POS2 (2UL) 2130 #define QEIV2_UVW_POS_UVW_POS3 (3UL) 2131 #define QEIV2_UVW_POS_UVW_POS4 (4UL) 2132 #define QEIV2_UVW_POS_UVW_POS5 (5UL) 2133 2134 /* UVW_POS_CFG register group index macro definition */ 2135 #define QEIV2_UVW_POS_CFG_UVW_POS0_CFG (0UL) 2136 #define QEIV2_UVW_POS_CFG_UVW_POS1_CFG (1UL) 2137 #define QEIV2_UVW_POS_CFG_UVW_POS2_CFG (2UL) 2138 #define QEIV2_UVW_POS_CFG_UVW_POS3_CFG (3UL) 2139 #define QEIV2_UVW_POS_CFG_UVW_POS4_CFG (4UL) 2140 #define QEIV2_UVW_POS_CFG_UVW_POS5_CFG (5UL) 2141 2142 2143 #endif /* HPM_QEIV2_H */ 2144