1 /* Define for CH579 */ 2 /* Website: http://wch.cn */ 3 /* Email: tech@wch.cn */ 4 /* Author: W.ch 2016.10 */ 5 /* V0.2 SpecialFunctionRegister */ 6 7 // multi-blocks: __BASE_TYPE__, __CH579SFR_H__, __CH579ETHSFR_H__, __CH579USBSFR_H__, __USB_TYPE__... 8 9 #ifndef __BASE_TYPE__ 10 #define __BASE_TYPE__ 11 12 #ifdef __cplusplus 13 extern "C" { 14 #endif 15 16 /* ********************************************************************************************************************* */ 17 /* Base types & constants */ 18 19 #ifndef TRUE 20 #define TRUE 1 21 #define FALSE 0 22 #endif 23 #ifndef NULL 24 #define NULL 0 25 #endif 26 27 #ifndef VOID 28 #define VOID void 29 #endif 30 #ifndef CONST 31 #define CONST const 32 #endif 33 #ifndef BOOL 34 typedef unsigned char BOOL; 35 #endif 36 #ifndef BOOLEAN 37 typedef unsigned char BOOLEAN; 38 #endif 39 #ifndef CHAR 40 typedef char CHAR; 41 #endif 42 #ifndef INT8 43 typedef char INT8; 44 #endif 45 #ifndef INT16 46 typedef short INT16; 47 #endif 48 #ifndef INT32 49 typedef long INT32; 50 #endif 51 #ifndef UINT8 52 typedef unsigned char UINT8; 53 #endif 54 #ifndef UINT16 55 typedef unsigned short UINT16; 56 #endif 57 #ifndef UINT32 58 typedef unsigned long UINT32; 59 #endif 60 #ifndef UINT8V 61 typedef unsigned char volatile UINT8V; 62 #endif 63 #ifndef UINT16V 64 typedef unsigned short volatile UINT16V; 65 #endif 66 #ifndef UINT32V 67 typedef unsigned long volatile UINT32V; 68 #endif 69 70 #ifndef PVOID 71 typedef void *PVOID; 72 #endif 73 #ifndef PCHAR 74 typedef char *PCHAR; 75 #endif 76 #ifndef PCHAR 77 typedef const char *PCCHAR; 78 #endif 79 #ifndef PINT8 80 typedef char *PINT8; 81 #endif 82 #ifndef PINT16 83 typedef short *PINT16; 84 #endif 85 #ifndef PINT32 86 typedef long *PINT32; 87 #endif 88 #ifndef PUINT8 89 typedef unsigned char *PUINT8; 90 #endif 91 #ifndef PUINT16 92 typedef unsigned short *PUINT16; 93 #endif 94 #ifndef PUINT32 95 typedef unsigned long *PUINT32; 96 #endif 97 #ifndef PUINT8V 98 typedef volatile unsigned char *PUINT8V; 99 #endif 100 #ifndef PUINT16V 101 typedef volatile unsigned short *PUINT16V; 102 #endif 103 #ifndef PUINT32V 104 typedef volatile unsigned long *PUINT32V; 105 #endif 106 107 /* ********************************************************************************************************************* */ 108 /* Base macros */ 109 110 #ifndef min 111 #define min(a,b) (((a) < (b)) ? (a) : (b)) 112 #endif 113 #ifndef max 114 #define max(a,b) (((a) > (b)) ? (a) : (b)) 115 #endif 116 117 #ifdef DEBUG 118 #define PRINT(X...) printf(X) 119 #else 120 #define PRINT(X...) 121 #endif 122 123 /* Calculate the byte offset of a field in a structure of type */ 124 #define FIELD_OFFSET(Type, Field) ((UINT16)&(((Type *)0)->Field)) 125 126 /* Calculate the size of a field in a structure of type */ 127 #define FIELD_SIZE(Type, Field) (sizeof(((Type *)0)->Field)) 128 129 /* An expression that yields the type of a field in a struct */ 130 #define FIELD_TYPE(Type, Field) (((Type *)0)->Field) 131 132 /* Return the number of elements in a statically sized array */ 133 #define NUMBER_OF(Array) (sizeof(Array)/sizeof((Array)[0])) 134 #define NUMBER_OF_FIELD(Type, Field) (NUMBER_OF(FIELD_TYPE(Type, Field))) 135 136 #ifdef __cplusplus 137 } 138 #endif 139 140 #endif // __BASE_TYPE__ 141 142 143 #ifndef __CH579SFR_H__ 144 #define __CH579SFR_H__ 145 146 #ifdef __cplusplus 147 extern "C" { 148 #endif 149 150 /* ********************************************************************************************************************* */ 151 152 // Address Space 153 // CODE: 00000000H - 0003FFFFH 256K 154 // DATA: 20000000H - 20007FFFH 32KB 155 // SFR: 40000000H - 4000FFFFH 64KB 156 // PPB: E0000000H - E000FFFFH 64KB 157 // 158 // SFR: 40000000H - 4000FFFFH, 64KB 159 // SYS: +1000H - 1BFFH, include base configuration, interrupt, GPIO, etc... 160 // TMR0: +2000H - 23FFH 161 // TMR1: +2400H - 27FFH 162 // TMR2: +2800H - 2BFFH 163 // TMR3: +2C00H - 2FFFH 164 // UART0: +3000H - 33FFH 165 // UART1: +3400H - 37FFH 166 // UART2: +3800H - 3BFFH 167 // UART3: +3C00H - 3FFFH 168 // SPI0: +4000H - 43FFH 169 // SPI1: +4400H - 47FFH 170 // PWMx: +5000H - 53FFH 171 // LCD: +6000H - 63FFH 172 // LED: +6400H - 67FFH 173 // USB: +8000H - 83FFH 174 // ETH: +9000H - 93FFH 175 // BLE: +C000H - D3FFH 176 177 // Register Bit Attribute / Bit Access Type 178 // RF: Read only for Fixed value 179 // RO: Read Only (internal change) 180 // RZ: Read only with auto clear Zero 181 // WO: Write Only (read zero or different) 182 // WA: Write only under safe Accessing mode (read zero or different) 183 // WZ: Write only with auto clear Zero 184 // RW: Read / Write 185 // RWA: Read / Write under safe Accessing mode 186 // RW1: Read / Write 1 to Clear 187 188 /* Register name rule: 189 R32_* for 32 bits register (UINT32,ULONG) 190 R16_* for 16 bits register (UINT16,USHORT) 191 R8_* for 8 bits register (UINT8,UCHAR) 192 RB_* for bit or bit mask of 8 bit register 193 BA_* for base address point 194 b* for GPIO bit mask 195 Others for register address offset */ 196 197 /* ********************************************************************************************************************* */ 198 199 /* System: safe accessing register */ 200 #define R32_SAFE_ACCESS (*((PUINT32V)0x40001040)) // RW, safe accessing 201 #define R8_SAFE_ACCESS_SIG (*((PUINT8V)0x40001040)) // WO, safe accessing sign register, must write SAFE_ACCESS_SIG1 then SAFE_ACCESS_SIG2 to enter safe accessing mode 202 #define RB_SAFE_ACC_MODE 0x03 // RO, current safe accessing mode: 11=safe/unlocked (SAM), other=locked (00..01..10..11) 203 #define RB_SAFE_ACC_ACT 0x08 // RO, indicate safe accessing status now: 0=locked, read only, 1=safe/unlocked (SAM), write enabled 204 #define RB_SAFE_ACC_TIMER 0x70 // RO, safe accessing timer bit mask (16*clock number) 205 #define SAFE_ACCESS_SIG1 0x57 // WO: safe accessing sign value step 1 206 #define SAFE_ACCESS_SIG2 0xA8 // WO: safe accessing sign value step 2 207 #define SAFE_ACCESS_SIG0 0x00 // WO: safe accessing sign value for disable 208 #define R8_CHIP_ID (*((PUINT8V)0x40001041)) // RF, chip ID register, always is ID_CH57* 209 #define R8_SAFE_ACCESS_ID (*((PUINT8V)0x40001042)) // RF, safe accessing ID register, always 0x04 210 #define R8_WDOG_COUNT (*((PUINT8V)0x40001043)) // RW, watch-dog count, count by clock frequency Fsys/131072 211 212 /* System: global configuration register */ 213 #define R32_GLOBAL_CONFIG (*((PUINT32V)0x40001044)) // RW, global configuration 214 #define R8_RESET_STATUS (*((PUINT8V)0x40001044)) // RWA, reset status, SAM 215 #define RB_RESET_FLAG 0x07 // RO: recent reset flag 216 #define RST_FLAG_SW 0x00 217 #define RST_FLAG_RPOR 0x01 218 #define RST_FLAG_WTR 0x02 219 #define RST_FLAG_MR 0x03 220 //#define RST_FLAG_GPWSM 0x04 // RO, power on reset flag during sleep/shutdown: 0=no power on reset during sleep/shutdown, 1=power on reset occurred during sleep/shutdown 221 #define RST_FLAG_GPWSM 0x05 222 #define RB_ROM_CODE_OFS 0x10 // RWA, code offset address selection in Flash ROM: 0=start address 0x000000, 1=start address 0x008000 223 // RB_RESET_FLAG: recent reset flag 224 // 000 - SR, software reset, by RB_SOFTWARE_RESET=1 @RB_WDOG_RST_EN=0 225 // 001 - RPOR, real power on reset 226 // 010 - WTR, watch-dog timer-out reset 227 // 011 - MR, external manual reset by RST pin input low 228 // 101 - GRWSM, global reset by waking under shutdown mode 229 // 1?? - LRW, power on reset occurred during sleep 230 #define R8_GLOB_CFG_INFO (*((PUINT8V)0x40001045)) // RO, global configuration information and status 231 #define RB_CFG_ROM_READ 0x01 // RO, indicate protected status of Flash ROM code and data: 0=reading protect, 1=enable read by external programmer 232 #define RB_CFG_RESET_EN 0x04 // RO, manual reset input enable status 233 #define RB_CFG_BOOT_EN 0x08 // RO, boot-loader enable status 234 #define RB_CFG_DEBUG_EN 0x10 // RO, debug enable status 235 #define RB_BOOT_LOADER 0x20 // RO, indicate boot loader status: 0=application status (by software reset), 1=boot loader status 236 #define R8_RST_WDOG_CTRL (*((PUINT8V)0x40001046)) // RWA, reset and watch-dog control, SAM 237 #define RB_SOFTWARE_RESET 0x01 // WA/WZ, global software reset, high action, auto clear 238 #define RB_WDOG_RST_EN 0x02 // RWA, enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow 239 #define RB_WDOG_INT_EN 0x04 // RWA, watch-dog timer overflow interrupt enable: 0=disable, 1=enable 240 #define RB_WDOG_INT_FLAG 0x10 // RW1, watch-dog timer overflow interrupt flag, cleared by RW1 or reload watch-dog count or __SEV(Send-Event) 241 #define R8_GLOB_RESET_KEEP (*((PUINT8V)0x40001047)) // RW, value keeper during global reset 242 243 /* System: clock configuration register */ 244 #define R32_CLOCK_CONFIG (*((PUINT32V)0x40001008)) // RWA, clock configuration, SAM 245 #define R16_CLK_SYS_CFG (*((PUINT16V)0x40001008)) // RWA, system clock configuration, SAM 246 #define RB_CLK_PLL_DIV 0x1F // RWA, output clock divider from PLL or CK32M 247 #define RB_CLK_SYS_MOD 0xC0 // RWA, system clock source mode: 00=divided from 32MHz, 01=divided from PLL-480MHz, 10=directly from 32MHz, 11=directly from 32KHz 248 #define RB_CLK_OSC32M_XT 0x0200 // RWA, 32MHz clock source selection: 0=internal 32MHz oscillator, 1=external 32MHz oscillator 249 #define RB_XO_DI 0x8000 // RO, X32MO input status sample value 250 #define R8_HFCK_PWR_CTRL (*((PUINT8V)0x4000100A)) // RWA, high frequency clock module power control, SAM 251 #define RB_CLK_XT32M_PON 0x04 // RWA, external 32MHz oscillator power control: 0=power down, 1-power on 252 #define RB_CLK_INT32M_PON 0x08 // RWA, internal 32MHz oscillator power control: 0=power down, 1-power on 253 #define RB_CLK_PLL_PON 0x10 // RWA, PLL power control: 0=power down, 1-power on 254 // Fck32m = RB_CLK_OSC32M_XT ? XT_32MHz : RC_32MHz 255 // Fck32k = RB_CLK_OSC32K_XT ? XT_32KHz : RC_32KHz 256 // Fpll = Fck32m * 15 = 480MHz 257 // Fsys = RB_CLK_SYS_MOD[1] ? ( RB_CLK_SYS_MOD[0] ? Fck32k : Fck32m ) : ( ( RB_CLK_SYS_MOD[0] ? Fpll : Fck32m ) / RB_CLK_PLL_DIV ) 258 // default: Fsys = Fck32m / RB_CLK_PLL_DIV = 32MHz / 5 = 6.4MHz 259 // range: 32KHz, 1MHz~16MHz, 32MHz, 15MHz~48MHz 260 261 /* System: sleep control register */ 262 #define R32_SLEEP_CONTROL (*((PUINT32V)0x4000100C)) // RWA, sleep control, SAM 263 #define R8_SLP_CLK_OFF0 (*((PUINT8V)0x4000100C)) // RWA, sleep clock off control byte 0, SAM 264 #define RB_SLP_CLK_TMR0 0x01 // RWA, close TMR0 clock 265 #define RB_SLP_CLK_TMR1 0x02 // RWA, close TMR1 clock 266 #define RB_SLP_CLK_TMR2 0x04 // RWA, close TMR2 clock 267 #define RB_SLP_CLK_TMR3 0x08 // RWA, close TMR3 clock 268 #define RB_SLP_CLK_UART0 0x10 // RWA, close UART0 clock 269 #define RB_SLP_CLK_UART1 0x20 // RWA, close UART1 clock 270 #define RB_SLP_CLK_UART2 0x40 // RWA, close UART2 clock 271 #define RB_SLP_CLK_UART3 0x80 // RWA, close UART3 clock 272 #define R8_SLP_CLK_OFF1 (*((PUINT8V)0x4000100D)) // RWA, sleep clock off control byte 1, SAM 273 #define RB_SLP_CLK_SPI0 0x01 // RWA, close SPI0 clock 274 #define RB_SLP_CLK_SPI1 0x02 // RWA, close SPI1 clock 275 #define RB_SLP_CLK_PWMX 0x04 // RWA, close PWMx clock 276 #define RB_SLP_CLK_LCD 0x08 // RWA, close LCD clock 277 #define RB_SLP_CLK_USB 0x10 // RWA, close USB clock 278 #define RB_SLP_CLK_ETH 0x20 // RWA, close ETH clock 279 #define RB_SLP_CLK_LED 0x40 // RWA, close LED clock 280 #define RB_SLP_CLK_BLE 0x80 // RWA, close BLE clock 281 #define R8_SLP_WAKE_CTRL (*((PUINT8V)0x4000100E)) // RWA, wake control, SAM 282 #define RB_SLP_USB_WAKE 0x01 // RWA, enable USB waking 283 #define RB_SLP_ETH_WAKE 0x02 // RWA, enable ETH waking 284 //#define RB_SLP_BLE_WAKE 0x04 // RWA, enable BLE waking 285 #define RB_SLP_RTC_WAKE 0x08 // RWA, enable RTC waking 286 #define RB_SLP_GPIO_WAKE 0x10 // RWA, enable GPIO waking 287 #define RB_SLP_BAT_WAKE 0x20 // RWA, enable BAT waking 288 #define R8_SLP_POWER_CTRL (*((PUINT8V)0x4000100F)) // RWA, peripherals power down control, SAM 289 //#define RB_SLP_USB_PWR_DN 0x01 // RWA, enable USB power down 290 #define RB_SLP_ETH_PWR_DN 0x02 // RWA, enable ETH PHY power down 291 //#define RB_SLP_BLE_PWR_DN 0x04 // RWA, enable BLE power down 292 #define RB_SLP_ROM_PWR_DN 0x08 // RWA, enable Flash ROM power down during halt 293 #define RB_SLP_CLK_RAMX 0x10 // RWA, close main SRAM clock 294 #define RB_SLP_CLK_RAM2K 0x20 // RWA, close retention 2KB SRAM clock 295 296 /* System: I/O pin configuration register */ 297 #define R32_PIN_CONFIG (*((PUINT32V)0x40001018)) // RW, I/O pin configuration 298 #define R16_PIN_ALTERNATE (*((PUINT16V)0x40001018)) // RW, function pin alternate configuration 299 #define RB_PIN_TMR0 0x01 // RW, TMR0 alternate pin enable: 0=TMR0/PWM0/CAP0 on PA[3], 1=TMR0_/PWM0_/CAP0_ on PB[19] 300 #define RB_PIN_TMR1 0x02 // RW, TMR1 alternate pin enable: 0=TMR1/PWM1/CAP1 on PA[10], 1=TMR1_/PWM1_/CAP1_ on PB[10] 301 #define RB_PIN_TMR2 0x04 // RW, TMR2 alternate pin enable: 0=TMR2/PWM2/CAP2 on PA[11], 1=TMR2_/PWM2_/CAP2_ on PB[11] 302 #define RB_PIN_TMR3 0x08 // RW, TMR3 alternate pin enable: 0=TMR3/PWM3/CAP3 on PA[2], 1=TMR3_/PWM3_/CAP3_ on PB[18] 303 #define RB_PIN_UART0 0x10 // RW, RXD0/TXD0 alternate pin enable: 0=RXD0/TXD0 on PB[4]/PB[7], 1=RXD0_/TXD0_ on PA[15]/PA[14] 304 #define RB_PIN_UART1 0x20 // RW, RXD1/TXD1 alternate pin enable: 0=RXD1/TXD1 on PA[8]/PA[9], 1=RXD1_/TXD1_ on PB[8]/PB[9] 305 #define RB_PIN_UART2 0x40 // RW, RXD2/TXD2 alternate pin enable: 0=RXD2/TXD2 on PA[6]/PA[7], 1=RXD2_/TXD2_ on PB[22]/PB[23] 306 #define RB_PIN_UART3 0x80 // RW, RXD3/TXD3 alternate pin enable: 0=RXD3/TXD3 on PA[4]/PA[5], 1=RXD3_/TXD3_ on PB[20]/PB[21] 307 #define RB_PIN_SPI0 0x100 // RW, SCS/SCK0/MOSI/MISO alternate pin enable: 0=SCS/SCK0/MOSI/MISO on PA[12]/PA[13]/PA[14]/PA[15], 1=SCS_/SCK0_/MOSI_/MISO_ on PB[12]/PB[13]/PB[14]/PB[15] 308 #define R16_PIN_ANALOG_IE (*((PUINT16V)0x4000101A)) // RW, analog pin enable and digital input disable 309 #define RB_PIN_SEG0_3_IE 0x01 // RW, LCD segment 0~3 digital input disable: 0=digital input enable, 1=digital input disable 310 #define RB_PIN_SEG4_7_IE 0x02 // RW, LCD segment 4~7 digital input disable: 0=digital input enable, 1=digital input disable 311 #define RB_PIN_SEG8_11_IE 0x04 // RW, LCD segment 8~11 digital input disable: 0=digital input enable, 1=digital input disable 312 #define RB_PIN_SEG12_15_IE 0x08 // RW, LCD segment 12~15 digital input disable: 0=digital input enable, 1=digital input disable 313 #define RB_PIN_SEG16_19_IE 0x10 // RW, LCD segment 16~19 digital input disable: 0=digital input enable, 1=digital input disable 314 #define RB_PIN_SEG20_23_IE 0x20 // RW, LCD segment 20~23 digital input disable: 0=digital input enable, 1=digital input disable 315 #define RB_PIN_ETH_IE 0x40 // RW, ETH analog I/O enable and digital input disable: 0=analog I/O disable and digital input enable, 1=analog I/O enable and digital input disable 316 #define RB_PIN_USB_IE 0x80 // RW, USB analog I/O enable: 0=analog I/O disable, 1=analog I/O enable 317 #define RB_PIN_ADC8_9_IE 0x0100 // RW, ADC/TouchKey channel 9/8 digital input disable: 0=digital input enable, 1=digital input disable 318 #define RB_PIN_ADC6_7_IE 0x0200 // RW, ADC/TouchKey channel 7/6 digital input disable: 0=digital input enable, 1=digital input disable 319 #define RB_PIN_ADC0_1_IE 0x0400 // RW, ADC/TouchKey channel 0/1 digital input disable: 0=digital input enable, 1=digital input disable 320 #define RB_PIN_ADC10_11_IE 0x0800 // RW, ADC/TouchKey channel 10/11 digital input disable: 0=digital input enable, 1=digital input disable 321 #define RB_PIN_ADC12_13_IE 0x1000 // RW, ADC/TouchKey channel 12/13 digital input disable: 0=digital input enable, 1=digital input disable 322 #define RB_PIN_XT32K_IE 0x2000 // RW, external 32KHz oscillator digital input disable: 0=digital input enable, 1=digital input disable 323 #define RB_PIN_ADC2_3_IE 0x4000 // RW, ADC/TouchKey channel 2/3 digital input disable: 0=digital input enable, 1=digital input disable 324 #define RB_PIN_ADC4_5_IE 0x8000 // RW, ADC/TouchKey channel 4/5 digital input disable: 0=digital input enable, 1=digital input disable 325 326 /* System: parallel slave configuration register */ 327 #define R32_PARA_SLV_CFG (*((PUINT32V)0x4000101C)) // RW, parallel slave configuration 328 #define R8_SLV_CONFIG (*((PUINT8V)0x4000101C)) // RW, parallel slave configuration 329 #define RB_SLV_ENABLE 0x01 // RW, parallel slave enable 330 #define RB_SLV_IE_CMD 0x02 // RW, enable interrupt for slave writing command event 331 #define RB_SLV_IE_WR 0x04 // RW, enable interrupt for slave writing event 332 #define RB_SLV_IE_RD 0x08 // RW, enable interrupt for slave reading event 333 #define RB_IF_SLV_CMD 0x20 // RO, parallel slave command synchronous flag 334 #define RB_IF_SLV_WR 0x40 // RW1, interrupt flag of parallel slave writing event 335 #define RB_IF_SLV_RD 0x80 // RW1, interrupt flag of parallel slave reading event 336 #define R8_SLV_RD_DATA (*((PUINT8V)0x400010C8)) // RW, data for parallel slave read 337 #define R8_SLV_RD_STAT (*((PUINT8V)0x40001096)) // RW, status for parallel slave read 338 #define R8_SLV_WR_DATA (*((PUINT8V)0x40001097)) // RW, data or command from parallel slave write 339 340 /* System: power management register */ 341 #define R32_POWER_MANAG (*((PUINT32V)0x40001020)) // RWA, power management register, SAM 342 #define R16_POWER_PLAN (*((PUINT16V)0x40001020)) // RWA, power plan before sleep instruction, SAM 343 #define RB_PWR_RAM2K 0x02 // RWA, power for retention 2KB SRAM 344 #define RB_PWR_CORE 0x04 // RWA, power retention for core and base peripherals 345 #define RB_PWR_EXTEND 0x08 // RWA, power retention for USB and BLE 346 #define RB_PWR_RAM14K 0x10 // RWA, power for main SRAM 347 #define RB_PWR_SYS_EN 0x80 // RWA, power for system 348 #define RB_PWR_LDO_EN 0x0100 // RWA, LDO enable 349 #define RB_PWR_DCDC_EN 0x0200 // RWA, DC/DC converter enable: 0=DC/DC disable and bypass, 1=DC/DC enable 350 #define RB_PWR_DCDC_PRE 0x0400 // RWA, DC/DC converter pre-enable 351 #define RB_PWR_PLAN_EN 0x8000 // RWA/WZ, power plan enable, auto clear after sleep executed 352 #define RB_PWR_MUST_0010 0x1000 // RWA, must write 0010 353 #define R8_AUX_POWER_ADJ (*((PUINT8V)0x40001022)) // RWA, aux power adjust control, SAM 354 #define RB_ULPLDO_ADJ 0x0007 // RWA, Ultra-Low-Power LDO voltage adjust 355 356 /* System: battery detector register */ 357 #define R32_BATTERY_CTRL (*((PUINT32V)0x40001024)) // RWA, battery voltage detector, SAM 358 #define R8_BAT_DET_CTRL (*((PUINT8V)0x40001024)) // RWA, battery voltage detector control, SAM 359 #define RB_BAT_DET_EN 0x01 // RWA, battery voltage detector enable 360 #define RB_BAT_LOWER_IE 0x04 // RWA, interrupt enable for battery lower voltage 361 #define RB_BAT_LOW_IE 0x08 // RWA, interrupt enable for battery low voltage 362 // request NMI interrupt if both RB_BAT_LOWER_IE and RB_BAT_LOW_IE enabled 363 #define R8_BAT_DET_CFG (*((PUINT8V)0x40001025)) // RWA, battery voltage detector configuration, SAM 364 #define RB_BAT_LOW_VTH 0x03 // RWA, select threshold voltage of battery voltage low 365 #define R8_BAT_STATUS (*((PUINT8V)0x40001026)) // RO, battery status 366 #define RB_BAT_STAT_LOWER 0x01 // RO, battery lower voltage status, high action 367 #define RB_BAT_STAT_LOW 0x02 // RO, battery low voltage status, high action 368 369 /* System: 32KHz oscillator control register */ 370 #define R32_OSC32K_CTRL (*((PUINT32V)0x4000102C)) // RWA, 32KHz oscillator control, SAM 371 #define R16_INT32K_TUNE (*((PUINT16V)0x4000102C)) // RWA, internal 32KHz oscillator tune control, SAM 372 #define RB_INT32K_TUNE 0x03FF // RWA, internal 32KHz oscillator frequency tune 373 #define R8_XT32K_TUNE (*((PUINT8V)0x4000102E)) // RWA, external 32KHz oscillator tune control, SAM 374 #define RB_XT32K_I_TUNE 0x03 // RWA, external 32KHz oscillator current tune: 00=75% current, 01=standard current, 10=150% current, 11=200% current 375 #define RB_XT32K_C_LOAD 0xF0 // RWA, external 32KHz oscillator load capacitor tune: Cap = RB_XT32K_C_LOAD + 12pF 376 #define R8_CK32K_CONFIG (*((PUINT8V)0x4000102F)) // RWA, 32KHz oscillator configure 377 #define RB_CLK_XT32K_PON 0x01 // RWA, external 32KHz oscillator power on 378 #define RB_CLK_INT32K_PON 0x02 // RWA, internal 32KHz oscillator power on 379 #define RB_CLK_OSC32K_XT 0x04 // RWA, 32KHz oscillator source selection: 0=RC, 1=XT 380 #define RB_32K_CLK_PIN 0x80 // RO, 32KHz oscillator clock pin status 381 382 /* System: real-time clock register */ 383 #define R32_RTC_CTRL (*((PUINT32V)0x40001030)) // RWA, RTC control, SAM 384 #define R8_RTC_FLAG_CTRL (*((PUINT8V)0x40001030)) // RW, RTC flag and clear control 385 #define RB_RTC_TMR_CLR 0x10 // RW, set 1 to clear RTC timer action flag, auto clear 386 #define RB_RTC_TRIG_CLR 0x20 // RW, set 1 to clear RTC trigger action flag, auto clear 387 #define RB_RTC_TMR_FLAG 0x40 // RO, RTC timer action flag 388 #define RB_RTC_TRIG_FLAG 0x80 // RO, RTC trigger action flag 389 #define R8_RTC_MODE_CTRL (*((PUINT8V)0x40001031)) // RWA, RTC mode control, SAM 390 #define RB_RTC_TMR_MODE 0x07 // RWA, RTC timer mode: 000=0.125S, 001=0.25S, 010=0.5S, 011=1S, 100=2S, 101=4S, 110=8S, 111=16S 391 #define RB_RTC_IGNORE_B0 0x08 // RWA, force ignore bit0 for trigger mode: 0=compare bit0, 1=ignore bit0 392 #define RB_RTC_TMR_EN 0x10 // RWA, RTC timer mode enable 393 #define RB_RTC_TRIG_EN 0x20 // RWA, RTC trigger mode enable 394 #define RB_RTC_LOAD_LO 0x40 // RWA, set 1 to load RTC count low word R32_RTC_CNT_32K, auto clear after loaded 395 #define RB_RTC_LOAD_HI 0x80 // RWA, set 1 to load RTC count high word R32_RTC_CNT_DAY, auto clear after loaded 396 #define R32_RTC_TRIG (*((PUINT32V)0x40001034)) // RWA, RTC trigger value, SAM 397 #define R32_RTC_CNT_32K (*((PUINT32V)0x40001038)) // RO, RTC count based 32KHz 398 #define R16_RTC_CNT_32K (*((PUINT16V)0x40001038)) // RO, RTC count based 32KHz 399 #define R16_RTC_CNT_2S (*((PUINT16V)0x4000103A)) // RO, RTC count based 2 second 400 #define R32_RTC_CNT_DAY (*((PUINT32V)0x4000103C)) // RO, RTC count based one day, only low 14 bit 401 402 /*System: Miscellaneous Control register */ 403 #define R32_MISC_CTRL (*((PUINT32V)0x40001048)) // RWA, miscellaneous control register 404 #define R8_CFG_FLASH (*((PUINT8V)0x4000104A)) // RWA, Flash ROM configure register 405 #define RB_CFG_FLASH_X 0x0F // RWA, Flash ROM configure data, keep the value unchanged if write 406 #define RB_FLASH_BUSY_EN 0x80 // RWA, enable ROM busy if burst reading: 1-enable(suggest), 0-disable 407 #define R8_PLL_CONFIG (*((PUINT8V)0x4000104B)) // RWA, PLL configuration control, SAM 408 #define RB_PLL_CFG_DAT 0x03 // RWA, PLL configure data 409 #define RB_PLL_LOCKED 0x80 // RO, indicate PLL locked 410 411 /* System: 32MHz oscillator control register */ 412 #define R32_OSC32M_CTRL (*((PUINT32V)0x4000104C)) // RWA, 32MHz oscillator control, SAM 413 #define R8_INT32M_CALIB (*((PUINT8V)0x4000104C)) // RWA, internal 32MHz oscillator tune control, SAM 414 #define R8_XT32M_TUNE (*((PUINT8V)0x4000104E)) // RWA, external 32MHz oscillator tune control, SAM 415 #define RB_XT32M_I_BIAS 0x03 // RWA, external 32MHz oscillator bias current tune: 00=75% current, 01=standard current, 10=125% current, 11=150% current 416 #define RB_XT32M_C_LOAD 0x70 // RWA, external 32MHz oscillator load capacitor tune: Cap = RB_XT32M_C_LOAD * 2 + 10pF 417 418 /* System: oscillator frequency calibration register */ 419 #define R32_OSC_CALIB (*((PUINT32V)0x40001050)) // RWA, oscillator frequency calibration, SAM 420 #define R16_OSC_CAL_CNT (*((PUINT16V)0x40001050)) // RO, system clock count value for 32KHz 5 cycles 421 #define RB_OSC_CAL_CNT 0x0FFF // RO, system clock count value for 32KHz 5 cycles 422 #define R8_OSC_CAL_CTRL (*((PUINT8V)0x40001052)) // RWA, oscillator frequency calibration control, SAM 423 #define RB_OSC_CNT_EN 0x01 // RWA, calibration counter enable 424 #define RB_OSC_CNT_HALT 0x02 // RO, calibration counter halt status: 0=counting, 1=halt for reading count value 425 426 /* System: ADC and Touch-key register */ 427 #define R32_ADC_CTRL (*((PUINT32V)0x40001058)) // RW, ADC control 428 #define R8_ADC_CHANNEL (*((PUINT8V)0x40001058)) // RW, ADC input channel selection 429 #define RB_ADC_CH_INX 0x0F // RW, ADC input channel index 430 #define R8_ADC_CFG (*((PUINT8V)0x40001059)) // RW, ADC configure 431 #define RB_ADC_POWER_ON 0x01 // RW, ADC power control: 0=power down, 1=power on 432 #define RB_ADC_BUF_EN 0x02 // RW, ADC input buffer enable 433 #define RB_ADC_DIFF_EN 0x04 // RW, ADC input channel mode: 0=single-end, 1=differnetial 434 #define RB_ADC_OFS_TEST 0x08 // RW, enable ADC offset test mode: 0=normal mode, 1=short port4 to test offset 435 #define RB_ADC_PGA_GAIN 0x30 // RW, set ADC input PGA gain: 00=-12dB, 01=-6dB, 10=0dB, 11=6dB 436 #define RB_ADC_CLK_DIV 0xC0 // RW, select ADC clock frequency: 00=3.2MHz, 01=2.67MHz, 10=5.33MHz, 11=4MHz 437 #define R8_ADC_CONVERT (*((PUINT8V)0x4000105A)) // RW, ADC convert control 438 #define RB_ADC_START 0x01 // RW, ADC convert start control: 0=stop ADC convert, 1=start an ADC convert, auto clear 439 #define RB_ADC_EOC_X 0x80 // RO, end of ADC conversion flag 440 #define R8_TEM_SENSOR (*((PUINT8V)0x4000105B)) // RW, temperature sensor control 441 #define RB_TEM_SEN_CALIB 0x07 // RW, temperature sensor calibration 442 #define RB_TEM_SEN_PWR_ON 0x80 // RW, temperature sensor power control: 0=power down, 1=power on 443 #define R32_ADC_DATA (*((PUINT32V)0x4000105C)) // RO, ADC data and status 444 #define R16_ADC_DATA (*((PUINT16V)0x4000105C)) // RO, ADC data 445 #define RB_ADC_DATA 0x0FFF // RO, ADC conversion data 446 #define R8_ADC_INT_FLAG (*((PUINT8V)0x4000105E)) // RO, ADC interrupt flag register 447 #define RB_ADC_IF_EOC 0x80 // RO, ADC conversion interrupt flag: 0=free or converting, 1=end of conversion, interrupt action, write R8_ADC_CONVERT to clear flag 448 #define R8_TKEY_CTRL (*((PUINT8V)0x4000105A)) // RW, Touchkey capacity charge and discharge status 449 #define RB_TKEY_PWR_ON 0x08 // RW, Touchkey power on: 0=power down, 1=power on 450 #define RB_TKEY_ACTION 0x10 // RO, Touchkey action status: 0=free, 1=discharge or charge or ADC 451 #define RB_TKEY_CHG_ACT 0x20 // RO, Touchkey capacity charge status: 0=free, 1=charge 452 #define R8_TKEY_CNT (*((PUINT8V)0x4000105F)) // WO, Touch-key charge and discharge count 453 454 /* System: Flash ROM control register */ 455 #define R32_FLASH_DATA (*((PUINT32V)0x40001800)) // RW, Flash ROM data 456 #define R32_FLASH_ADDR (*((PUINT32V)0x40001804)) // RW, Flash ROM address 457 #define R32_FLASH_CTRL (*((PUINT32V)0x40001808)) // RW, Flash ROM control and status 458 #define R8_FLASH_COMMAND (*((PUINT8V)0x40001808)) // WO, Flash ROM operation command 459 #define ROM_CMD_PROG 0x9A // WO: Flash ROM word program operation command, for changing some ROM bit of a word from 1 to 0 460 #define ROM_CMD_ERASE 0xA6 // WO: Flash ROM sector erase operation command, for changing all ROM bit of 512Bytes from 0 to 1 461 #define R8_FLASH_PROTECT (*((PUINT8V)0x40001809)) // RW, Flash ROM protect control 462 #define RB_ROM_DATA_WE 0x04 // RW, enable Flash ROM data area being erase/write: 0=writing protect, 1=enable program and erase 463 #define RB_ROM_CODE_WE 0x08 // RW, enable Flash ROM code area being erase/write: 0=writing protect, 1=enable program and erase 464 #define RB_ROM_WE_MUST_10 0x80 // RW, must write 10 465 #define R16_FLASH_STATUS (*((PUINT16V)0x4000180A)) // RO, Flash ROM operation status 466 #define R8_FLASH_STATUS (*((PUINT8V)0x4000180A)) // RO, Flash ROM operation status 467 #define RB_ROM_CMD_TOUT 0x01 // RO, Flash ROM operation result: 0=success, 1=operation time out 468 #define RB_ROM_CMD_ERR 0x02 // RO, Flash ROM operation command error flag: 0=command accepted, 1=unknown command 469 #define RB_ROM_ADDR_OK 0x40 // RO, Flash ROM erase/write operation address valid flag, can be reviewed before or after operation: 0=invalid parameter, 1=address valid 470 #define RB_ROM_READ_FREE 0x100 // RO, indicate protected status of Flash ROM code and data: 0=reading protect, 1=enable read by external programmer 471 472 /* System: GPIO interrupt control register */ 473 #define R32_GPIO_INT_EN (*((PUINT32V)0x40001090)) // RW, GPIO interrupt enable 474 #define R16_PA_INT_EN (*((PUINT16V)0x40001090)) // RW, GPIO PA interrupt enable 475 #define R16_PB_INT_EN (*((PUINT16V)0x40001092)) // RW, GPIO PB interrupt enable 476 #define R32_GPIO_INT_MODE (*((PUINT32V)0x40001094)) // RW, GPIO interrupt mode: 0=level action, 1=edge action 477 #define R16_PA_INT_MODE (*((PUINT16V)0x40001094)) // RW, GPIO PA interrupt mode: 0=level action, 1=edge action 478 #define R16_PB_INT_MODE (*((PUINT16V)0x40001096)) // RW, GPIO PB interrupt mode: 0=level action, 1=edge action 479 #define R32_GPIO_INT_IF (*((PUINT32V)0x4000109C)) // RW1, GPIO interrupt flag 480 #define R16_PA_INT_IF (*((PUINT16V)0x4000109C)) // RW1, GPIO PA interrupt flag 481 #define R16_PB_INT_IF (*((PUINT16V)0x4000109E)) // RW1, GPIO PB interrupt flag 482 483 /* GPIO PA register */ 484 #define R32_PA_DIR (*((PUINT32V)0x400010A0)) // RW, GPIO PA I/O direction: 0=in, 1=out 485 #define R8_PA_DIR_0 (*((PUINT8V)0x400010A0)) // RW, GPIO PA I/O direction byte 0 486 #define R8_PA_DIR_1 (*((PUINT8V)0x400010A1)) // RW, GPIO PA I/O direction byte 1 487 #define R32_PA_PIN (*((PUINT32V)0x400010A4)) // RO, GPIO PA input 488 #define R8_PA_PIN_0 (*((PUINT8V)0x400010A4)) // RO, GPIO PA input byte 0 489 #define R8_PA_PIN_1 (*((PUINT8V)0x400010A5)) // RO, GPIO PA input byte 1 490 #define R32_PA_OUT (*((PUINT32V)0x400010A8)) // RW, GPIO PA output 491 #define R8_PA_OUT_0 (*((PUINT8V)0x400010A8)) // RW, GPIO PA output byte 0 492 #define R8_PA_OUT_1 (*((PUINT8V)0x400010A9)) // RW, GPIO PA output byte 1 493 #define R32_PA_CLR (*((PUINT32V)0x400010AC)) // WZ, GPIO PA clear output: 0=keep, 1=clear 494 #define R8_PA_CLR_0 (*((PUINT8V)0x400010AC)) // WZ, GPIO PA clear output byte 0 495 #define R8_PA_CLR_1 (*((PUINT8V)0x400010AD)) // WZ, GPIO PA clear output byte 1 496 #define R32_PA_PU (*((PUINT32V)0x400010B0)) // RW, GPIO PA pullup resistance enable 497 #define R8_PA_PU_0 (*((PUINT8V)0x400010B0)) // RW, GPIO PA pullup resistance enable byte 0 498 #define R8_PA_PU_1 (*((PUINT8V)0x400010B1)) // RW, GPIO PA pullup resistance enable byte 1 499 #define R32_PA_PD_DRV (*((PUINT32V)0x400010B4)) // RW, PA pulldown for input or PA driving capability for output 500 #define R8_PA_PD_DRV_0 (*((PUINT8V)0x400010B4)) // RW, PA pulldown for input or PA driving capability for output byte 0 501 #define R8_PA_PD_DRV_1 (*((PUINT8V)0x400010B5)) // RW, PA pulldown for input or PA driving capability for output byte 1 502 503 /* GPIO PB register */ 504 #define R32_PB_DIR (*((PUINT32V)0x400010C0)) // RW, GPIO PB I/O direction: 0=in, 1=out 505 #define R8_PB_DIR_0 (*((PUINT8V)0x400010C0)) // RW, GPIO PB I/O direction byte 0 506 #define R8_PB_DIR_1 (*((PUINT8V)0x400010C1)) // RW, GPIO PB I/O direction byte 1 507 #define R8_PB_DIR_2 (*((PUINT8V)0x400010C2)) // RW, GPIO PB I/O direction byte 2 508 #define R32_PB_PIN (*((PUINT32V)0x400010C4)) // RO, GPIO PB input 509 #define R8_PB_PIN_0 (*((PUINT8V)0x400010C4)) // RO, GPIO PB input byte 0 510 #define R8_PB_PIN_1 (*((PUINT8V)0x400010C5)) // RO, GPIO PB input byte 1 511 #define R8_PB_PIN_2 (*((PUINT8V)0x400010C6)) // RO, GPIO PB input byte 2 512 #define R32_PB_OUT (*((PUINT32V)0x400010C8)) // RW, GPIO PB output 513 #define R8_PB_OUT_0 (*((PUINT8V)0x400010C8)) // RW, GPIO PB output byte 0 514 #define R8_PB_OUT_1 (*((PUINT8V)0x400010C9)) // RW, GPIO PB output byte 1 515 #define R8_PB_OUT_2 (*((PUINT8V)0x400010CA)) // RW, GPIO PB output byte 2 516 #define R32_PB_CLR (*((PUINT32V)0x400010CC)) // WZ, GPIO PB clear output: 0=keep, 1=clear 517 #define R8_PB_CLR_0 (*((PUINT8V)0x400010CC)) // WZ, GPIO PB clear output byte 0 518 #define R8_PB_CLR_1 (*((PUINT8V)0x400010CD)) // WZ, GPIO PB clear output byte 1 519 #define R8_PB_CLR_2 (*((PUINT8V)0x400010CE)) // WZ, GPIO PB clear output byte 2 520 #define R32_PB_PU (*((PUINT32V)0x400010D0)) // RW, GPIO PB pullup resistance enable 521 #define R8_PB_PU_0 (*((PUINT8V)0x400010D0)) // RW, GPIO PB pullup resistance enable byte 0 522 #define R8_PB_PU_1 (*((PUINT8V)0x400010D1)) // RW, GPIO PB pullup resistance enable byte 1 523 #define R8_PB_PU_2 (*((PUINT8V)0x400010D2)) // RW, GPIO PB pullup resistance enable byte 2 524 #define R32_PB_PD_DRV (*((PUINT32V)0x400010D4)) // RW, PB pulldown for input or PB driving capability for output 525 #define R8_PB_PD_DRV_0 (*((PUINT8V)0x400010D4)) // RW, PB pulldown for input or PB driving capability for output byte 0 526 #define R8_PB_PD_DRV_1 (*((PUINT8V)0x400010D5)) // RW, PB pulldown for input or PB driving capability for output byte 1 527 #define R8_PB_PD_DRV_2 (*((PUINT8V)0x400010D6)) // RW, PB pulldown for input or PB driving capability for output byte 2 528 529 /* GPIO register address offset and bit define */ 530 #define BA_PA ((PUINT8V)0x400010A0) // point GPIO PA base address 531 #define BA_PB ((PUINT8V)0x400010C0) // point GPIO PB base address 532 #define GPIO_DIR 0x00 533 #define GPIO_DIR_0 0x00 534 #define GPIO_DIR_1 0x01 535 #define GPIO_DIR_2 0x02 536 #define GPIO_PIN 0x04 537 #define GPIO_PIN_0 0x04 538 #define GPIO_PIN_1 0x05 539 #define GPIO_PIN_2 0x06 540 #define GPIO_OUT 0x08 541 #define GPIO_OUT_0 0x08 542 #define GPIO_OUT_1 0x09 543 #define GPIO_OUT_2 0x0A 544 #define GPIO_CLR 0x0C 545 #define GPIO_CLR_0 0x0C 546 #define GPIO_CLR_1 0x0D 547 #define GPIO_CLR_2 0x0E 548 #define GPIO_PU 0x10 549 #define GPIO_PU_0 0x10 550 #define GPIO_PU_1 0x11 551 #define GPIO_PU_2 0x12 552 #define GPIO_PD_DRV 0x14 553 #define GPIO_PD_DRV_0 0x14 554 #define GPIO_PD_DRV_1 0x15 555 #define GPIO_PD_DRV_2 0x16 556 557 /* GPIO alias name */ 558 #define bSCK1 (1<<0) // PA0 559 #define bPADDR (1<<0) // PA0 560 #define bLED0 (1<<0) // PA0 561 #define bCOM0 (1<<0) // PA0 562 #define bSDO (1<<1) // PA1 563 #define bMOSI1 bSDO 564 #define bPCS (1<<1) // PA1 565 #define bLED1 (1<<1) // PA1 566 #define bCOM1 (1<<1) // PA1 567 #define bTMR3 (1<<2) // PA2 568 #define bCAP3 bTMR3 569 #define bPWM3 bTMR3 570 #define bSDI (1<<2) // PA2 571 #define bMISO1 bSDI 572 #define bLED2 (1<<2) // PA2 573 #define bCOM2 (1<<2) // PA2 574 #define bTMR0 (1<<3) // PA3 575 #define bCAP0 bTMR0 576 #define bPWM0 bTMR0 577 #define bPINT (1<<3) // PA3 578 #define bLED3 (1<<3) // PA3 579 #define bCOM3 (1<<3) // PA3 580 #define bUBUS1 (1<<4) // PA4 581 #define bAIN0 (1<<4) // PA4 582 #define bRXD3 (1<<4) // PA4 583 #define bLEDC (1<<4) // PA4 584 #define bUCC1 (1<<5) // PA5 585 #define bAIN1 (1<<5) // PA5 586 #define bTXD3 (1<<5) // PA5 587 #define bUCC2 (1<<6) // PA6 588 #define bAIN2 (1<<6) // PA6 589 #define bRXD2 (1<<6) // PA6 590 #define bPWM4 (1<<6) // PA6 591 #define bTIN3 (1<<7) // PA7 592 #define bTXD2 (1<<7) // PA7 593 #define bPWM5 (1<<7) // PA7 594 #define bTIN4 (1<<8) // PA8 595 #define bRXD1 (1<<8) // PA8 596 #define bTIN5 (1<<9) // PA9 597 #define bTXD1 (1<<9) // PA9 598 #define bX32KI (1<<10) // PA10 599 #define bTMR1 (1<<10) // PA10 600 #define bCAP1 bTMR1 601 #define bPWM1 bTMR1 602 #define bX32KO (1<<11) // PA11 603 #define bTMR2 (1<<11) // PA11 604 #define bCAP2 bTMR2 605 #define bPWM2 bTMR2 606 #define bTIN2 (1<<12) // PA12 607 #define bSCS (1<<12) // PA12 608 #define bTIN1 (1<<13) // PA13 609 #define bSCK0 (1<<13) // PA13 610 #define bUBUS2 (1<<14) // PA14 611 #define bAIN3 (1<<14) // PA14 612 #define bMOSI (1<<14) // PA14 613 #define bTXD0_ (1<<14) // PA14 614 #define bTIN0 (1<<15) // PA15 615 #define bMISO (1<<15) // PA15 616 #define bRXD0_ (1<<15) // PA15 617 #define bCTS (1<<0) // PB0 618 #define bPWM6 (1<<0) // PB0 619 #define bSEG0 (1<<0) // PB0 620 #define bDSR (1<<1) // PB1 621 #define bPWM7 (1<<1) // PB1 622 #define bSEG1 (1<<1) // PB1 623 #define bRI (1<<2) // PB2 624 #define bPWM8 (1<<2) // PB2 625 #define bSEG2 (1<<2) // PB2 626 #define bDCD (1<<3) // PB3 627 #define bPWM9 (1<<3) // PB3 628 #define bSEG3 (1<<3) // PB3 629 #define bRXD0 (1<<4) // PB4 630 #define bSEG4 (1<<4) // PB4 631 #define bDTR (1<<5) // PB5 632 #define bSEG5 (1<<5) // PB5 633 #define bRTS (1<<6) // PB6 634 #define bSEG6 (1<<6) // PB6 635 #define bTXD0 (1<<7) // PB7 636 #define bSEG7 (1<<7) // PB7 637 #define bPBUS (0xFF<<0) // PB0~PB7 638 #define bTIN8 (1<<8) // PB8 639 #define bRXD1_ (1<<8) // PB8 640 #define bPRD (1<<8) // PB8 641 #define bSEG8 (1<<8) // PB8 642 #define bTIN9 (1<<9) // PB9 643 #define bTXD1_ (1<<9) // PB9 644 #define bPWR (1<<9) // PB9 645 #define bSEG9 (1<<9) // PB9 646 #define bUDM (1<<10) // PB10 647 #define bTMR1_ (1<<10) // PB10 648 #define bCAP1_ bTMR1_ 649 #define bPWM1_ bTMR1_ 650 #define bSEG10 (1<<10) // PB10 651 #define bUDP (1<<11) // PB11 652 #define bTMR2_ (1<<11) // PB11 653 #define bCAP2_ bTMR2_ 654 #define bPWM2_ bTMR2_ 655 #define bSEG11 (1<<11) // PB11 656 #define bETM (1<<12) // PB12 657 #define bSCS_ (1<<12) // PB12 658 #define bSEG12 (1<<12) // PB12 659 #define bETP (1<<13) // PB13 660 #define bSCK0_ (1<<13) // PB13 661 #define bSEG13 (1<<13) // PB13 662 #define bERM (1<<14) // PB14 663 #define bMOSI_ (1<<14) // PB14 664 #define bPWM10 (1<<14) // PB14 665 #define bSEG14 (1<<14) // PB14 666 #define bERP (1<<15) // PB15 667 #define bMISO_ (1<<15) // PB15 668 #define bSEG15 (1<<15) // PB15 669 #define bTIN6 (1<<16) // PB16 670 #define bTIO (1<<16) // PB16 671 #define bSEG16 (1<<16) // PB16 672 #define bTIN7 (1<<17) // PB17 673 #define bTCK (1<<17) // PB17 674 #define bSEG17 (1<<17) // PB17 675 #define bTMR3_ (1<<18) // PB18 676 #define bCAP3_ bTMR3_ 677 #define bPWM3_ bTMR3_ 678 #define bSEG18 (1<<18) // PB18 679 #define bTMR0_ (1<<19) // PB19 680 #define bCAP0_ bTMR0_ 681 #define bPWM0_ bTMR0_ 682 #define bSEG19 (1<<19) // PB19 683 #define bRXD3_ (1<<20) // PB20 684 #define bSEG20 (1<<20) // PB20 685 #define bTXD3_ (1<<21) // PB21 686 #define bSEG21 (1<<21) // PB21 687 #define bRXD2_ (1<<22) // PB22 688 #define bSEG22 (1<<22) // PB22 689 #define bRST (1<<23) // PB23 690 #define bTXD2_ (1<<23) // PB23 691 #define bPWM11 (1<<23) // PB23 692 #define bSEG23 (1<<23) // PB23 693 694 /* Timer0 register */ 695 #define R32_TMR0_CONTROL (*((PUINT32V)0x40002000)) // RW, TMR0 control 696 #define R8_TMR0_CTRL_MOD (*((PUINT8V)0x40002000)) // RW, TMR0 mode control 697 #define R8_TMR0_INTER_EN (*((PUINT8V)0x40002002)) // RW, TMR0 interrupt enable 698 #define R32_TMR0_STATUS (*((PUINT32V)0x40002004)) // RW, TMR0 status 699 #define R8_TMR0_INT_FLAG (*((PUINT8V)0x40002006)) // RW1, TMR0 interrupt flag 700 #define R8_TMR0_FIFO_COUNT (*((PUINT8V)0x40002007)) // RO, TMR0 FIFO count status 701 #define R32_TMR0_COUNT (*((PUINT32V)0x40002008)) // RO, TMR0 current count 702 #define R16_TMR0_COUNT (*((PUINT16V)0x40002008)) // RO, TMR0 current count 703 #define R8_TMR0_COUNT (*((PUINT8V)0x40002008)) // RO, TMR0 current count 704 #define R32_TMR0_CNT_END (*((PUINT32V)0x4000200C)) // RW, TMR0 end count value, only low 26 bit 705 #define R32_TMR0_FIFO (*((PUINT32V)0x40002010)) // RO/WO, TMR0 FIFO register, only low 26 bit 706 #define R16_TMR0_FIFO (*((PUINT16V)0x40002010)) // RO/WO, TMR0 FIFO register 707 #define R8_TMR0_FIFO (*((PUINT8V)0x40002010)) // RO/WO, TMR0 FIFO register 708 709 /* Timer1 register */ 710 #define R32_TMR1_CONTROL (*((PUINT32V)0x40002400)) // RW, TMR1 control 711 #define R8_TMR1_CTRL_MOD (*((PUINT8V)0x40002400)) // RW, TMR1 mode control 712 #define R8_TMR1_CTRL_DMA (*((PUINT8V)0x40002401)) // RW, TMR1 DMA control 713 #define R8_TMR1_INTER_EN (*((PUINT8V)0x40002402)) // RW, TMR1 interrupt enable 714 #define R32_TMR1_STATUS (*((PUINT32V)0x40002404)) // RW, TMR1 status 715 #define R8_TMR1_INT_FLAG (*((PUINT8V)0x40002406)) // RW1, TMR1 interrupt flag 716 #define R8_TMR1_FIFO_COUNT (*((PUINT8V)0x40002407)) // RO, TMR1 FIFO count status 717 #define R32_TMR1_COUNT (*((PUINT32V)0x40002408)) // RO, TMR1 current count 718 #define R16_TMR1_COUNT (*((PUINT16V)0x40002408)) // RO, TMR1 current count 719 #define R8_TMR1_COUNT (*((PUINT8V)0x40002408)) // RO, TMR1 current count 720 #define R32_TMR1_CNT_END (*((PUINT32V)0x4000240C)) // RW, TMR1 end count value, only low 26 bit 721 #define R32_TMR1_FIFO (*((PUINT32V)0x40002410)) // RO/WO, TMR1 FIFO register, only low 26 bit 722 #define R16_TMR1_FIFO (*((PUINT16V)0x40002410)) // RO/WO, TMR1 FIFO register 723 #define R8_TMR1_FIFO (*((PUINT8V)0x40002410)) // RO/WO, TMR1 FIFO register 724 #define R32_TMR1_DMA_NOW (*((PUINT32V)0x40002414)) // RW, TMR1 DMA current address 725 #define R16_TMR1_DMA_NOW (*((PUINT16V)0x40002414)) // RW, TMR1 DMA current address 726 #define R32_TMR1_DMA_BEG (*((PUINT32V)0x40002418)) // RW, TMR1 DMA begin address 727 #define R16_TMR1_DMA_BEG (*((PUINT16V)0x40002418)) // RW, TMR1 DMA begin address 728 #define R32_TMR1_DMA_END (*((PUINT32V)0x4000241C)) // RW, TMR1 DMA end address 729 #define R16_TMR1_DMA_END (*((PUINT16V)0x4000241C)) // RW, TMR1 DMA end address 730 731 /* Timer2 register */ 732 #define R32_TMR2_CONTROL (*((PUINT32V)0x40002800)) // RW, TMR2 control 733 #define R8_TMR2_CTRL_MOD (*((PUINT8V)0x40002800)) // RW, TMR2 mode control 734 #define R8_TMR2_CTRL_DMA (*((PUINT8V)0x40002801)) // RW, TMR2 DMA control 735 #define R8_TMR2_INTER_EN (*((PUINT8V)0x40002802)) // RW, TMR2 interrupt enable 736 #define R32_TMR2_STATUS (*((PUINT32V)0x40002804)) // RW, TMR2 status 737 #define R8_TMR2_INT_FLAG (*((PUINT8V)0x40002806)) // RW1, TMR2 interrupt flag 738 #define R8_TMR2_FIFO_COUNT (*((PUINT8V)0x40002807)) // RO, TMR2 FIFO count status 739 #define R32_TMR2_COUNT (*((PUINT32V)0x40002808)) // RO, TMR2 current count 740 #define R16_TMR2_COUNT (*((PUINT16V)0x40002808)) // RO, TMR2 current count 741 #define R8_TMR2_COUNT (*((PUINT8V)0x40002808)) // RO, TMR2 current count 742 #define R32_TMR2_CNT_END (*((PUINT32V)0x4000280C)) // RW, TMR2 end count value, only low 26 bit 743 #define R32_TMR2_FIFO (*((PUINT32V)0x40002810)) // RO/WO, TMR2 FIFO register, only low 26 bit 744 #define R16_TMR2_FIFO (*((PUINT16V)0x40002810)) // RO/WO, TMR2 FIFO register 745 #define R8_TMR2_FIFO (*((PUINT8V)0x40002810)) // RO/WO, TMR2 FIFO register 746 #define R32_TMR2_DMA_NOW (*((PUINT32V)0x40002814)) // RW, TMR2 DMA current address 747 #define R16_TMR2_DMA_NOW (*((PUINT16V)0x40002814)) // RW, TMR2 DMA current address 748 #define R32_TMR2_DMA_BEG (*((PUINT32V)0x40002818)) // RW, TMR2 DMA begin address 749 #define R16_TMR2_DMA_BEG (*((PUINT16V)0x40002818)) // RW, TMR2 DMA begin address 750 #define R32_TMR2_DMA_END (*((PUINT32V)0x4000281C)) // RW, TMR2 DMA end address 751 #define R16_TMR2_DMA_END (*((PUINT16V)0x4000281C)) // RW, TMR2 DMA end address 752 753 /* Timer3 register */ 754 #define R32_TMR3_CONTROL (*((PUINT32V)0x40002C00)) // RW, TMR3 control 755 #define R8_TMR3_CTRL_MOD (*((PUINT8V)0x40002C00)) // RW, TMR3 mode control 756 #define R8_TMR3_INTER_EN (*((PUINT8V)0x40002C02)) // RW, TMR3 interrupt enable 757 #define R32_TMR3_STATUS (*((PUINT32V)0x40002C04)) // RW, TMR3 status 758 #define R8_TMR3_INT_FLAG (*((PUINT8V)0x40002C06)) // RW1, TMR3 interrupt flag 759 #define R8_TMR3_FIFO_COUNT (*((PUINT8V)0x40002C07)) // RO, TMR3 FIFO count status 760 #define R32_TMR3_COUNT (*((PUINT32V)0x40002C08)) // RO, TMR3 current count 761 #define R16_TMR3_COUNT (*((PUINT16V)0x40002C08)) // RO, TMR3 current count 762 #define R8_TMR3_COUNT (*((PUINT8V)0x40002C08)) // RO, TMR3 current count 763 #define R32_TMR3_CNT_END (*((PUINT32V)0x40002C0C)) // RW, TMR3 end count value, only low 26 bit 764 #define R32_TMR3_FIFO (*((PUINT32V)0x40002C10)) // RO/WO, TMR3 FIFO register, only low 26 bit 765 #define R16_TMR3_FIFO (*((PUINT16V)0x40002C10)) // RO/WO, TMR3 FIFO register 766 #define R8_TMR3_FIFO (*((PUINT8V)0x40002C10)) // RO/WO, TMR3 FIFO register 767 768 /* Timer register address offset and bit define */ 769 #define TMR_FIFO_SIZE 8 // timer FIFO size (depth) 770 #define BA_TMR0 ((PUINT8V)0x40002000) // point TMR0 base address 771 #define BA_TMR1 ((PUINT8V)0x40002400) // point TMR1 base address 772 #define BA_TMR2 ((PUINT8V)0x40002800) // point TMR2 base address 773 #define BA_TMR3 ((PUINT8V)0x40002C00) // point TMR3 base address 774 #define TMR_CTRL_MOD 0 775 #define RB_TMR_MODE_IN 0x01 // RW, timer in mode: 0=timer/PWM, 1=capture/count 776 #define RB_TMR_ALL_CLEAR 0x02 // RW, force clear timer FIFO and count 777 #define RB_TMR_COUNT_EN 0x04 // RW, timer count enable 778 #define RB_TMR_OUT_EN 0x08 // RW, timer output enable 779 #define RB_TMR_OUT_POLAR 0x10 // RW, timer PWM output polarity: 0=default low and high action, 1=default high and low action 780 #define RB_TMR_CAP_COUNT 0x10 // RW, count sub-mode if RB_TMR_MODE_IN=1: 0=capture, 1=count 781 #define RB_TMR_PWM_REPEAT 0xC0 // RW, timer PWM repeat mode: 00=1, 01=4, 10=8, 11-16 782 #define RB_TMR_CAP_EDGE 0xC0 // RW, timer capture edge mode: 00=disable, 01=edge change, 10=fall to fall, 11-rise to rise 783 #define TMR_CTRL_DMA 1 784 #define RB_TMR_DMA_ENABLE 0x01 // RW, timer1/2 DMA enable 785 #define RB_TMR_DMA_LOOP 0x04 // RW, timer1/2 DMA address loop enable 786 #define TMR_INTER_EN 2 787 #define RB_TMR_IE_CYC_END 0x01 // RW, enable interrupt for timer capture count timeout or PWM cycle end 788 #define RB_TMR_IE_DATA_ACT 0x02 // RW, enable interrupt for timer capture input action or PWM trigger 789 #define RB_TMR_IE_FIFO_HF 0x04 // RW, enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo <=3) 790 #define RB_TMR_IE_DMA_END 0x08 // RW, enable interrupt for timer1/2 DMA completion 791 #define RB_TMR_IE_FIFO_OV 0x10 // RW, enable interrupt for timer FIFO overflow 792 #define TMR_INT_FLAG 6 793 #define RB_TMR_IF_CYC_END 0x01 // RW1, interrupt flag for timer capture count timeout or PWM cycle end 794 #define RB_TMR_IF_DATA_ACT 0x02 // RW1, interrupt flag for timer capture input action or PWM trigger 795 #define RB_TMR_IF_FIFO_HF 0x04 // RW1, interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo <=3) 796 #define RB_TMR_IF_DMA_END 0x08 // RW1, interrupt flag for timer1/2 DMA completion 797 #define RB_TMR_IF_FIFO_OV 0x10 // RW1, interrupt flag for timer FIFO overflow 798 #define TMR_FIFO_COUNT 7 799 #define TMR_COUNT 0x08 800 #define TMR_CNT_END 0x0C 801 #define TMR_FIFO 0x10 802 #define TMR_DMA_NOW 0x14 803 #define TMR_DMA_BEG 0x18 804 #define TMR_DMA_END 0x1C 805 806 /* UART0 register */ 807 #define R32_UART0_CTRL (*((PUINT32V)0x40003000)) // RW, UART0 control 808 #define R8_UART0_MCR (*((PUINT8V)0x40003000)) // RW, UART0 modem control 809 #define R8_UART0_IER (*((PUINT8V)0x40003001)) // RW, UART0 interrupt enable 810 #define R8_UART0_FCR (*((PUINT8V)0x40003002)) // RW, UART0 FIFO control 811 #define R8_UART0_LCR (*((PUINT8V)0x40003003)) // RW, UART0 line control 812 #define R32_UART0_STAT (*((PUINT32V)0x40003004)) // RO, UART0 status 813 #define R8_UART0_IIR (*((PUINT8V)0x40003004)) // RO, UART0 interrupt identification 814 #define R8_UART0_LSR (*((PUINT8V)0x40003005)) // RO, UART0 line status 815 #define R8_UART0_MSR (*((PUINT8V)0x40003006)) // RO, UART0 modem status 816 #define R32_UART0_FIFO (*((PUINT32V)0x40003008)) // RW, UART0 data or FIFO port 817 #define R8_UART0_RBR (*((PUINT8V)0x40003008)) // RO, UART0 receiver buffer, receiving byte 818 #define R8_UART0_THR (*((PUINT8V)0x40003008)) // WO, UART0 transmitter holding, transmittal byte 819 #define R8_UART0_RFC (*((PUINT8V)0x4000300A)) // RO, UART0 receiver FIFO count 820 #define R8_UART0_TFC (*((PUINT8V)0x4000300B)) // RO, UART0 transmitter FIFO count 821 #define R32_UART0_SETUP (*((PUINT32V)0x4000300C)) // RW, UART0 setup 822 #define R16_UART0_DL (*((PUINT16V)0x4000300C)) // RW, UART0 divisor latch 823 #define R8_UART0_DLL (*((PUINT8V)0x4000300C)) // RW, UART0 divisor latch LSB byte 824 #define R8_UART0_DLM (*((PUINT8V)0x4000300D)) // RW, UART0 divisor latch MSB byte 825 #define R8_UART0_DIV (*((PUINT8V)0x4000300E)) // RW, UART0 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 826 #define R8_UART0_ADR (*((PUINT8V)0x4000300F)) // RW, UART0 slave address: 0xFF=disable, other=enable 827 828 /* UART1 register */ 829 #define R32_UART1_CTRL (*((PUINT32V)0x40003400)) // RW, UART1 control 830 #define R8_UART1_MCR (*((PUINT8V)0x40003400)) // RW, UART1 modem control 831 #define R8_UART1_IER (*((PUINT8V)0x40003401)) // RW, UART1 interrupt enable 832 #define R8_UART1_FCR (*((PUINT8V)0x40003402)) // RW, UART1 FIFO control 833 #define R8_UART1_LCR (*((PUINT8V)0x40003403)) // RW, UART1 line control 834 #define R32_UART1_STAT (*((PUINT32V)0x40003404)) // RO, UART1 status 835 #define R8_UART1_IIR (*((PUINT8V)0x40003404)) // RO, UART1 interrupt identification 836 #define R8_UART1_LSR (*((PUINT8V)0x40003405)) // RO, UART1 line status 837 #define R32_UART1_FIFO (*((PUINT32V)0x40003408)) // RW, UART1 data or FIFO port 838 #define R8_UART1_RBR (*((PUINT8V)0x40003408)) // RO, UART1 receiver buffer, receiving byte 839 #define R8_UART1_THR (*((PUINT8V)0x40003408)) // WO, UART1 transmitter holding, transmittal byte 840 #define R8_UART1_RFC (*((PUINT8V)0x4000340A)) // RO, UART1 receiver FIFO count 841 #define R8_UART1_TFC (*((PUINT8V)0x4000340B)) // RO, UART1 transmitter FIFO count 842 #define R32_UART1_SETUP (*((PUINT32V)0x4000340C)) // RW, UART1 setup 843 #define R16_UART1_DL (*((PUINT16V)0x4000340C)) // RW, UART1 divisor latch 844 #define R8_UART1_DLL (*((PUINT8V)0x4000340C)) // RW, UART1 divisor latch LSB byte 845 #define R8_UART1_DLM (*((PUINT8V)0x4000340D)) // RW, UART1 divisor latch MSB byte 846 #define R8_UART1_DIV (*((PUINT8V)0x4000340E)) // RW, UART1 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 847 848 /* UART2 register */ 849 #define R32_UART2_CTRL (*((PUINT32V)0x40003800)) // RW, UART2 control 850 #define R8_UART2_MCR (*((PUINT8V)0x40003800)) // RW, UART2 modem control 851 #define R8_UART2_IER (*((PUINT8V)0x40003801)) // RW, UART2 interrupt enable 852 #define R8_UART2_FCR (*((PUINT8V)0x40003802)) // RW, UART2 FIFO control 853 #define R8_UART2_LCR (*((PUINT8V)0x40003803)) // RW, UART2 line control 854 #define R32_UART2_STAT (*((PUINT32V)0x40003804)) // RO, UART2 status 855 #define R8_UART2_IIR (*((PUINT8V)0x40003804)) // RO, UART2 interrupt identification 856 #define R8_UART2_LSR (*((PUINT8V)0x40003805)) // RO, UART2 line status 857 #define R32_UART2_FIFO (*((PUINT32V)0x40003808)) // RW, UART2 data or FIFO port 858 #define R8_UART2_RBR (*((PUINT8V)0x40003808)) // RO, UART2 receiver buffer, receiving byte 859 #define R8_UART2_THR (*((PUINT8V)0x40003808)) // WO, UART2 transmitter holding, transmittal byte 860 #define R8_UART2_RFC (*((PUINT8V)0x4000380A)) // RO, UART2 receiver FIFO count 861 #define R8_UART2_TFC (*((PUINT8V)0x4000380B)) // RO, UART2 transmitter FIFO count 862 #define R32_UART2_SETUP (*((PUINT32V)0x4000380C)) // RW, UART2 setup 863 #define R16_UART2_DL (*((PUINT16V)0x4000380C)) // RW, UART2 divisor latch 864 #define R8_UART2_DLL (*((PUINT8V)0x4000380C)) // RW, UART2 divisor latch LSB byte 865 #define R8_UART2_DLM (*((PUINT8V)0x4000380D)) // RW, UART2 divisor latch MSB byte 866 #define R8_UART2_DIV (*((PUINT8V)0x4000380E)) // RW, UART2 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 867 868 /* UART3 register */ 869 #define R32_UART3_CTRL (*((PUINT32V)0x40003C00)) // RW, UART3 control 870 #define R8_UART3_MCR (*((PUINT8V)0x40003C00)) // RW, UART3 modem control 871 #define R8_UART3_IER (*((PUINT8V)0x40003C01)) // RW, UART3 interrupt enable 872 #define R8_UART3_FCR (*((PUINT8V)0x40003C02)) // RW, UART3 FIFO control 873 #define R8_UART3_LCR (*((PUINT8V)0x40003C03)) // RW, UART3 line control 874 #define R32_UART3_STAT (*((PUINT32V)0x40003C04)) // RO, UART3 status 875 #define R8_UART3_IIR (*((PUINT8V)0x40003C04)) // RO, UART3 interrupt identification 876 #define R8_UART3_LSR (*((PUINT8V)0x40003C05)) // RO, UART3 line status 877 #define R32_UART3_FIFO (*((PUINT32V)0x40003C08)) // RW, UART3 data or FIFO port 878 #define R8_UART3_RBR (*((PUINT8V)0x40003C08)) // RO, UART3 receiver buffer, receiving byte 879 #define R8_UART3_THR (*((PUINT8V)0x40003C08)) // WO, UART3 transmitter holding, transmittal byte 880 #define R8_UART3_RFC (*((PUINT8V)0x40003C0A)) // RO, UART3 receiver FIFO count 881 #define R8_UART3_TFC (*((PUINT8V)0x40003C0B)) // RO, UART3 transmitter FIFO count 882 #define R32_UART3_SETUP (*((PUINT32V)0x40003C0C)) // RW, UART3 setup 883 #define R16_UART3_DL (*((PUINT16V)0x40003C0C)) // RW, UART3 divisor latch 884 #define R8_UART3_DLL (*((PUINT8V)0x40003C0C)) // RW, UART3 divisor latch LSB byte 885 #define R8_UART3_DLM (*((PUINT8V)0x40003C0D)) // RW, UART3 divisor latch MSB byte 886 #define R8_UART3_DIV (*((PUINT8V)0x40003C0E)) // RW, UART3 pre-divisor latch byte, only low 7 bit, from 1 to 0/128 887 888 /* UART register address offset and bit define */ 889 #define UART_FIFO_SIZE 8 // UART FIFO size (depth) 890 #define UART_RECV_RDY_SZ 7 // the max FIFO trigger level for UART receiver data available 891 #define BA_UART0 ((PUINT8V)0x40003000) // point UART0 base address 892 #define BA_UART1 ((PUINT8V)0x40003400) // point UART1 base address 893 #define BA_UART2 ((PUINT8V)0x40003800) // point UART2 base address 894 #define BA_UART3 ((PUINT8V)0x40003C00) // point UART3 base address 895 #define UART_MCR 0 896 #define RB_MCR_DTR 0x01 // RW, UART0 control DTR 897 #define RB_MCR_RTS 0x02 // RW, UART0 control RTS 898 #define RB_MCR_OUT1 0x04 // RW, UART0 control OUT1 899 #define RB_MCR_OUT2 0x08 // RW, UART control OUT2 900 #define RB_MCR_INT_OE 0x08 // RW, UART interrupt output enable 901 #define RB_MCR_LOOP 0x10 // RW, UART0 enable local loop back 902 #define RB_MCR_AU_FLOW_EN 0x20 // RW, UART0 enable autoflow control 903 #define RB_MCR_TNOW 0x40 // RW, UART0 enable TNOW output on DTR pin 904 #define RB_MCR_HALF 0x80 // RW, UART0 enable half-duplex 905 #define UART_IER 1 906 #define RB_IER_RECV_RDY 0x01 // RW, UART interrupt enable for receiver data ready 907 #define RB_IER_THR_EMPTY 0x02 // RW, UART interrupt enable for THR empty 908 #define RB_IER_LINE_STAT 0x04 // RW, UART interrupt enable for receiver line status 909 #define RB_IER_MODEM_CHG 0x08 // RW, UART0 interrupt enable for modem status change 910 #define RB_IER_DTR_EN 0x10 // RW, UART0 DTR/TNOW output pin enable 911 #define RB_IER_RTS_EN 0x20 // RW, UART0 RTS output pin enable 912 #define RB_IER_TXD_EN 0x40 // RW, UART TXD pin enable 913 #define RB_IER_RESET 0x80 // WZ, UART software reset control, high action, auto clear 914 #define UART_FCR 2 915 #define RB_FCR_FIFO_EN 0x01 // RW, UART FIFO enable 916 #define RB_FCR_RX_FIFO_CLR 0x02 // WZ, clear UART receiver FIFO, high action, auto clear 917 #define RB_FCR_TX_FIFO_CLR 0x04 // WZ, clear UART transmitter FIFO, high action, auto clear 918 #define RB_FCR_FIFO_TRIG 0xC0 // RW, UART receiver FIFO trigger level: 00-1byte, 01-2bytes, 10-4bytes, 11-7bytes 919 #define UART_LCR 3 920 #define RB_LCR_WORD_SZ 0x03 // RW, UART word bit length: 00-5bit, 01-6bit, 10-7bit, 11-8bit 921 #define RB_LCR_STOP_BIT 0x04 // RW, UART stop bit length: 0-1bit, 1-2bit 922 #define RB_LCR_PAR_EN 0x08 // RW, UART parity enable 923 #define RB_LCR_PAR_MOD 0x30 // RW, UART parity mode: 00-odd, 01-even, 10-mark, 11-space 924 #define RB_LCR_BREAK_EN 0x40 // RW, UART break control enable 925 #define RB_LCR_DLAB 0x80 // RW, UART reserved bit 926 #define RB_LCR_GP_BIT 0x80 // RW, UART general purpose bit 927 #define UART_IIR 4 928 #define RB_IIR_NO_INT 0x01 // RO, UART no interrupt flag: 0=interrupt action, 1=no interrupt 929 #define RB_IIR_INT_MASK 0x0F // RO, UART interrupt flag bit mask 930 #define RB_IIR_FIFO_ID 0xC0 // RO, UART FIFO enabled flag 931 #define UART_LSR 5 932 #define RB_LSR_DATA_RDY 0x01 // RO, UART receiver fifo data ready status 933 #define RB_LSR_OVER_ERR 0x02 // RZ, UART receiver overrun error 934 #define RB_LSR_PAR_ERR 0x04 // RZ, UART receiver parity error 935 #define RB_LSR_FRAME_ERR 0x08 // RZ, UART receiver frame error 936 #define RB_LSR_BREAK_ERR 0x10 // RZ, UART receiver break error 937 #define RB_LSR_TX_FIFO_EMP 0x20 // RO, UART transmitter fifo empty status 938 #define RB_LSR_TX_ALL_EMP 0x40 // RO, UART transmitter all empty status 939 #define RB_LSR_ERR_RX_FIFO 0x80 // RO, indicate error in UART receiver fifo 940 #define UART_MSR 6 941 #define RB_MSR_CTS_CHG 0x01 // RZ, UART0 CTS changed status, high action 942 #define RB_MSR_DSR_CHG 0x02 // RZ, UART0 DSR changed status, high action 943 #define RB_MSR_RI_CHG 0x04 // RZ, UART0 RI changed status, high action 944 #define RB_MSR_DCD_CHG 0x08 // RZ, UART0 DCD changed status, high action 945 #define RB_MSR_CTS 0x10 // RO, UART0 CTS action status 946 #define RB_MSR_DSR 0x20 // RO, UART0 DSR action status 947 #define RB_MSR_RI 0x40 // RO, UART0 RI action status 948 #define RB_MSR_DCD 0x80 // RO, UART0 DCD action status 949 #define UART_RBR 8 950 #define UART_THR 8 951 #define UART_RFC 0x0A 952 #define UART_TFC 0x0B 953 #define UART_DLL 0x0C 954 #define UART_DLM 0x0D 955 #define UART_DIV 0x0E 956 #define UART_ADR 0x0F 957 958 /* UART interrupt identification values for IIR bits 3:0 */ 959 #define UART_II_SLV_ADDR 0x0E // RO, UART0 slave address match 960 #define UART_II_LINE_STAT 0x06 // RO, UART interrupt by receiver line status 961 #define UART_II_RECV_RDY 0x04 // RO, UART interrupt by receiver data available 962 #define UART_II_RECV_TOUT 0x0C // RO, UART interrupt by receiver fifo timeout 963 #define UART_II_THR_EMPTY 0x02 // RO, UART interrupt by THR empty 964 #define UART_II_MODEM_CHG 0x00 // RO, UART0 interrupt by modem status change 965 #define UART_II_NO_INTER 0x01 // RO, no UART interrupt is pending 966 967 /* SPI0 register */ 968 #define R32_SPI0_CONTROL (*((PUINT32V)0x40004000)) // RW, SPI0 control 969 #define R8_SPI0_CTRL_MOD (*((PUINT8V)0x40004000)) // RW, SPI0 mode control 970 #define R8_SPI0_CTRL_CFG (*((PUINT8V)0x40004001)) // RW, SPI0 configuration control 971 #define R8_SPI0_INTER_EN (*((PUINT8V)0x40004002)) // RW, SPI0 interrupt enable 972 #define R8_SPI0_CLOCK_DIV (*((PUINT8V)0x40004003)) // RW, SPI0 master clock divisor 973 #define R8_SPI0_SLAVE_PRE (*((PUINT8V)0x40004003)) // RW, SPI0 slave preset value 974 #define R32_SPI0_STATUS (*((PUINT32V)0x40004004)) // RW, SPI0 status 975 #define R8_SPI0_BUFFER (*((PUINT8V)0x40004004)) // RO, SPI0 data buffer 976 #define R8_SPI0_RUN_FLAG (*((PUINT8V)0x40004005)) // RO, SPI0 work flag 977 #define R8_SPI0_INT_FLAG (*((PUINT8V)0x40004006)) // RW1, SPI0 interrupt flag 978 #define R8_SPI0_FIFO_COUNT (*((PUINT8V)0x40004007)) // RO, SPI0 FIFO count status 979 #define R32_SPI0_TOTAL_CNT (*((PUINT32V)0x4000400C)) // RW, SPI0 total byte count, only low 12 bit 980 #define R16_SPI0_TOTAL_CNT (*((PUINT16V)0x4000400C)) // RW, SPI0 total byte count, only low 12 bit 981 #define R32_SPI0_FIFO (*((PUINT32V)0x40004010)) // RW, SPI0 FIFO register 982 #define R8_SPI0_FIFO (*((PUINT8V)0x40004010)) // RO/WO, SPI0 FIFO register 983 #define R8_SPI0_FIFO_COUNT1 (*((PUINT8V)0x40004013)) // RO, SPI0 FIFO count status 984 #define R32_SPI0_DMA_NOW (*((PUINT32V)0x40004014)) // RW, SPI0 DMA current address 985 #define R16_SPI0_DMA_NOW (*((PUINT16V)0x40004014)) // RW, SPI0 DMA current address 986 #define R32_SPI0_DMA_BEG (*((PUINT32V)0x40004018)) // RW, SPI0 DMA begin address 987 #define R16_SPI0_DMA_BEG (*((PUINT16V)0x40004018)) // RW, SPI0 DMA begin address 988 #define R32_SPI0_DMA_END (*((PUINT32V)0x4000401C)) // RW, SPI0 DMA end address 989 #define R16_SPI0_DMA_END (*((PUINT16V)0x4000401C)) // RW, SPI0 DMA end address 990 991 /* SPI1 register */ 992 #define R32_SPI1_CONTROL (*((PUINT32V)0x40004400)) // RW, SPI1 control 993 #define R8_SPI1_CTRL_MOD (*((PUINT8V)0x40004400)) // RW, SPI1 mode control 994 #define R8_SPI1_CTRL_CFG (*((PUINT8V)0x40004401)) // RW, SPI1 configuration control 995 #define R8_SPI1_INTER_EN (*((PUINT8V)0x40004402)) // RW, SPI1 interrupt enable 996 #define R8_SPI1_CLOCK_DIV (*((PUINT8V)0x40004403)) // RW, SPI1 master clock divisor 997 #define R32_SPI1_STATUS (*((PUINT32V)0x40004404)) // RW, SPI1 status 998 #define R8_SPI1_BUFFER (*((PUINT8V)0x40004404)) // RO, SPI1 data buffer 999 #define R8_SPI1_RUN_FLAG (*((PUINT8V)0x40004405)) // RO, SPI1 work flag 1000 #define R8_SPI1_INT_FLAG (*((PUINT8V)0x40004406)) // RW1, SPI1 interrupt flag 1001 #define R8_SPI1_FIFO_COUNT (*((PUINT8V)0x40004407)) // RO, SPI1 FIFO count status 1002 #define R32_SPI1_TOTAL_CNT (*((PUINT32V)0x4000440C)) // RW, SPI1 total byte count, only low 12 bit 1003 #define R16_SPI1_TOTAL_CNT (*((PUINT16V)0x4000440C)) // RW, SPI1 total byte count, only low 12 bit 1004 #define R32_SPI1_FIFO (*((PUINT32V)0x40004410)) // RW, SPI1 FIFO register 1005 #define R8_SPI1_FIFO (*((PUINT8V)0x40004410)) // RO/WO, SPI1 FIFO register 1006 #define R8_SPI1_FIFO_COUNT1 (*((PUINT8V)0x40004413)) // RO, SPI1 FIFO count status 1007 1008 /* SPI register address offset and bit define */ 1009 #define SPI_FIFO_SIZE 8 // SPI FIFO size (depth) 1010 #define BA_SPI0 ((PUINT8V)0x40004000) // point SPI0 base address 1011 #define BA_SPI1 ((PUINT8V)0x40004400) // point SPI1 base address 1012 #define SPI_CTRL_MOD 0 1013 #define RB_SPI_MODE_SLAVE 0x01 // RW, SPI0 slave mode: 0=master/host, 1=slave/device 1014 #define RB_SPI_ALL_CLEAR 0x02 // RW, force clear SPI FIFO and count 1015 #define RB_SPI_2WIRE_MOD 0x04 // RW, SPI0 enable 2 wire mode for slave: 0=3wire(SCK0,MOSI,MISO), 1=2wire(SCK0,MISO=MXSX) 1016 #define RB_SPI_MST_SCK_MOD 0x08 // RW, SPI master clock mode: 0=mode 0, 1=mode 3 1017 #define RB_SPI_SLV_CMD_MOD 0x08 // RW, SPI0 slave command mode: 0=byte stream, 1=first byte command 1018 #define RB_SPI_FIFO_DIR 0x10 // RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode) 1019 #define RB_SPI_SCK_OE 0x20 // RW, SPI SCK output enable 1020 #define RB_SPI_MOSI_OE 0x40 // RW, SPI MOSI output enable 1021 #define RB_SPI1_SDO_OE 0x40 // RW, SPI1 SDO output enable 1022 #define RB_SPI_MISO_OE 0x80 // RW, SPI MISO output enable 1023 #define RB_SPI1_SDI_OE 0x80 // RW, SPI1 SDI output enable, SPI1 enable 2 wire mode: 0=3wire(SCK1,SDO,SDI), 1=2wire(SCK1,SDI=SDX) 1024 #define SPI_CTRL_CFG 1 1025 #define RB_SPI_DMA_ENABLE 0x01 // RW, SPI0 DMA enable 1026 #define RB_SPI_DMA_LOOP 0x04 // RW, SPI0 DMA address loop enable 1027 #define RB_SPI_AUTO_IF 0x10 // RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag 1028 #define RB_SPI_BIT_ORDER 0x20 // RW, SPI bit data order: 0=MSB first, 1=LSB first 1029 #define RB_SPI_MST_DLY_EN 0x40 // RW, SPI master input delay enable 1030 #define SPI_INTER_EN 2 1031 #define RB_SPI_IE_CNT_END 0x01 // RW, enable interrupt for SPI total byte count end 1032 #define RB_SPI_IE_BYTE_END 0x02 // RW, enable interrupt for SPI byte exchanged 1033 #define RB_SPI_IE_FIFO_HF 0x04 // RW, enable interrupt for SPI FIFO half 1034 #define RB_SPI_IE_DMA_END 0x08 // RW, enable interrupt for SPI0 DMA completion 1035 #define RB_SPI_IE_FIFO_OV 0x10 // RW, enable interrupt for SPI0 FIFO overflow 1036 #define RB_SPI_IE_FST_BYTE 0x80 // RW, enable interrupt for SPI0 slave mode first byte received 1037 #define SPI_CLOCK_DIV 3 1038 #define SPI_SLAVE_PRESET 3 1039 #define SPI_BUFFER 4 1040 #define SPI_RUN_FLAG 5 1041 #define RB_SPI_SLV_CMD_ACT 0x10 // RO, SPI0 slave first byte / command flag 1042 #define RB_SPI_FIFO_READY 0x20 // RO, SPI FIFO ready status 1043 #define RB_SPI_SLV_CS_LOAD 0x40 // RO, SPI0 slave chip-select loading status 1044 #define RB_SPI_SLV_SELECT 0x80 // RO, SPI0 slave selection status 1045 #define SPI_INT_FLAG 6 1046 #define RB_SPI_IF_CNT_END 0x01 // RW1, interrupt flag for SPI total byte count end 1047 #define RB_SPI_IF_BYTE_END 0x02 // RW1, interrupt flag for SPI byte exchanged 1048 #define RB_SPI_IF_FIFO_HF 0x04 // RW1, interrupt flag for SPI FIFO half (RB_SPI_FIFO_DIR ? >=4bytes : <4bytes) 1049 #define RB_SPI_IF_DMA_END 0x08 // RW1, interrupt flag for SPI0 DMA completion 1050 #define RB_SPI_IF_FIFO_OV 0x10 // RW1, interrupt flag for SPI0 FIFO overflow 1051 #define RB_SPI_FREE 0x40 // RO, current SPI free status 1052 #define RB_SPI_IF_FST_BYTE 0x80 // RW1, interrupt flag for SPI0 slave mode first byte received 1053 #define SPI_FIFO_COUNT 7 1054 #define SPI_TOTAL_CNT 0x0C 1055 #define SPI_FIFO 0x10 1056 #define SPI_DMA_NOW 0x14 1057 #define SPI_DMA_BEG 0x18 1058 #define SPI_DMA_END 0x1C 1059 1060 /* PWM4/5/6/7/8/9/10/11 register */ 1061 #define R32_PWM_CONTROL (*((PUINT32V)0x40005000)) // RW, PWM control 1062 #define R8_PWM_OUT_EN (*((PUINT8V)0x40005000)) // RW, PWM output enable control 1063 #define R8_PWM_POLAR (*((PUINT8V)0x40005001)) // RW, PWM output polarity control 1064 #define R8_PWM_CONFIG (*((PUINT8V)0x40005002)) // RW, PWM configuration 1065 #define R8_PWM_CLOCK_DIV (*((PUINT8V)0x40005003)) // RW, PWM clock divisor 1066 #define R32_PWM4_7_DATA (*((PUINT32V)0x40005004)) // RW, PWM4-7 data holding 1067 #define R8_PWM4_DATA (*((PUINT8V)0x40005004)) // RW, PWM4 data holding 1068 #define R8_PWM5_DATA (*((PUINT8V)0x40005005)) // RW, PWM5 data holding 1069 #define R8_PWM6_DATA (*((PUINT8V)0x40005006)) // RW, PWM6 data holding 1070 #define R8_PWM7_DATA (*((PUINT8V)0x40005007)) // RW, PWM7 data holding 1071 #define R32_PWM8_11_DATA (*((PUINT32V)0x40005008)) // RW, PWM8-11 data holding 1072 #define R8_PWM8_DATA (*((PUINT8V)0x40005008)) // RW, PWM8 data holding 1073 #define R8_PWM9_DATA (*((PUINT8V)0x40005009)) // RW, PWM9 data holding 1074 #define R8_PWM10_DATA (*((PUINT8V)0x4000500A)) // RW, PWM10 data holding 1075 #define R8_PWM11_DATA (*((PUINT8V)0x4000500B)) // RW, PWM11 data holding 1076 1077 /* PWM4/5/6/7/8/9/10/11 register address offset and bit define */ 1078 #define BA_PWMX ((PUINT8V)0x40005000) // point PWM4/5/6/7/8/9/10/11 base address 1079 #define PWM_OUT_EN 0 1080 #define RB_PWM4_OUT_EN 0x01 // RW, PWM4 output enable 1081 #define RB_PWM5_OUT_EN 0x02 // RW, PWM5 output enable 1082 #define RB_PWM6_OUT_EN 0x04 // RW, PWM6 output enable 1083 #define RB_PWM7_OUT_EN 0x08 // RW, PWM7 output enable 1084 #define RB_PWM8_OUT_EN 0x10 // RW, PWM8 output enable 1085 #define RB_PWM9_OUT_EN 0x20 // RW, PWM9 output enable 1086 #define RB_PWM10_OUT_EN 0x40 // RW, PWM10 output enable 1087 #define RB_PWM11_OUT_EN 0x80 // RW, PWM11 output enable 1088 #define PWM_POLAR 1 1089 #define RB_PWM4_POLAR 0x01 // RW, PWM4 output polarity: 0=default low and high action, 1=default high and low action 1090 #define RB_PWM5_POLAR 0x02 // RW, PWM5 output polarity: 0=default low and high action, 1=default high and low action 1091 #define RB_PWM6_POLAR 0x04 // RW, PWM6 output polarity: 0=default low and high action, 1=default high and low action 1092 #define RB_PWM7_POLAR 0x08 // RW, PWM7 output polarity: 0=default low and high action, 1=default high and low action 1093 #define RB_PWM8_POLAR 0x10 // RW, PWM8 output polarity: 0=default low and high action, 1=default high and low action 1094 #define RB_PWM9_POLAR 0x20 // RW, PWM9 output polarity: 0=default low and high action, 1=default high and low action 1095 #define RB_PWM10_POLAR 0x40 // RW, PWM10 output polarity: 0=default low and high action, 1=default high and low action 1096 #define RB_PWM11_POLAR 0x80 // RW, PWM11 output polarity: 0=default low and high action, 1=default high and low action 1097 #define PWM_CONFIG 2 1098 #define RB_PWM_CYCLE_SEL 0x01 // RW, PWM cycle selection: 0=256/128/64/32 clocks, 1=255/127/63/31 clocks 1099 #define RB_PWM_STAG_ST 0x02 // RO, PWM stagger cycle status 1100 #define RB_PWM_CYC_MOD 0x0c // RW, PWM data width mode: 00=8 bits data, 01=7 bits data, 10=6 bits data, 11=5 bits data 1101 #define RB_PWM4_5_STAG_EN 0x10 // RW, PWM4/5 stagger output enable: 0=independent output, 1=stagger output 1102 #define RB_PWM6_7_STAG_EN 0x20 // RW, PWM6/7 stagger output enable: 0=independent output, 1=stagger output 1103 #define RB_PWM8_9_STAG_EN 0x40 // RW, PWM8/9 stagger output enable: 0=independent output, 1=stagger output 1104 #define RB_PWM10_11_STAG_EN 0x80 // RW, PWM10/11 stagger output enable: 0=independent output, 1=stagger output 1105 #define PWM_CLOCK_DIV 3 1106 #define PWM4_DATA_HOLD 4 1107 #define PWM5_DATA_HOLD 5 1108 #define PWM6_DATA_HOLD 6 1109 #define PWM7_DATA_HOLD 7 1110 #define PWM8_DATA_HOLD 8 1111 #define PWM9_DATA_HOLD 9 1112 #define PWM10_DATA_HOLD 10 1113 #define PWM11_DATA_HOLD 11 1114 1115 /* LED register */ 1116 #define R32_LED_CONTROL (*((PUINT32V)0x40006400)) // RW, LED control 1117 #define R8_LED_CTRL_MOD (*((PUINT8V)0x40006400)) // RW, LED mode control 1118 #define R8_LED_CLOCK_DIV (*((PUINT8V)0x40006401)) // RW, LED serial clock divisor 1119 #define R8_LED_STATUS (*((PUINT8V)0x40006404)) // RO, LED status 1120 #define R32_LED_FIFO (*((PUINT32V)0x40006408)) // WO, LED FIFO register, width is half-word, only low 16 bit 1121 #define R16_LED_FIFO (*((PUINT16V)0x40006408)) // WO, LED FIFO register, width is half-word 1122 #define R32_LED_DMA_CNT (*((PUINT32V)0x40006410)) // RW, LED DMA main buffer remainder half-word count, exclude auxiliary buffer, automatic decreasing after DMA, only low 12 bit 1123 #define R16_LED_DMA_CNT (*((PUINT16V)0x40006410)) // RW, LED DMA main buffer remainder half-word count, exclude auxiliary buffer, automatic decreasing after DMA, only low 12 bit 1124 #define R32_LED_DMA_MAIN (*((PUINT32V)0x40006414)) // RW, LED main buffer DMA begin & current address, automatic increasing after DMA 1125 #define R16_LED_DMA_MAIN (*((PUINT16V)0x40006414)) // RW, LED main buffer DMA begin & current address, automatic increasing after DMA 1126 #define R32_LED_DMA_AUX (*((PUINT32V)0x40006418)) // RW, LED auxiliary buffer DMA begin & current address, automatic increasing after DMA 1127 #define R16_LED_DMA_AUX (*((PUINT16V)0x40006418)) // RW, LED auxiliary buffer DMA begin & current address, automatic increasing after DMA 1128 1129 /* LED register address offset and bit define */ 1130 #define LED_FIFO_SIZE 2 // LED FIFO size (depth), width is half-word 1131 #define BA_LED ((PUINT8V)0x40006400) // point LED base address 1132 #define LED_CTRL_MOD 0 1133 #define RB_LED_BIT_ORDER 0x01 // RW, LED bit data order: 0=LSB first, 1=MSB first 1134 #define RB_LED_ALL_CLEAR 0x02 // RW, force clear LED FIFO and count 1135 #define RB_LED_OUT_POLAR 0x04 // RW, LED output polarity: 0=pass, 1=invert 1136 #define RB_LED_OUT_EN 0x08 // RW, LED output enable 1137 #define RB_LED_DMA_EN 0x10 // RW, LED DMA enable and DMA interrupt enable 1138 #define RB_LED_IE_FIFO 0x20 // RW, enable interrupt for LED FIFO <=2 1139 #define RB_LED_CHAN_MOD 0xC0 // RW, LED channel mode: 00=LED0, 01=LED0/1, 10=LED0~3, 11=LED0~3 and LED2/3 from auxiliary buffer 1140 // RB_LED_CHAN_MOD: LED channel mode 1141 // 00: single channel output, LED0 1142 // 01: dual channels output, LED0/1 1143 // 10: 4 channels output, LED0~3 1144 // 11: 4 channels output and LED2/3 from aux buffer, LED0~3 1145 #define LED_CLOCK_DIV 1 1146 #define LED_STATUS 4 1147 #define RB_LED_FIFO_COUNT 0x07 // RO, LED FIFO byte count status, must divided by 2 for width half-word 1148 #define RB_LED_CLOCK 0x10 // RO, current LED clock level 1149 #define RB_LED_IF_FIFO 0x20 // RW1, interrupt flag for LED FIFO <=2, cleared by RW1 or write R32/R16_LED_FIFO 1150 #define RB_LED_FIFO_EMPTY 0x40 // RO: indicate FIFO empty status 1151 #define RB_LED_IF_DMA_END 0x80 // RW1, interrupt flag for LED DMA completion, cleared by RW1 or write R32/R16_LED_DMA_CNT 1152 #define LED_FIFO 8 1153 #define LED_DMA_CNT 0x10 1154 #define LED_DMA_BEG 0x14 1155 #define LED_DMA_END 0x18 1156 1157 /* LCD register */ 1158 #define R32_LCD_CONTROL (*((PUINT32V)(0x40006000))) 1159 #define R8_LCD_CTRL_MOD (*((PUINT8V)(0x40006000))) 1160 #define RB_SYS_POWER_ON 0x01 // RW, LCD digital system enable 1161 #define RB_LCD_POWER_ON 0x02 // RW, LCD analog system enable 1162 #define RB_LCD_BIAS 0x04 // RW, LCD bias select: 0=1/2 bias, 1=1/3 bias 1163 #define RB_LCD_DUTY 0x18 // RW, LCD duty select: 00=1/2 duty, 01=1/3 duty, 10=1/4 duty 1164 #define RB_LCD_SCAN_CLK 0x60 // RW, LCD scan clock select: 00=256Hz, 01=512Hz, 10=1KHz, 11=128Hz 1165 #define RB_LCD_V_SEL 0x80 // RW, LCD drive voltage：0=VIO33*100%(3.3V),1=VIO33*76%(2.5V) 1166 1167 #define R32_LCD_RAM0 (*((PUINT32V)(0x40006004))) // RW, LCD driver data0, address 0-3 1168 #define R32_LCD_RAM1 (*((PUINT32V)(0x40006008))) // RW, LCD driver data1, address 4-7 1169 #define R32_LCD_RAM2 (*((PUINT32V)(0x4000600C))) // RW, LCD driver data2, address 8-12 1170 1171 1172 /* Address space define */ 1173 #define BA_CODE ((PUINT32)0x00000000) // point code base address 1174 #define SZ_CODE 0x00040000 // code size 1175 #define BA_SFR ((PUINT32)0x40000000) // point SFR base address 1176 #define SZ_SFR 0x00010000 // SFR size 1177 #define BA_RAM ((PUINT32)0x20000000) // point RAM base address 1178 #define SZ_RAM 0x00008000 // RAM size 1179 #define BA_PPB ((PUINT32)0xE0000000) // point PPB base address 1180 #define SZ_PPB 0x00010000 // PPB size 1181 1182 /* Special Program Space */ 1183 #define DATA_FLASH_ADDR 0x3E800 // start address of Data-Flash 1184 #define DATA_FLASH_SIZE 0x0800 // size of Data-Flash 1185 #define BOOT_LOAD_ADDR 0x3F000 // start address of boot loader program 1186 #define BOOT_LOAD_SIZE 0x1000 // size of boot loader program 1187 #define BOOT_LOAD_CFG 0x40000 // start address of configuration information for boot loader program 1188 #define ROM_CFG_ADDR 0x40010 // chip configuration information address 1189 1190 /*----- Reference Information --------------------------------------------*/ 1191 #define ID_CH579 0x79 // chip ID 1192 1193 /* Interrupt routine address and interrupt number */ 1194 #define INT_ID_TMR0 0 // interrupt number for Timer0 1195 #define INT_ID_GPIO 1 // interrupt number for GPIO 1196 #define INT_ID_SLAVE 2 // interrupt number for Slave 1197 #define INT_ID_SPI0 3 // interrupt number for SPI0 1198 #define INT_ID_BLEB 4 // interrupt number for BLEBB 1199 #define INT_ID_BLEL 5 // interrupt number for BLELLE 1200 #define INT_ID_USB 6 // interrupt number for USB 1201 #define INT_ID_ETH 7 // interrupt number for ETH 1202 #define INT_ID_TMR1 8 // interrupt number for Timer1 1203 #define INT_ID_TMR2 9 // interrupt number for Timer2 1204 #define INT_ID_UART0 10 // interrupt number for UART0 1205 #define INT_ID_UART1 11 // interrupt number for UART1 1206 #define INT_ID_RTC 12 // interrupt number for RTC 1207 #define INT_ID_ADC 13 // interrupt number for ADC and TouchKey 1208 #define INT_ID_SPI1 14 // interrupt number for SPI1 1209 #define INT_ID_LED 15 // interrupt number for LED 1210 #define INT_ID_TMR3 16 // interrupt number for Timer3 1211 #define INT_ID_UART2 17 // interrupt number for UART2 1212 #define INT_ID_UART3 18 // interrupt number for UART3 1213 #define INT_ID_WDOG_BAT 19 // interrupt number for Watch-Dog timer and Battery low voltage 1214 #define INT_VEC_ENTRY_SZ 4 // size of each interrupt vector entry 1215 #define INT_ADDR_TMR0 (INT_ID_TMR0*INT_VEC_ENTRY_SZ+64) // interrupt vector address for Timer0 1216 #define INT_ADDR_GPIO (INT_ID_GPIO*INT_VEC_ENTRY_SZ+64) // interrupt vector address for GPIO 1217 #define INT_ADDR_SLAVE (INT_ID_SLAVE*INT_VEC_ENTRY_SZ+64) // interrupt vector address for Slave 1218 #define INT_ADDR_SPI0 (INT_ID_SPI0*INT_VEC_ENTRY_SZ+64) // interrupt vector address for SPI0 1219 #define INT_ADDR_BLEB (INT_ID_BLEB*INT_VEC_ENTRY_SZ+64) // interrupt vector address for BLEBB 1220 #define INT_ADDR_BLEL (INT_ID_BLEL*INT_VEC_ENTRY_SZ+64) // interrupt vector address for BLELLE 1221 #define INT_ADDR_USB (INT_ID_USB*INT_VEC_ENTRY_SZ+64) // interrupt vector address for USB 1222 #define INT_ADDR_ETH (INT_ID_ETH*INT_VEC_ENTRY_SZ+64) // interrupt vector address for ETH 1223 #define INT_ADDR_TMR1 (INT_ID_TMR1*INT_VEC_ENTRY_SZ+64) // interrupt vector address for Timer1 1224 #define INT_ADDR_TMR2 (INT_ID_TMR2*INT_VEC_ENTRY_SZ+64) // interrupt vector address for Timer2 1225 #define INT_ADDR_UART0 (INT_ID_UART0*INT_VEC_ENTRY_SZ+64) // interrupt vector address for UART0 1226 #define INT_ADDR_UART1 (INT_ID_UART1*INT_VEC_ENTRY_SZ+64) // interrupt vector address for UART1 1227 #define INT_ADDR_RTC (INT_ID_RTC*INT_VEC_ENTRY_SZ+64) // interrupt vector address for RTC 1228 #define INT_ADDR_AD (INT_ID_ADC*INT_VEC_ENTRY_SZ+64) // interrupt vector address for ADC and TouchKey 1229 #define INT_ADDR_SPI1 (INT_ID_SPI1*INT_VEC_ENTRY_SZ+64) // interrupt vector address for SPI1 1230 #define INT_ADDR_LED (INT_ID_LED*INT_VEC_ENTRY_SZ+64) // interrupt vector address for LED 1231 #define INT_ADDR_Timer3 (INT_ID_Timer3*INT_VEC_ENTRY_SZ+64) // interrupt vector address for Timer3 1232 #define INT_ADDR_UART2 (INT_ID_UART2*INT_VEC_ENTRY_SZ+64) // interrupt vector address for UART2 1233 #define INT_ADDR_UART3 (INT_ID_UART3*INT_VEC_ENTRY_SZ+64) // interrupt vector address for UART3 1234 #define INT_ADDR_WDOG_BAT (INT_ID_WDOG_BAT*INT_VEC_ENTRY_SZ+64) // interrupt vector address for Watch-Dog timer and Battery low voltage 1235 1236 #ifndef TABLE_IRQN 1237 #define __NVIC_PRIO_BITS 2 /*!< uses 2 Bits for the Priority Levels */ 1238 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 1239 typedef enum IRQn 1240 { 1241 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ 1242 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 1243 HardFault_IRQn = -13, /*!< 3 HardFault Interrupt */ 1244 SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ 1245 PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ 1246 SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */ 1247 /* ---------------------- ARMCM0 Specific Interrupt Numbers --------------------- */ 1248 TMR0_IRQn = 0, /*!< Timer0 Interrupt */ 1249 GPIO_IRQn = 1, /*!< GPIO A/B Interrupt */ 1250 SLAVE_IRQn = 2, /*!< Slave parallel port Interrupt */ 1251 SPI0_IRQn = 3, /*!< SPI0 Interrupt */ 1252 BLEB_IRQn = 4, /*!< BB Interrupt */ 1253 BLEL_IRQn = 5, /*!< LLE Interrupt */ 1254 USB_IRQn = 6, /*!< USB Interrupt */ 1255 ETH_IRQn = 7, /*!< Ethernet Interrupt */ 1256 TMR1_IRQn = 8, /*!< Timer1 Interrupt */ 1257 TMR2_IRQn = 9, /*!< Timer2 Interrupt */ 1258 UART0_IRQn = 10, /*!< UART0 Interrupt */ 1259 UART1_IRQn = 11, /*!< UART1 Interrupt */ 1260 RTC_IRQn = 12, /*!< Real Time Clock Interrupt */ 1261 ADC_IRQn = 13, /*!< ADC Interrupt */ 1262 SPI1_IRQn = 14, /*!< SPI1 Interrupt */ 1263 LED_IRQn = 15, /*!< LED control Interrupt */ 1264 TMR3_IRQn = 16, /*!< Timer3 Interrupt */ 1265 UART2_IRQn = 17, /*!< UART2 Interrupt */ 1266 UART3_IRQn = 18, /*!< UART3 Interrupt */ 1267 WDOG_BAT_IRQn = 19, /*!< Watch Dog Interrupt */ 1268 } IRQn_Type; 1269 #endif 1270 1271 1272 #ifdef __cplusplus 1273 } 1274 #endif 1275 1276 #endif // __CH579SFR_H__ 1277 1278 1279 #ifndef __CH579ETHSFR_H__ 1280 #define __CH579ETHSFR_H__ 1281 1282 #ifdef __cplusplus 1283 extern "C" { 1284 #endif 1285 1286 /******************************************************************************/ 1287 /* ETH Peripheral memory map */ 1288 /******************************************************************************/ 1289 /* ETH addresses 1290 // ETH: +9000H - 93FFH */ 1291 #define ETH_BASE_ADDR (0x40009000) 1292 1293 /* ETH register */ 1294 #define R8_ETH_EIE (*((PUINT8V)(0x40009003))) /* 中断使能寄存器 */ 1295 #define RB_ETH_EIE_INTIE 0x80 /* RW 中断使能 */ 1296 #define RB_ETH_EIE_RXIE 0x40 /* RW 接收完成中断使能 */ 1297 #define RB_ETH_EIE_LINKIE 0x10 /* RW Link 变化中断使能 */ 1298 #define RB_ETH_EIE_TXIE 0x08 /* RW 发送完成中断使能 */ 1299 #define RB_ETH_EIE_R_EN50 0x04 /* RW TX 50Ω电阻调节。1：片内 50Ω连接 0：片内 50Ω断开 */ 1300 #define RB_ETH_EIE_TXERIE 0x02 /* RW 发送错误中断使能 */ 1301 #define RB_ETH_EIE_RXERIE 0x01 /* RW1 接收错误标志 */ 1302 #define R32_ETH_CON (*((PUINT32V)(0x40009004))) 1303 #define R8_ETH_EIR (*((PUINT8V)(0x40009004))) /* 中断标志寄存器 */ 1304 #define RB_ETH_EIR_RXIF 0x40 /* RW1 接收完成标志 */ 1305 #define RB_ETH_EIR_LINKIF 0x10 /* RW1 Link 变化标志 */ 1306 #define RB_ETH_EIR_TXIF 0x08 /* RW1 发送完成标志 */ 1307 #define RB_ETH_EIR_TXERIF 0x02 /* RW1 发送错误标志 */ 1308 #define RB_ETH_EIR_RXERIF 0x01 1309 #define R8_ETH_ESTAT (*((PUINT8V)(0x40009005))) /* 状态寄存器 */ 1310 #define RB_ETH_ESTAT_INT 0x80 /* RW1 中断 */ 1311 #define RB_ETH_ESTAT_BUFER 0x40 /* RW1 Buffer 错误，理论上 mcu 主频太低才会发生 */ 1312 #define RB_ETH_ESTAT_RXCRCER 0x20 /* RO 接收 crc 出错 */ 1313 #define RB_ETH_ESTAT_RXNIBBLE 0x10 /* RO 接收 nibble 错误 */ 1314 #define RB_ETH_ESTAT_RXMORE 0x08 /* RO 接收超过最大数据包 */ 1315 #define RB_ETH_ESTAT_RXBUSY 0x04 /* RO 接收进行中 */ 1316 #define RB_ETH_ESTAT_TXABRT 0x02 /* RO 发送被 mcu 打断 */ 1317 #define R8_ETH_ECON2 (*((PUINT8V)(0x40009006))) /* ETH PHY模拟模块控制寄存器 */ 1318 #define RB_ETH_ECON2_RX 0x0E /* 必须写入011 */ 1319 #define RB_ETH_ECON2_TX 0x01 1320 #define RB_ETH_ECON2_MUST 0x06 /* 必须写入011 */ 1321 #define R8_ETH_ECON1 (*((PUINT8V)(0x40009007))) /* 收发控制寄存器 */ 1322 #define RB_ETH_ECON1_TXRST 0x80 /* RW 发送模块复位 */ 1323 #define RB_ETH_ECON1_RXRST 0x40 /* RW 接收模块复位 */ 1324 #define RB_ETH_ECON1_TXRTS 0x08 /* RW 发送开始，发送完成后自动清零，如主动清零会使发送错误标志TXERIF和TXABRT变1 */ 1325 #define RB_ETH_ECON1_RXEN 0x04 /* RW 接收使能，清零时如正在接受则错误标志RXERIF变1 */ 1326 1327 #define R32_ETH_TX (*((PUINT32V)(0x40009008))) /* 发送控制 */ 1328 #define R16_ETH_ETXST (*((PUINT16V)(0x40009008))) /* RW 发送 DMA 缓冲区起始地址 */ 1329 #define R16_ETH_ETXLN (*((PUINT16V)(0x4000900A))) /* RW 发送长度 */ 1330 #define R32_ETH_RX (*((PUINT32V)(0x4000900C))) /* 接收控制 */ 1331 #define R16_ETH_ERXST (*((PUINT16V)(0x4000900C))) /* RW 接收 DMA 缓冲区起始地址 */ 1332 #define R16_ETH_ERXLN (*((PUINT16V)(0x4000900E))) /* RO 接收长度 */ 1333 1334 #define R32_ETH_HTL (*((PUINT32V)(0x40009010))) 1335 #define R8_ETH_EHT0 (*((PUINT8V)(0x40009010))) /* RW Hash Table Byte0 */ 1336 #define R8_ETH_EHT1 (*((PUINT8V)(0x40009011))) /* RW Hash Table Byte1 */ 1337 #define R8_ETH_EHT2 (*((PUINT8V)(0x40009012))) /* RW Hash Table Byte2 */ 1338 #define R8_ETH_EHT3 (*((PUINT8V)(0x40009013))) /* RW Hash Table Byte3 */ 1339 #define R32_ETH_HTH (*((PUINT32V)(0x40009014))) 1340 #define R8_ETH_EHT4 (*((PUINT8V)(0x40009014))) /* RW Hash Table Byte4 */ 1341 #define R8_ETH_EHT5 (*((PUINT8V)(0x40009015))) /* RW Hash Table Byte5 */ 1342 #define R8_ETH_EHT6 (*((PUINT8V)(0x40009016))) /* RW Hash Table Byte6 */ 1343 #define R8_ETH_EHT7 (*((PUINT8V)(0x40009017))) /* RW Hash Table Byte7 */ 1344 1345 #define R32_ETH_MACON (*((PUINT32V)(0x40009018))) 1346 #define R8_ETH_ERXFCON (*((PUINT8V)(0x40009018))) /* 接收包过滤控制寄存器 */ 1347 #define RB_ETH_ERXFCON_UCEN 0x80 /* RW 0=不启用该过滤条件，1=当ANDOR=1，目标地址不匹配将被过滤，当ANDOR=0，目标地址匹配将被接收 */ 1348 #define RB_ETH_ERXFCON_ANDOR 0x40 /* RW 1=AND，所有过滤条件都满足包才被接收 0=OR，任一过滤条件满足包均被接收 */ 1349 #define RB_ETH_ERXFCON_CRCEN 0x20 /* RW 0=不启用该过滤条件，1=当ANDOR=1，CRC校验错将被过滤，当ANDOR=0，CRC校验正确将被接收 */ 1350 #define RB_ETH_ERXFCON_MPEN 0x08 /* RW 0=不启用该过滤条件，1=当ANDOR=1，非魔法包将被过滤，当ANDOR=0，魔法包将被接收 */ 1351 #define RB_ETH_ERXFCON_HTEN 0x04 /* RW 0=不启用该过滤条件，1=当ANDOR=1，hash table不匹配将被过滤，当ANDOR=0，hash table匹配将被接收 */ 1352 #define RB_ETH_ERXFCON_MCEN 0x02 /* RW 0=不启用该过滤条件，1=当ANDOR=1，组播包不匹配将被过滤，当ANDOR=0，组播包匹配将被接收 */ 1353 #define RB_ETH_ERXFCON_BCEN 0x01 /* RW 0=不启用该过滤条件，1=当ANDOR=1，非广播包将被过滤，当ANDOR=0，广播包将被接收 */ 1354 #define R8_ETH_MACON1 (*((PUINT8V)(0x40009019))) /* Mac 层流控制寄存器 */ 1355 #define RB_ETH_MACON1_FCEN 0x30 /* RW 当FULDPX=0均无效，当FULDPX=1，11=发送0 timer暂停帧，然后停止发送，10=周期性发送暂停帧，01=发送一次暂停帧，然后停止发送，00=停止发送暂停帧 */ 1356 #define RB_ETH_MACON1_TXPAUS 0x08 /* RW 发送pause帧使能 */ 1357 #define RB_ETH_MACON1_RXPAUS 0x04 /* RW 接收pause帧使能 */ 1358 #define RB_ETH_MACON1_PASSALL 0x02 /* RW 1=没被过滤的控制帧将写入缓存，0=控制帧将被过滤 */ 1359 #define RB_ETH_MACON1_MARXEN 0x01 /* RW MAC层接收使能 */ 1360 #define R8_ETH_MACON2 (*((PUINT8V)(0x4000901A))) /* Mac 层封包控制寄存器 */ 1361 #define RB_ETH_MACON2_PADCFG 0xE0 /* RW 短包填充设置 */ 1362 #define RB_ETH_MACON2_TXCRCEN 0x10 /* RW 发送添加crc，PADCFG中如需要添加crc，该位置1 */ 1363 #define RB_ETH_MACON2_PHDREN 0x08 /* RW 特殊4字节不参与crc校验 */ 1364 #define RB_ETH_MACON2_HFRMEN 0x04 /* RW 允许接收巨型帧 */ 1365 #define RB_ETH_MACON2_FULDPX 0x01 /* RW 全双工 */ 1366 #define R8_ETH_MABBIPG (*((PUINT8V)(0x4000901B))) /* 最小包间间隔寄存器 */ 1367 #define RB_ETH_MABBIPG_MABBIPG 0x7F /* RW 最小包间间隔字节数 */ 1368 1369 #define R32_ETH_TIM (*((PUINT32V)(0x4000901C))) 1370 #define R16_ETH_EPAUS (*((PUINT16V)(0x4000901C))) /* RW 流控制暂停帧时间寄存器 */ 1371 #define R16_ETH_MAMXFL (*((PUINT16V)(0x4000901E))) /* RW 最大接收包长度寄存器 */ 1372 #define R16_ETH_MIRD (*((PUINT16V)(0x40009020))) /* RW MII 读数据寄存器 */ 1373 1374 #define R32_ETH_MIWR (*((PUINT32V)(0x40009024))) 1375 #define R8_ETH_MIREGADR (*((PUINT8V)(0x40009024))) /* MII 地址寄存器 */ 1376 #define RB_ETH_MIREGADR_MASK 0x1F /* RW PHY 寄存器地址掩码 */ 1377 #define R8_ETH_MISTAT (*((PUINT8V)(0x40009025))) /* MII 状态寄存器 */ 1378 //#define RB_ETH_MIREGADR_MIIWR 0x20 /* WO MII 写命令 */ 1379 #define R16_ETH_MIWR (*((PUINT16V)(0x40009026))) /* WO MII 写数据寄存器 */ 1380 #define R32_ETH_MAADRL (*((PUINT32V)(0x40009028))) /* RW MAC 1-4 */ 1381 #define R16_ETH_MAADRH (*((PUINT16V)(0x4000902C))) /* RW MAC 5-6 */ 1382 1383 #ifdef __cplusplus 1384 } 1385 #endif 1386 1387 #endif // __CH579ETHSFR_H__ 1388 1389 1390 #ifndef __CH579USBSFR_H__ 1391 #define __CH579USBSFR_H__ 1392 1393 #ifdef __cplusplus 1394 extern "C" { 1395 #endif 1396 1397 /******************************************************************************/ 1398 /* Peripheral memory map */ 1399 /******************************************************************************/ 1400 /* usb addresses 1401 // USB: +8000H - 83FFH */ 1402 #define USB_BASE_ADDR (0x40008000) 1403 1404 /* USB */ 1405 #define R32_USB_CONTROL (*((PUINT32V)(0x40008000))) // USB control & interrupt enable & device address 1406 #define R8_USB_CTRL (*((PUINT8V)(0x40008000))) // USB base control 1407 #define RB_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode 1408 #define RB_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps 1409 #define RB_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable 1410 #define RB_UC_SYS_CTRL1 0x20 // USB system control high bit 1411 #define RB_UC_SYS_CTRL0 0x10 // USB system control low bit 1412 #define MASK_UC_SYS_CTRL 0x30 // bit mask of USB system control 1413 // bUC_HOST_MODE & bUC_SYS_CTRL1 & bUC_SYS_CTRL0: USB system control 1414 // 0 00: disable USB device and disable internal pullup resistance 1415 // 0 01: enable USB device and disable internal pullup resistance, need external pullup resistance 1416 // 0 1x: enable USB device and enable internal pullup resistance 1417 // 1 00: enable USB host and normal status 1418 // 1 01: enable USB host and force UDP/UDM output SE0 state 1419 // 1 10: enable USB host and force UDP/UDM output J state 1420 // 1 11: enable USB host and force UDP/UDM output resume or K state 1421 #define RB_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid 1422 #define RB_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear 1423 #define RB_UC_CLR_ALL 0x02 // force clear FIFO and count of USB 1424 #define RB_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB 1425 1426 #define R8_UDEV_CTRL (*((PUINT8V)(0x40008001))) // USB device physical prot control 1427 #define RB_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable 1428 #define RB_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level 1429 #define RB_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level 1430 #define RB_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed 1431 #define RB_UD_GP_BIT 0x02 // general purpose bit 1432 #define RB_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable 1433 1434 #define R8_UHOST_CTRL R8_UDEV_CTRL // USB host physical prot control 1435 #define RB_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable 1436 #define RB_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level 1437 #define RB_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level 1438 #define RB_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed 1439 #define RB_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset 1440 #define RB_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached 1441 1442 #define R8_USB_INT_EN (*((PUINT8V)(0x40008002))) // USB interrupt enable 1443 #define RB_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode 1444 #define RB_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode 1445 #define RB_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow 1446 #define RB_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode 1447 #define RB_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event 1448 #define RB_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion 1449 #define RB_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode 1450 #define RB_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode 1451 1452 #define R8_USB_DEV_AD (*((PUINT8V)(0x40008003))) // USB device address 1453 #define RB_UDA_GP_BIT 0x80 // general purpose bit 1454 #define MASK_USB_ADDR 0x7F // bit mask for USB device address 1455 1456 #define R32_USB_STATUS (*((PUINT32V)(0x40008004))) // USB miscellaneous status & interrupt flag & interrupt status 1457 #define R8_USB_MIS_ST (*((PUINT8V)(0x40008005))) // USB miscellaneous status 1458 #define RB_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status 1459 #define RB_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host 1460 #define RB_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status 1461 #define RB_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty) 1462 #define RB_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status 1463 #define RB_UMS_SUSPEND 0x04 // RO, indicate USB suspend status 1464 #define RB_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host 1465 #define RB_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host 1466 1467 #define R8_USB_INT_FG (*((PUINT8V)(0x40008006))) // USB interrupt flag 1468 #define RB_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received 1469 #define RB_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK 1470 #define RB_U_SIE_FREE 0x20 // RO, indicate USB SIE free status 1471 #define RB_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear 1472 #define RB_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear 1473 #define RB_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear 1474 #define RB_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear 1475 #define RB_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear 1476 #define RB_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear 1477 1478 #define R8_USB_INT_ST (*((PUINT8V)(0x40008007))) // USB interrupt status 1479 #define RB_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode 1480 #define RB_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK 1481 #define RB_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode 1482 #define RB_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode 1483 #define MASK_UIS_TOKEN 0x30 // RO, bit mask of current token PID code received for USB device mode 1484 #define UIS_TOKEN_OUT 0x00 1485 #define UIS_TOKEN_SOF 0x10 1486 #define UIS_TOKEN_IN 0x20 1487 #define UIS_TOKEN_SETUP 0x30 1488 // bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode 1489 // 00: OUT token PID received 1490 // 01: SOF token PID received 1491 // 10: IN token PID received 1492 // 11: SETUP token PID received 1493 #define MASK_UIS_ENDP 0x0F // RO, bit mask of current transfer endpoint number for USB device mode 1494 #define MASK_UIS_H_RES 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received 1495 1496 #define R8_USB_RX_LEN (*((PUINT8V)(0x40008008))) // USB receiving length 1497 #define R32_USB_BUF_MODE (*((PUINT32V)(0x4000800c))) // USB endpoint buffer mode 1498 #define R8_UEP4_1_MOD (*((PUINT8V)(0x4000800c))) // endpoint 4/1 mode 1499 #define RB_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) 1500 #define RB_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) 1501 #define RB_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 1502 // bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA 1503 // 0 0 x: disable endpoint and disable buffer 1504 // 1 0 0: 64 bytes buffer for receiving (OUT endpoint) 1505 // 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes 1506 // 0 1 0: 64 bytes buffer for transmittal (IN endpoint) 1507 // 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes 1508 // 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes 1509 // 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes 1510 #define RB_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) 1511 #define RB_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) 1512 // bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA 1513 // 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) 1514 // 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes 1515 // 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes 1516 // 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) 1517 // + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes 1518 1519 #define R8_UEP2_3_MOD (*((PUINT8V)(0x4000800d))) // endpoint 2/3 mode 1520 #define RB_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) 1521 #define RB_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) 1522 #define RB_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 1523 #define RB_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) 1524 #define RB_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) 1525 #define RB_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 1526 1527 #define R8_UH_EP_MOD R8_UEP2_3_MOD //host endpoint mode 1528 #define RB_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal 1529 #define RB_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint 1530 // bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA 1531 // 0 x: disable endpoint and disable buffer 1532 // 1 0: 64 bytes buffer for transmittal (OUT endpoint) 1533 // 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes 1534 #define RB_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving 1535 #define RB_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint 1536 // bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA 1537 // 0 x: disable endpoint and disable buffer 1538 // 1 0: 64 bytes buffer for receiving (IN endpoint) 1539 // 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes 1540 1541 #define R16_UEP0_DMA (*((PUINT16V)(0x40008010))) // endpoint 0 DMA buffer address 1542 #define R16_UEP1_DMA (*((PUINT16V)(0x40008014))) // endpoint 1 DMA buffer address 1543 #define R16_UEP2_DMA (*((PUINT16V)(0x40008018))) // endpoint 2 DMA buffer address 1544 #define R16_UH_RX_DMA R16_UEP2_DMA // host rx endpoint buffer high address 1545 #define R16_UEP3_DMA (*((PUINT16V)(0x4000801C))) // endpoint 3 DMA buffer address 1546 #define R16_UH_TX_DMA R16_UEP3_DMA // host tx endpoint buffer high address 1547 #define R32_USB_EP0_CTRL (*((PUINT32V)(0x40008020))) // endpoint 0 control & transmittal length 1548 #define R8_UEP0_T_LEN (*((PUINT8V)(0x40008020))) // endpoint 0 transmittal length 1549 #define R8_UEP0_CTRL (*((PUINT8V)(0x40008022))) // endpoint 0 control 1550 #define R32_USB_EP1_CTRL (*((PUINT32V)(0x40008024))) // endpoint 1 control & transmittal length 1551 #define R8_UEP1_T_LEN (*((PUINT8V)(0x40008024))) // endpoint 1 transmittal length 1552 #define R8_UEP1_CTRL (*((PUINT8V)(0x40008026))) // endpoint 1 control 1553 #define RB_UEP_R_TOG 0x80 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 1554 #define RB_UEP_T_TOG 0x40 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 1555 #define RB_UEP_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle 1556 #define RB_UEP_R_RES1 0x08 // handshake response type high bit for USB endpoint X receiving (OUT) 1557 #define RB_UEP_R_RES0 0x04 // handshake response type low bit for USB endpoint X receiving (OUT) 1558 #define MASK_UEP_R_RES 0x0C // bit mask of handshake response type for USB endpoint X receiving (OUT) 1559 #define UEP_R_RES_ACK 0x00 1560 #define UEP_R_RES_TOUT 0x04 1561 #define UEP_R_RES_NAK 0x08 1562 #define UEP_R_RES_STALL 0x0C 1563 // RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) 1564 // 00: ACK (ready) 1565 // 01: no response, time out to host, for non-zero endpoint isochronous transactions 1566 // 10: NAK (busy) 1567 // 11: STALL (error) 1568 #define RB_UEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN) 1569 #define RB_UEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN) 1570 #define MASK_UEP_T_RES 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) 1571 #define UEP_T_RES_ACK 0x00 1572 #define UEP_T_RES_TOUT 0x01 1573 #define UEP_T_RES_NAK 0x02 1574 #define UEP_T_RES_STALL 0x03 1575 // bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) 1576 // 00: DATA0 or DATA1 then expecting ACK (ready) 1577 // 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions 1578 // 10: NAK (busy) 1579 // 11: STALL (error) 1580 1581 #define R8_UH_SETUP R8_UEP1_CTRL // host aux setup 1582 #define RB_UH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub 1583 #define RB_UH_SOF_EN 0x40 // USB host automatic SOF enable 1584 1585 #define R32_USB_EP2_CTRL (*((PUINT32V)(0x40008028))) // endpoint 2 control & transmittal length 1586 #define R8_UEP2_T_LEN (*((PUINT8V)(0x40008028))) // endpoint 2 transmittal length 1587 #define R8_UEP2_CTRL (*((PUINT8V)(0x4000802a))) // endpoint 2 control 1588 1589 #define R8_UH_EP_PID R8_UEP2_T_LEN // host endpoint and PID 1590 #define MASK_UH_TOKEN 0xF0 // bit mask of token PID for USB host transfer 1591 #define MASK_UH_ENDP 0x0F // bit mask of endpoint number for USB host transfer 1592 1593 #define R8_UH_RX_CTRL R8_UEP2_CTRL // host receiver endpoint control 1594 #define RB_UH_R_TOG 0x80 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 1595 #define RB_UH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle 1596 #define RB_UH_R_RES 0x04 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions 1597 1598 #define R32_USB_EP3_CTRL (*((PUINT32V)(0x4000802c))) // endpoint 3 control & transmittal length 1599 #define R8_UEP3_T_LEN (*((PUINT8V)(0x4000802c))) // endpoint 3 transmittal length 1600 #define R8_UEP3_CTRL (*((PUINT8V)(0x4000802e))) // endpoint 3 control 1601 #define R8_UH_TX_LEN R8_UEP3_T_LEN // host transmittal endpoint transmittal length 1602 1603 #define R8_UH_TX_CTRL R8_UEP3_CTRL // host transmittal endpoint control 1604 #define RB_UH_T_TOG 0x40 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 1605 #define RB_UH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle 1606 #define RB_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions 1607 1608 #define R32_USB_EP4_CTRL (*((PUINT32V)(0x40008030))) // endpoint 4 control & transmittal length 1609 #define R8_UEP4_T_LEN (*((PUINT8V)(0x40008030))) // endpoint 4 transmittal length 1610 #define R8_UEP4_CTRL (*((PUINT8V)(0x40008032))) // endpoint 4 control 1611 1612 #define R8_USB_TYPE_C_CTRL (*((PUINT8V)(0x40008038))) // USB type-C control 1613 #define RB_UTCC_GP_BIT 0x80 // USB general purpose bit 1614 #define RB_UCC2_PD_EN 0x40 // USB CC2 5.1K pulldown resistance: 0=disable, 1=enable pulldown 1615 #define RB_UCC2_PU1_EN 0x20 // USB CC2 pullup resistance control high bit 1616 #define RB_UCC2_PU0_EN 0x10 // USB CC2 pullup resistance control low bit 1617 #define RB_VBUS_PD_EN 0x08 // USB VBUS 10K pulldown resistance: 0=disable, 1=enable pullup 1618 #define RB_UCC1_PD_EN 0x04 // USB CC1 5.1K pulldown resistance: 0=disable, 1=enable pulldown 1619 #define RB_UCC1_PU1_EN 0x02 // USB CC1 pullup resistance control high bit 1620 #define RB_UCC1_PU0_EN 0x01 // USB CC1 pullup resistance control low bit 1621 // RB_UCC?_PU1_EN & RB_UCC?_PU0_EN: USB CC pullup resistance selection 1622 // 00: disable pullup resistance 1623 // 01: enable 36K pullup resistance for default USB power 1624 // 10: enable 12K pullup resistance for 1.5A USB power 1625 // 11: enable 4.7K pullup resistance for 3A USB power 1626 1627 1628 #ifdef __cplusplus 1629 } 1630 #endif 1631 1632 #endif //__CH579USBSFR_H__ 1633 1634 1635 #ifndef __USB_TYPE__ 1636 #define __USB_TYPE__ 1637 1638 #ifdef __cplusplus 1639 extern "C" { 1640 #endif 1641 1642 /*----- USB constant and structure define --------------------------------*/ 1643 1644 /* USB PID */ 1645 #ifndef USB_PID_SETUP 1646 #define USB_PID_NULL 0x00 /* reserved PID */ 1647 #define USB_PID_SOF 0x05 1648 #define USB_PID_SETUP 0x0D 1649 #define USB_PID_IN 0x09 1650 #define USB_PID_OUT 0x01 1651 #define USB_PID_ACK 0x02 1652 #define USB_PID_NAK 0x0A 1653 #define USB_PID_STALL 0x0E 1654 #define USB_PID_DATA0 0x03 1655 #define USB_PID_DATA1 0x0B 1656 #define USB_PID_PRE 0x0C 1657 #endif 1658 1659 /* USB standard device request code */ 1660 #ifndef USB_GET_DESCRIPTOR 1661 #define USB_GET_STATUS 0x00 1662 #define USB_CLEAR_FEATURE 0x01 1663 #define USB_SET_FEATURE 0x03 1664 #define USB_SET_ADDRESS 0x05 1665 #define USB_GET_DESCRIPTOR 0x06 1666 #define USB_SET_DESCRIPTOR 0x07 1667 #define USB_GET_CONFIGURATION 0x08 1668 #define USB_SET_CONFIGURATION 0x09 1669 #define USB_GET_INTERFACE 0x0A 1670 #define USB_SET_INTERFACE 0x0B 1671 #define USB_SYNCH_FRAME 0x0C 1672 #endif 1673 1674 /* USB hub class request code */ 1675 #ifndef HUB_GET_DESCRIPTOR 1676 #define HUB_GET_STATUS 0x00 1677 #define HUB_CLEAR_FEATURE 0x01 1678 #define HUB_GET_STATE 0x02 1679 #define HUB_SET_FEATURE 0x03 1680 #define HUB_GET_DESCRIPTOR 0x06 1681 #define HUB_SET_DESCRIPTOR 0x07 1682 #endif 1683 1684 /* USB HID class request code */ 1685 #ifndef HID_GET_REPORT 1686 #define HID_GET_REPORT 0x01 1687 #define HID_GET_IDLE 0x02 1688 #define HID_GET_PROTOCOL 0x03 1689 #define HID_SET_REPORT 0x09 1690 #define HID_SET_IDLE 0x0A 1691 #define HID_SET_PROTOCOL 0x0B 1692 #endif 1693 1694 /* Bit define for USB request type */ 1695 #ifndef USB_REQ_TYP_MASK 1696 #define USB_REQ_TYP_IN 0x80 /* control IN, device to host */ 1697 #define USB_REQ_TYP_OUT 0x00 /* control OUT, host to device */ 1698 #define USB_REQ_TYP_READ 0x80 /* control read, device to host */ 1699 #define USB_REQ_TYP_WRITE 0x00 /* control write, host to device */ 1700 #define USB_REQ_TYP_MASK 0x60 /* bit mask of request type */ 1701 #define USB_REQ_TYP_STANDARD 0x00 1702 #define USB_REQ_TYP_CLASS 0x20 1703 #define USB_REQ_TYP_VENDOR 0x40 1704 #define USB_REQ_TYP_RESERVED 0x60 1705 #define USB_REQ_RECIP_MASK 0x1F /* bit mask of request recipient */ 1706 #define USB_REQ_RECIP_DEVICE 0x00 1707 #define USB_REQ_RECIP_INTERF 0x01 1708 #define USB_REQ_RECIP_ENDP 0x02 1709 #define USB_REQ_RECIP_OTHER 0x03 1710 #endif 1711 1712 /* USB request type for hub class request */ 1713 #ifndef HUB_GET_HUB_DESCRIPTOR 1714 #define HUB_CLEAR_HUB_FEATURE 0x20 1715 #define HUB_CLEAR_PORT_FEATURE 0x23 1716 #define HUB_GET_BUS_STATE 0xA3 1717 #define HUB_GET_HUB_DESCRIPTOR 0xA0 1718 #define HUB_GET_HUB_STATUS 0xA0 1719 #define HUB_GET_PORT_STATUS 0xA3 1720 #define HUB_SET_HUB_DESCRIPTOR 0x20 1721 #define HUB_SET_HUB_FEATURE 0x20 1722 #define HUB_SET_PORT_FEATURE 0x23 1723 #endif 1724 1725 /* Hub class feature selectors */ 1726 #ifndef HUB_PORT_RESET 1727 #define HUB_C_HUB_LOCAL_POWER 0 1728 #define HUB_C_HUB_OVER_CURRENT 1 1729 #define HUB_PORT_CONNECTION 0 1730 #define HUB_PORT_ENABLE 1 1731 #define HUB_PORT_SUSPEND 2 1732 #define HUB_PORT_OVER_CURRENT 3 1733 #define HUB_PORT_RESET 4 1734 #define HUB_PORT_POWER 8 1735 #define HUB_PORT_LOW_SPEED 9 1736 #define HUB_C_PORT_CONNECTION 16 1737 #define HUB_C_PORT_ENABLE 17 1738 #define HUB_C_PORT_SUSPEND 18 1739 #define HUB_C_PORT_OVER_CURRENT 19 1740 #define HUB_C_PORT_RESET 20 1741 #endif 1742 1743 /* USB descriptor type */ 1744 #ifndef USB_DESCR_TYP_DEVICE 1745 #define USB_DESCR_TYP_DEVICE 0x01 1746 #define USB_DESCR_TYP_CONFIG 0x02 1747 #define USB_DESCR_TYP_STRING 0x03 1748 #define USB_DESCR_TYP_INTERF 0x04 1749 #define USB_DESCR_TYP_ENDP 0x05 1750 #define USB_DESCR_TYP_QUALIF 0x06 1751 #define USB_DESCR_TYP_SPEED 0x07 1752 #define USB_DESCR_TYP_OTG 0x09 1753 #define USB_DESCR_TYP_HID 0x21 1754 #define USB_DESCR_TYP_REPORT 0x22 1755 #define USB_DESCR_TYP_PHYSIC 0x23 1756 #define USB_DESCR_TYP_CS_INTF 0x24 1757 #define USB_DESCR_TYP_CS_ENDP 0x25 1758 #define USB_DESCR_TYP_HUB 0x29 1759 #endif 1760 1761 /* USB device class */ 1762 #ifndef USB_DEV_CLASS_HUB 1763 #define USB_DEV_CLASS_RESERVED 0x00 1764 #define USB_DEV_CLASS_AUDIO 0x01 1765 #define USB_DEV_CLASS_COMMUNIC 0x02 1766 #define USB_DEV_CLASS_HID 0x03 1767 #define USB_DEV_CLASS_MONITOR 0x04 1768 #define USB_DEV_CLASS_PHYSIC_IF 0x05 1769 #define USB_DEV_CLASS_POWER 0x06 1770 #define USB_DEV_CLASS_PRINTER 0x07 1771 #define USB_DEV_CLASS_STORAGE 0x08 1772 #define USB_DEV_CLASS_HUB 0x09 1773 #define USB_DEV_CLASS_VEN_SPEC 0xFF 1774 #endif 1775 1776 /* USB endpoint type and attributes */ 1777 #ifndef USB_ENDP_TYPE_MASK 1778 #define USB_ENDP_DIR_MASK 0x80 1779 #define USB_ENDP_ADDR_MASK 0x0F 1780 #define USB_ENDP_TYPE_MASK 0x03 1781 #define USB_ENDP_TYPE_CTRL 0x00 1782 #define USB_ENDP_TYPE_ISOCH 0x01 1783 #define USB_ENDP_TYPE_BULK 0x02 1784 #define USB_ENDP_TYPE_INTER 0x03 1785 #endif 1786 1787 #ifndef USB_DEVICE_ADDR 1788 #define USB_DEVICE_ADDR 0x02 /* 默认的USB设备地址 */ 1789 #endif 1790 #ifndef DEFAULT_ENDP0_SIZE 1791 #define DEFAULT_ENDP0_SIZE 8 /* default maximum packet size for endpoint 0 */ 1792 #endif 1793 #ifndef MAX_PACKET_SIZE 1794 #define MAX_PACKET_SIZE 64 /* maximum packet size */ 1795 #endif 1796 #ifndef USB_BO_CBW_SIZE 1797 #define USB_BO_CBW_SIZE 0x1F /* 命令块CBW的总长度 */ 1798 #define USB_BO_CSW_SIZE 0x0D /* 命令状态块CSW的总长度 */ 1799 #endif 1800 #ifndef USB_BO_CBW_SIG 1801 #define USB_BO_CBW_SIG 0x43425355 /* 命令块CBW识别标志'USBC' */ 1802 #define USB_BO_CSW_SIG 0x53425355 /* 命令状态块CSW识别标志'USBS' */ 1803 #endif 1804 1805 //#define __PACKED 1806 #ifndef __PACKED 1807 #define __PACKED __packed 1808 #endif 1809 1810 __PACKED typedef struct _USB_SETUP_REQ { 1811 UINT8 bRequestType; 1812 UINT8 bRequest; 1813 UINT16 wValue; 1814 UINT16 wIndex; 1815 UINT16 wLength; 1816 } USB_SETUP_REQ, *PUSB_SETUP_REQ; 1817 1818 1819 __PACKED typedef struct _USB_DEVICE_DESCR { 1820 UINT8 bLength; 1821 UINT8 bDescriptorType; 1822 UINT16 bcdUSB; 1823 UINT8 bDeviceClass; 1824 UINT8 bDeviceSubClass; 1825 UINT8 bDeviceProtocol; 1826 UINT8 bMaxPacketSize0; 1827 UINT16 idVendor; 1828 UINT16 idProduct; 1829 UINT16 bcdDevice; 1830 UINT8 iManufacturer; 1831 UINT8 iProduct; 1832 UINT8 iSerialNumber; 1833 UINT8 bNumConfigurations; 1834 } USB_DEV_DESCR, *PUSB_DEV_DESCR; 1835 1836 1837 __PACKED typedef struct _USB_CONFIG_DESCR { 1838 UINT8 bLength; 1839 UINT8 bDescriptorType; 1840 UINT16 wTotalLength; 1841 UINT8 bNumInterfaces; 1842 UINT8 bConfigurationValue; 1843 UINT8 iConfiguration; 1844 UINT8 bmAttributes; 1845 UINT8 MaxPower; 1846 } USB_CFG_DESCR, *PUSB_CFG_DESCR; 1847 1848 1849 __PACKED typedef struct _USB_INTERF_DESCR { 1850 UINT8 bLength; 1851 UINT8 bDescriptorType; 1852 UINT8 bInterfaceNumber; 1853 UINT8 bAlternateSetting; 1854 UINT8 bNumEndpoints; 1855 UINT8 bInterfaceClass; 1856 UINT8 bInterfaceSubClass; 1857 UINT8 bInterfaceProtocol; 1858 UINT8 iInterface; 1859 } USB_ITF_DESCR, *PUSB_ITF_DESCR; 1860 1861 1862 __PACKED typedef struct _USB_ENDPOINT_DESCR { 1863 UINT8 bLength; 1864 UINT8 bDescriptorType; 1865 UINT8 bEndpointAddress; 1866 UINT8 bmAttributes; 1867 UINT16 wMaxPacketSize; 1868 UINT8 bInterval; 1869 } USB_ENDP_DESCR, *PUSB_ENDP_DESCR; 1870 1871 1872 __PACKED typedef struct _USB_CONFIG_DESCR_LONG { 1873 USB_CFG_DESCR cfg_descr; 1874 USB_ITF_DESCR itf_descr; 1875 USB_ENDP_DESCR endp_descr[1]; 1876 } USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; 1877 1878 typedef USB_CFG_DESCR_LONG *PXUSB_CFG_DESCR_LONG; 1879 1880 __PACKED typedef struct _USB_HUB_DESCR { 1881 UINT8 bDescLength; 1882 UINT8 bDescriptorType; 1883 UINT8 bNbrPorts; 1884 UINT8 wHubCharacteristicsL; 1885 UINT8 wHubCharacteristicsH; 1886 UINT8 bPwrOn2PwrGood; 1887 UINT8 bHubContrCurrent; 1888 UINT8 DeviceRemovable; 1889 UINT8 PortPwrCtrlMask; 1890 } USB_HUB_DESCR, *PUSB_HUB_DESCR; 1891 1892 typedef USB_HUB_DESCR *PXUSB_HUB_DESCR; 1893 1894 __PACKED typedef struct _USB_HID_DESCR { 1895 UINT8 bLength; 1896 UINT8 bDescriptorType; 1897 UINT16 bcdHID; 1898 UINT8 bCountryCode; 1899 UINT8 bNumDescriptors; 1900 UINT8 bDescriptorTypeX; 1901 UINT8 wDescriptorLengthL; 1902 UINT8 wDescriptorLengthH; 1903 } USB_HID_DESCR, *PUSB_HID_DESCR; 1904 1905 typedef USB_HID_DESCR *PXUSB_HID_DESCR; 1906 1907 1908 __PACKED typedef struct _UDISK_BOC_CBW { /* command of BulkOnly USB-FlashDisk */ 1909 UINT32 mCBW_Sig; 1910 UINT32 mCBW_Tag; 1911 UINT32 mCBW_DataLen; /* uppest byte of data length, always is 0 */ 1912 UINT8 mCBW_Flag; /* transfer direction and etc. */ 1913 UINT8 mCBW_LUN; 1914 UINT8 mCBW_CB_Len; /* length of command block */ 1915 UINT8 mCBW_CB_Buf[16]; /* command block buffer */ 1916 } UDISK_BOC_CBW, *PUDISK_BOC_CBW; 1917 1918 typedef UDISK_BOC_CBW *PXUDISK_BOC_CBW; 1919 1920 __PACKED typedef struct _UDISK_BOC_CSW { /* status of BulkOnly USB-FlashDisk */ 1921 UINT32 mCSW_Sig; 1922 UINT32 mCSW_Tag; 1923 UINT32 mCSW_Residue; /* return: remainder bytes */ /* uppest byte of remainder length, always is 0 */ 1924 UINT8 mCSW_Status; /* return: result status */ 1925 } UDISK_BOC_CSW, *PUDISK_BOC_CSW; 1926 1927 typedef UDISK_BOC_CSW *PXUDISK_BOC_CSW; 1928 1929 1930 #ifdef __cplusplus 1931 } 1932 #endif 1933 1934 #endif // __USB_TYPE__ 1935