1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_rcc.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_RCC_H 22 #define __REG_RCC_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 40 41 42 43 44 //////////////////////////////////////////////////////////////////////////////// 45 /// @brief RCC Base Address Definition 46 //////////////////////////////////////////////////////////////////////////////// 47 #define RCC_BASE (AHBPERIPH_BASE + 0x1000) ///< Base Address: 0x40021000 48 49 50 51 52 53 //////////////////////////////////////////////////////////////////////////////// 54 /// @brief RCC Register Structure Definition 55 //////////////////////////////////////////////////////////////////////////////// 56 typedef struct { 57 __IO u32 CR; ///< Control Register offset: 0x00 58 __IO u32 CFGR; ///< Configuration Register offset: 0x04 59 __IO u32 CIR; ///< Clock Interrupt Register offset: 0x08 60 __IO u32 AHB3RSTR; ///< Advanced High Performance Bus 3 Reset Register offset: 0x0C 61 __IO u32 AHB2RSTR; ///< Advanced High Performance Bus 2 Reset Register offset: 0x10 62 __IO u32 AHBRSTR; ///< Advanced High Performance Bus 1 Reset Register offset: 0x14 63 __IO u32 APB2RSTR; ///< Advanced Peripheral Bus 2 Reset Register offset: 0x18 64 __IO u32 APB1RSTR; ///< Advanced Peripheral Bus 1 Reset Register offset: 0x1C 65 __IO u32 AHB3ENR; ///< Advanced High Performance Bus 3 Enable Register offset: 0x20 66 __IO u32 AHB2ENR; ///< Advanced High Performance Bus 2 Enable Register offset: 0x24 67 union { 68 __IO u32 AHBENR; ///< Advanced High Performance Bus 1 Enable Register offset: 0x28 69 __IO u32 AHB1ENR; 70 }; 71 72 __IO u32 APB2ENR; ///< Advanced Peripheral Bus 2 Enable Register offset: 0x2C 73 __IO u32 APB1ENR; ///< Advanced Peripheral Bus 1 Enable Register offset: 0x30 74 75 76 __IO u32 BDCR; ///< Backup Domain Control Register offset: 0x34 77 __IO u32 CSR; ///< Control Status Register offset: 0x38 78 __IO u32 SYSCFGR; ///< System Configuration Register offset: 0x3C 79 __IO u32 CFGR2; ///< System Configuration Register offset: 0x40 80 __IO u32 ICSCR; ///< Internal clock source calibration register offset: 0x44 81 __IO u32 PLLCFGR; ///< PLL configures registers offset: 0x48 82 u32 Reserved1[13]; ///< Reserved space 83 __IO u32 HSIDLY; ///< HSI delay register offset: 0x80 84 __IO u32 HSEDLY; ///< HSE delay register offset: 0x84 85 __IO u32 PLLDLY; ///< PLL delay register offset: 0x88 86 } RCC_TypeDef; 87 88 89 //////////////////////////////////////////////////////////////////////////////// 90 /// @brief RCC type pointer Definition 91 //////////////////////////////////////////////////////////////////////////////// 92 #define RCC ((RCC_TypeDef*) RCC_BASE) 93 94 95 96 //////////////////////////////////////////////////////////////////////////////// 97 /// @brief RCC_CR Register Bit Definition 98 //////////////////////////////////////////////////////////////////////////////// 99 #define RCC_CR_HSION_Pos (0) 100 #define RCC_CR_HSION (0x01U << RCC_CR_HSION_Pos) ///< Internal High Speed clock enable 101 102 #define RCC_CR_HSIRDY_Pos (1) 103 #define RCC_CR_HSIRDY (0x01U << RCC_CR_HSIRDY_Pos) ///< Internal High Speed clock ready flag 104 105 106 107 #define RCC_CR_HSIDIV_Pos (11) 108 #define RCC_CR_HSIDIV_0 (0x00U << RCC_CR_HSIDIV_Pos) ///< HSI regardless of frequency 109 #define RCC_CR_HSIDIV_2 (0x01U << RCC_CR_HSIDIV_Pos) ///< HSI 2 frequency division 110 #define RCC_CR_HSIDIV_4 (0x02U << RCC_CR_HSIDIV_Pos) ///< HSI 4 frequency division 111 #define RCC_CR_HSIDIV_8 (0x03U << RCC_CR_HSIDIV_Pos) ///< HSI eight points and frequency 112 #define RCC_CR_HSIDIV_16 (0x04U << RCC_CR_HSIDIV_Pos) ///< HSI 16 points and frequency 113 #define RCC_CR_HSIDIV_32 (0x05U << RCC_CR_HSIDIV_Pos) ///< HSI 32 points and frequency 114 #define RCC_CR_HSIDIV_64 (0x06U << RCC_CR_HSIDIV_Pos) ///< HSI 64 frequency division 115 #define RCC_CR_HSIDIV_128 (0x07U << RCC_CR_HSIDIV_Pos) ///< HSI 128 frequency division 116 #define RCC_CR_HSEON_Pos (16) 117 #define RCC_CR_HSEON (0x01U << RCC_CR_HSEON_Pos) ///< External High Speed clock enable 118 #define RCC_CR_HSERDY_Pos (17) 119 #define RCC_CR_HSERDY (0x01U << RCC_CR_HSERDY_Pos) ///< External High Speed clock ready flag 120 #define RCC_CR_HSEBYP_Pos (18) 121 #define RCC_CR_HSEBYP (0x01U << RCC_CR_HSEBYP_Pos) ///< External High Speed clock Bypass 122 #define RCC_CR_CSSON_Pos (19) 123 #define RCC_CR_CSSON (0x01U << RCC_CR_CSSON_Pos) ///< Clock Security System enable 124 125 126 #define RCC_CR_PLLON_Pos (24) 127 #define RCC_CR_PLLON (0x01U << RCC_CR_PLLON_Pos) ///< PLL enable 128 #define RCC_CR_PLLRDY_Pos (25) 129 #define RCC_CR_PLLRDY (0x01U << RCC_CR_PLLRDY_Pos) ///< PLL clock ready flag 130 //////////////////////////////////////////////////////////////////////////////// 131 /// @brief RCC_CFGR Register Bit Definition 132 //////////////////////////////////////////////////////////////////////////////// 133 #define RCC_CFGR_SW_Pos (0) 134 #define RCC_CFGR_SW (0x03U << RCC_CFGR_SW_Pos) ///< SW[1:0] bits (System clock Switch) 135 #define RCC_CFGR_SW_HSI_DIV6 (0x00U << RCC_CFGR_SW_Pos) ///< HSI/6 selected as system clock 136 #define RCC_CFGR_SW_HSE (0x01U << RCC_CFGR_SW_Pos) ///< HSE selected as system clock 137 #define RCC_CFGR_SW_PLL (0x02U << RCC_CFGR_SW_Pos) ///< PLL selected as system clock 138 #define RCC_CFGR_SW_LSI (0x03U << RCC_CFGR_SW_Pos) ///< LSI selected as system clock 139 140 #define RCC_CFGR_SWS_Pos (2) 141 #define RCC_CFGR_SWS (0x03U << RCC_CFGR_SWS_Pos) ///< SWS[1:0] bits (System Clock Switch Status) 142 #define RCC_CFGR_SWS_HSI_DIV6 (0x00U << RCC_CFGR_SWS_Pos) ///< HSI/6 oscillator used as system clock 143 #define RCC_CFGR_SWS_HSE (0x01U << RCC_CFGR_SWS_Pos) ///< HSE oscillator used as system clock 144 #define RCC_CFGR_SWS_PLL (0x02U << RCC_CFGR_SWS_Pos) ///< PLL used as system clock 145 #define RCC_CFGR_SWS_LSI (0x03U << RCC_CFGR_SWS_Pos) ///< LSI used as system clock 146 147 #define RCC_CFGR_HPRE_Pos (4) 148 #define RCC_CFGR_HPRE (0x0FU << RCC_CFGR_HPRE_Pos) ///< HPRE[3:0] bits (AHB prescaler) 149 #define RCC_CFGR_PPRE_0 (0x01U << RCC_CFGR_HPRE_Pos) ///< Bit 0 150 #define RCC_CFGR_PPRE_1 (0x02U << RCC_CFGR_HPRE_Pos) ///< Bit 1 151 #define RCC_CFGR_PPRE_2 (0x04U << RCC_CFGR_HPRE_Pos) ///< Bit 2 152 #define RCC_CFGR_PPRE_3 (0x08U << RCC_CFGR_HPRE_Pos) ///< Bit 3 153 154 #define RCC_CFGR_HPRE_DIV1 (0x00U << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK not divided 155 #define RCC_CFGR_HPRE_DIV2 (0x08U << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 2 156 #define RCC_CFGR_HPRE_DIV4 (0x09U << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 4 157 #define RCC_CFGR_HPRE_DIV8 (0x0AU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 8 158 #define RCC_CFGR_HPRE_DIV16 (0x0BU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 16 159 #define RCC_CFGR_HPRE_DIV64 (0x0CU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 64 160 #define RCC_CFGR_HPRE_DIV128 (0x0DU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 128 161 #define RCC_CFGR_HPRE_DIV256 (0x0EU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 256 162 #define RCC_CFGR_HPRE_DIV512 (0x0FU << RCC_CFGR_HPRE_Pos) ///< AHB = FCLK = SYSCLK divided by 512 163 164 #define RCC_CFGR_PPRE1_Pos (8) 165 #define RCC_CFGR_PPRE1 (0x07U << RCC_CFGR_PPRE1_Pos) ///< PRE1[2:0] bits (APB1 prescaler) 166 #define RCC_CFGR_PPRE1_0 (0x01U << RCC_CFGR_PPRE1_Pos) ///< Bit 0 167 #define RCC_CFGR_PPRE1_1 (0x02U << RCC_CFGR_PPRE1_Pos) ///< Bit 1 168 #define RCC_CFGR_PPRE1_2 (0x04U << RCC_CFGR_PPRE1_Pos) ///< Bit 2 169 170 #define RCC_CFGR_PPRE1_DIV1 (0x00U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK not divided 171 #define RCC_CFGR_PPRE1_DIV2 (0x04U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 2 172 #define RCC_CFGR_PPRE1_DIV4 (0x05U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 4 173 #define RCC_CFGR_PPRE1_DIV8 (0x06U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 8 174 #define RCC_CFGR_PPRE1_DIV16 (0x07U << RCC_CFGR_PPRE1_Pos) ///< APB1 = HCLK divided by 16 175 176 #define RCC_CFGR_PPRE2_Pos (11) 177 #define RCC_CFGR_PPRE2 (0x07U << RCC_CFGR_PPRE2_Pos) ///< PRE2[2:0] bits (APB2 prescaler) 178 #define RCC_CFGR_PPRE2_0 (0x01U << RCC_CFGR_PPRE2_Pos) ///< Bit 0 179 #define RCC_CFGR_PPRE2_1 (0x02U << RCC_CFGR_PPRE2_Pos) ///< Bit 1 180 #define RCC_CFGR_PPRE2_2 (0x04U << RCC_CFGR_PPRE2_Pos) ///< Bit 2 181 182 #define RCC_CFGR_PPRE2_DIV1 (0x00U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK not divided 183 #define RCC_CFGR_PPRE2_DIV2 (0x04U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 2 184 #define RCC_CFGR_PPRE2_DIV4 (0x05U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 4 185 #define RCC_CFGR_PPRE2_DIV8 (0x06U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 8 186 #define RCC_CFGR_PPRE2_DIV16 (0x07U << RCC_CFGR_PPRE2_Pos) ///< APB2 = HCLK divided by 16 187 188 189 #define RCC_CFGR_USBPRE_Pos (22) 190 #define RCC_CFGR_USBPRE (0x03U << RCC_CFGR_USBPRE_Pos) ///< USB prescaler BIT[1:0] 191 192 #define RCC_CFGR_MCO_Pos (24) 193 #define RCC_CFGR_MCO (0x07U << RCC_CFGR_MCO_Pos) ///< MCO[2:0] bits (Microcontroller Clock Output) 194 #define RCC_CFGR_MCO_NOCLOCK (0x00U << RCC_CFGR_MCO_Pos) ///< No clock 195 #define RCC_CFGR_MCO_LSI (0x02U << RCC_CFGR_MCO_Pos) ///< LSI clock 196 #define RCC_CFGR_MCO_LSE (0x03U << RCC_CFGR_MCO_Pos) ///< LSE clock 197 #define RCC_CFGR_MCO_SYSCLK (0x04U << RCC_CFGR_MCO_Pos) ///< System clock selected 198 #define RCC_CFGR_MCO_HSI (0x05U << RCC_CFGR_MCO_Pos) ///< Internal 48 MHz RC oscillator clock selected 199 #define RCC_CFGR_MCO_HSE (0x06U << RCC_CFGR_MCO_Pos) ///< External 1-25 MHz oscillator clock selected 200 #define RCC_CFGR_MCO_PLL (0x07U << RCC_CFGR_MCO_Pos) ///< PLL clock divided by 2 selected 201 202 203 204 //////////////////////////////////////////////////////////////////////////////// 205 /// @brief RCC_CIR Register Bit Definition 206 //////////////////////////////////////////////////////////////////////////////// 207 #define RCC_CIR_LSIRDYF_Pos (0) 208 #define RCC_CIR_LSIRDYF (0x01U << RCC_CIR_LSIRDYF_Pos) ///< LSI Ready Interrupt flag 209 210 #define RCC_CIR_LSERDYF_Pos (1) 211 #define RCC_CIR_LSERDYF (0x01U << RCC_CIR_LSERDYF_Pos) ///< LSE Ready Interrupt flag 212 213 #define RCC_CIR_HSIRDYF_Pos (2) 214 #define RCC_CIR_HSIRDYF (0x01U << RCC_CIR_HSIRDYF_Pos) ///< HSI Ready Interrupt flag 215 #define RCC_CIR_HSERDYF_Pos (3) 216 #define RCC_CIR_HSERDYF (0x01U << RCC_CIR_HSERDYF_Pos) ///< HSE Ready Interrupt flag 217 218 #define RCC_CIR_PLLRDYF_Pos (4) 219 #define RCC_CIR_PLLRDYF (0x01U << RCC_CIR_PLLRDYF_Pos) ///< PLL Ready Interrupt flag 220 221 #define RCC_CIR_CSSF_Pos (7) 222 #define RCC_CIR_CSSF (0x01U << RCC_CIR_CSSF_Pos) ///< Clock Security System Interrupt flag 223 #define RCC_CIR_LSIRDYIE_Pos (8) 224 #define RCC_CIR_LSIRDYIE (0x01U << RCC_CIR_LSIRDYIE_Pos) ///< LSI Ready Interrupt Enable 225 226 #define RCC_CIR_LSERDYIE_Pos (9) 227 #define RCC_CIR_LSERDYIE (0x01U << RCC_CIR_LSERDYIE_Pos) ///< LSE Ready Interrupt Enable 228 229 #define RCC_CIR_HSIRDYIE_Pos (10) 230 #define RCC_CIR_HSIRDYIE (0x01U << RCC_CIR_HSIRDYIE_Pos) ///< HSI Ready Interrupt Enable 231 #define RCC_CIR_HSERDYIE_Pos (11) 232 #define RCC_CIR_HSERDYIE (0x01U << RCC_CIR_HSIRDYIE_Pos) ///< HSE Ready Interrupt Enable 233 234 #define RCC_CIR_PLLRDYIE_Pos (12) 235 #define RCC_CIR_PLLRDYIE (0x01U << RCC_CIR_PLLRDYIE_Pos) ///< PLL Ready Interrupt Enable 236 237 #define RCC_CIR_LSIRDYC_Pos (16) 238 #define RCC_CIR_LSIRDYC (0x01U << RCC_CIR_LSIRDYC_Pos) ///< LSI Ready Interrupt Clear 239 240 #define RCC_CIR_LSERDYC_Pos (17) 241 #define RCC_CIR_LSERDYC (0x01U << RCC_CIR_LSERDYC_Pos) ///< LSE Ready Interrupt Clear 242 243 #define RCC_CIR_HSIRDYC_Pos (18) 244 #define RCC_CIR_HSIRDYC (0x01U << RCC_CIR_HSIRDYC_Pos) ///< HSI Ready Interrupt Clear 245 #define RCC_CIR_HSERDYC_Pos (19) 246 #define RCC_CIR_HSERDYC (0x01U << RCC_CIR_HSERDYC_Pos) ///< HSE Ready Interrupt Clear 247 248 #define RCC_CIR_PLLRDYC_Pos (20) 249 #define RCC_CIR_PLLRDYC (0x01U << RCC_CIR_PLLRDYC_Pos) ///< PLL Ready Interrupt Clear 250 251 #define RCC_CIR_CSSC_Pos (23) 252 #define RCC_CIR_CSSC (0x01U << RCC_CIR_CSSC_Pos) ///< Clock Security System Interrupt Clear 253 254 //////////////////////////////////////////////////////////////////////////////// 255 /// @brief RCC_APB2RSTR Register Bit Definition 256 //////////////////////////////////////////////////////////////////////////////// 257 #define RCC_APB2RSTR_TIM1_Pos (0) 258 #define RCC_APB2RSTR_TIM1 (0x01U << RCC_APB2RSTR_TIM1_Pos) ///< TIM1 reset 259 #define RCC_APB2RSTR_TIM8_Pos (1) 260 #define RCC_APB2RSTR_TIM8 (0x01U << RCC_APB2RSTR_TIM8_Pos) ///< TIM8 reset 261 #define RCC_APB2RSTR_UART1_Pos (4) 262 #define RCC_APB2RSTR_UART1 (0x01U << RCC_APB2RSTR_UART1_Pos) ///< UART1 reset 263 #define RCC_APB2RSTR_UART6_Pos (5) 264 #define RCC_APB2RSTR_UART6 (0x01U << RCC_APB2RSTR_UART6_Pos) ///< UART6 reset 265 #define RCC_APB2RSTR_ADC1_Pos (8) 266 #define RCC_APB2RSTR_ADC1 (0x01U << RCC_APB2RSTR_ADC1_Pos) ///< ADC1 reset 267 #define RCC_APB2RSTR_ADC2_Pos (9) 268 #define RCC_APB2RSTR_ADC2 (0x01U << RCC_APB2RSTR_ADC2_Pos) ///< ADC2 reset 269 #define RCC_APB2RSTR_ADC3_Pos (10) 270 #define RCC_APB2RSTR_ADC3 (0x01U << RCC_APB2RSTR_ADC3_Pos) ///< ADC3 reset 271 #define RCC_APB2RSTR_SPI1_Pos (12) 272 #define RCC_APB2RSTR_SPI1 (0x01U << RCC_APB2RSTR_SPI1_Pos) ///< SPI1 reset 273 #define RCC_APB2RSTR_SYSCFG_Pos (14) 274 #define RCC_APB2RSTR_SYSCFG (0x01U << RCC_APB2RSTR_SYSCFG_Pos) ///< SYSCFG reset 275 #define RCC_APB2RSTR_COMP_Pos (15) 276 #define RCC_APB2RSTR_COMP (0x01U << RCC_APB2RSTR_COMP_Pos) ///< COMP reset 277 278 279 280 281 282 283 284 285 //////////////////////////////////////////////////////////////////////////////// 286 /// @brief RCC_AHB3RSTR Register Bit Definition 287 //////////////////////////////////////////////////////////////////////////////// 288 #define RCC_AHB3RSTR_FSMC_Pos (0) 289 #define RCC_AHB3RSTR_FSMC (0x01U << RCC_AHB3RSTR_FSMC_Pos) ///< FSMC reset 290 291 292 //////////////////////////////////////////////////////////////////////////////// 293 /// @brief RCC_APB1RSTR Register Bit Definition 294 //////////////////////////////////////////////////////////////////////////////// 295 #define RCC_APB1RSTR_TIM2_Pos (0) 296 #define RCC_APB1RSTR_TIM2 (0x01U << RCC_APB1RSTR_TIM2_Pos) ///< Timer 2 reset 297 #define RCC_APB1RSTR_TIM3_Pos (1) 298 #define RCC_APB1RSTR_TIM3 (0x01U << RCC_APB1RSTR_TIM3_Pos) ///< Timer 3 reset 299 300 #define RCC_APB1RSTR_TIM4_Pos (2) 301 #define RCC_APB1RSTR_TIM4 (0x01U << RCC_APB1RSTR_TIM4_Pos) ///< Timer 4 reset 302 #define RCC_APB1RSTR_TIM5_Pos (3) 303 #define RCC_APB1RSTR_TIM5 (0x01U << RCC_APB1RSTR_TIM5_Pos) ///< Timer 5 reset 304 #define RCC_APB1RSTR_TIM6_Pos (4) 305 #define RCC_APB1RSTR_TIM6 (0x01U << RCC_APB1RSTR_TIM6_Pos) ///< Timer 6 reset 306 #define RCC_APB1RSTR_TIM7_Pos (5) 307 #define RCC_APB1RSTR_TIM7 (0x01U << RCC_APB1RSTR_TIM7_Pos) ///< Timer 7 reset 308 309 #define RCC_APB1RSTR_WWDG_Pos (11) 310 #define RCC_APB1RSTR_WWDG (0x01U << RCC_APB1RSTR_WWDG_Pos) ///< Window Watchdog reset 311 #define RCC_APB1RSTR_SPI2_Pos (14) 312 #define RCC_APB1RSTR_SPI2 (0x01U << RCC_APB1RSTR_SPI2_Pos) ///< SPI 2 reset 313 #define RCC_APB1RSTR_SPI3_Pos (15) 314 #define RCC_APB1RSTR_SPI3 (0x01U << RCC_APB1RSTR_SPI3_Pos) ///< SPI 3 reset 315 316 #define RCC_APB1RSTR_UART2_Pos (17) 317 #define RCC_APB1RSTR_UART2 (0x01U << RCC_APB1RSTR_UART2_Pos) ///< UART 2 reset 318 #define RCC_APB1RSTR_UART3_Pos (18) 319 #define RCC_APB1RSTR_UART3 (0x01U << RCC_APB1RSTR_UART3_Pos) ///< UART 3 reset 320 #define RCC_APB1RSTR_UART4_Pos (19) 321 #define RCC_APB1RSTR_UART4 (0x01U << RCC_APB1RSTR_UART4_Pos) ///< UART 4 reset 322 #define RCC_APB1RSTR_UART5_Pos (20) 323 #define RCC_APB1RSTR_UART5 (0x01U << RCC_APB1RSTR_UART5_Pos) ///< UART 5 reset 324 #define RCC_APB1RSTR_I2C1_Pos (21) 325 #define RCC_APB1RSTR_I2C1 (0x01U << RCC_APB1RSTR_I2C1_Pos) ///< I2C 1 reset 326 #define RCC_APB1RSTR_I2C2_Pos (22) 327 #define RCC_APB1RSTR_I2C2 (0x01U << RCC_APB1RSTR_I2C2_Pos) ///< I2C 2 reset 328 329 #define RCC_APB1RSTR_CRS_Pos (24) 330 #define RCC_APB1RSTR_CRS (0x01U << RCC_APB1RSTR_CRS_Pos) ///< CRS reset 331 #define RCC_APB1RSTR_CAN_Pos (25) 332 #define RCC_APB1RSTR_CAN (0x01U << RCC_APB1RSTR_CAN_Pos) ///< CAN reset 333 334 #define RCC_APB1RSTR_BKP_Pos (27) 335 #define RCC_APB1RSTR_BKP (0x01U << RCC_APB1RSTR_BKP_Pos) ///< Backup interface reset 336 337 #define RCC_APB1RSTR_PWR_Pos (28) 338 #define RCC_APB1RSTR_PWR (0x01U << RCC_APB1RSTR_PWR_Pos) ///< Power interface reset 339 #define RCC_APB1RSTR_DAC_Pos (29) 340 #define RCC_APB1RSTR_DAC (0x01U << RCC_APB1RSTR_DAC_Pos) ///< DAC interface reset 341 342 343 #define RCC_APB1RSTR_UART7_Pos (30) 344 #define RCC_APB1RSTR_UART7 (0x01U << RCC_APB1RSTR_UART7_Pos) ///< UART7 reset 345 #define RCC_APB1RSTR_UART8_Pos (31) 346 #define RCC_APB1RSTR_UART8 (0x01U << RCC_APB1RSTR_UART8_Pos) ///< UART8 reset 347 348 //////////////////////////////////////////////////////////////////////////////// 349 /// @brief RCC_AHB2RSTR Register Bit Definition 350 //////////////////////////////////////////////////////////////////////////////// 351 #define RCC_AHB2RSTR_USBFS_Pos (7) 352 #define RCC_AHB2RSTR_USBFS (0x01U << RCC_AHB2RSTR_USBFS_Pos) ///< USBFS reset 353 //////////////////////////////////////////////////////////////////////////////// 354 /// @brief RCC_AHB3ENR Register Bit Definition 355 //////////////////////////////////////////////////////////////////////////////// 356 #define RCC_AHB3ENR_FSMC_Pos (0) 357 #define RCC_AHB3ENR_FSMC (0x01U << RCC_AHB3ENR_FSMC_Pos) ///< FSMC reset 358 359 //////////////////////////////////////////////////////////////////////////////// 360 /// @brief RCC_AHB2ENR Register Bit Definition 361 //////////////////////////////////////////////////////////////////////////////// 362 #define RCC_AHB2ENR_USBFS_Pos (7) 363 #define RCC_AHB2ENR_USBFS (0x01U << RCC_AHB2ENR_USBFS_Pos) ///< USBFS reset 364 365 //////////////////////////////////////////////////////////////////////////////// 366 /// @brief RCC_AHBENR Register Bit Definition 367 //////////////////////////////////////////////////////////////////////////////// 368 369 370 371 #define RCC_AHBENR_GPIOA_Pos (0) 372 #define RCC_AHBENR_GPIOA (0x01U << RCC_AHBENR_GPIOA_Pos) ///< GPIOA clock enable 373 #define RCC_AHBENR_GPIOB_Pos (1) 374 #define RCC_AHBENR_GPIOB (0x01U << RCC_AHBENR_GPIOB_Pos) ///< GPIOB clock enable 375 #define RCC_AHBENR_GPIOC_Pos (2) 376 #define RCC_AHBENR_GPIOC (0x01U << RCC_AHBENR_GPIOC_Pos) ///< GPIOC clock enable 377 #define RCC_AHBENR_GPIOD_Pos (3) 378 #define RCC_AHBENR_GPIOD (0x01U << RCC_AHBENR_GPIOD_Pos) ///< GPIOD clock enable 379 #define RCC_AHBENR_GPIOE_Pos (4) 380 #define RCC_AHBENR_GPIOE (0x01U << RCC_AHBENR_GPIOE_Pos) ///< GPIOE clock enable 381 #define RCC_AHBENR_GPIOF_Pos (5) 382 #define RCC_AHBENR_GPIOF (0x01U << RCC_AHBENR_GPIOF_Pos) ///< GPIOF clock enable 383 #define RCC_AHBENR_GPIOG_Pos (6) 384 #define RCC_AHBENR_GPIOG (0x01U << RCC_AHBENR_GPIOG_Pos) ///< GPIOG clock enable 385 #define RCC_AHBENR_GPIOH_Pos (7) 386 #define RCC_AHBENR_GPIOH (0x01U << RCC_AHBENR_GPIOH_Pos) ///< GPIOH clock enable 387 #define RCC_AHBENR_SDIO_Pos (10) 388 #define RCC_AHBENR_SDIO (0x01U << RCC_AHBENR_SDIO_Pos) ///< SDIO clock enable 389 #define RCC_AHBENR_CRC_Pos (12) 390 #define RCC_AHBENR_CRC (0x01U << RCC_AHBENR_CRC_Pos) ///< CRC clock enable 391 #define RCC_AHBENR_FLASH_Pos (13) 392 #define RCC_AHBENR_FLASH (0x01U << RCC_AHBENR_FLASH_Pos) ///< FLASH clock enable 393 #define RCC_AHBENR_SRAM_Pos (14) 394 #define RCC_AHBENR_SRAM (0x01U << RCC_AHBENR_SRAM_Pos) ///< SRAM clock enable 395 #define RCC_AHBENR_DMA1_Pos (21) 396 #define RCC_AHBENR_DMA1 (0x01U << RCC_AHBENR_DMA1_Pos) ///< DMA1 clock enable 397 #define RCC_AHBENR_DMA2_Pos (22) 398 #define RCC_AHBENR_DMA2 (0x01U << RCC_AHBENR_DMA2_Pos) ///< DMA2 clock enable 399 #define RCC_AHBENR_ETHMAC_Pos (25) 400 #define RCC_AHBENR_ETHMAC (0x01U << RCC_AHBENR_ETHMAC_Pos) ///< ETHMAC clock enable 401 //////////////////////////////////////////////////////////////////////////////// 402 /// @brief RCC_APB2ENR Register Bit Definition 403 //////////////////////////////////////////////////////////////////////////////// 404 #define RCC_APB2ENR_TIM1_Pos (0) 405 #define RCC_APB2ENR_TIM1 (0x01U << RCC_APB2ENR_TIM1_Pos) ///< TIM1 enable 406 #define RCC_APB2ENR_TIM8_Pos (1) 407 #define RCC_APB2ENR_TIM8 (0x01U << RCC_APB2ENR_TIM8_Pos) ///< TIM8 enable 408 #define RCC_APB2ENR_UART1_Pos (4) 409 #define RCC_APB2ENR_UART1 (0x01U << RCC_APB2ENR_UART1_Pos) ///< UART1 enable 410 #define RCC_APB2ENR_UART6_Pos (5) 411 #define RCC_APB2ENR_UART6 (0x01U << RCC_APB2ENR_UART6_Pos) ///< UART6 enable 412 #define RCC_APB2ENR_ADC1_Pos (8) 413 #define RCC_APB2ENR_ADC1 (0x01U << RCC_APB2ENR_ADC1_Pos) ///< ADC1 enable 414 #define RCC_APB2ENR_ADC2_Pos (9) 415 #define RCC_APB2ENR_ADC2 (0x01U << RCC_APB2ENR_ADC2_Pos) ///< ADC2 enable 416 #define RCC_APB2ENR_ADC3_Pos (10) 417 #define RCC_APB2ENR_ADC3 (0x01U << RCC_APB2ENR_ADC3_Pos) ///< ADC3 enable 418 #define RCC_APB2ENR_SPI1_Pos (12) 419 #define RCC_APB2ENR_SPI1 (0x01U << RCC_APB2ENR_SPI1_Pos) ///< SPI1 enable 420 #define RCC_APB2ENR_EXTI_Pos (14) 421 #define RCC_APB2ENR_EXTI (0x01U << RCC_APB2ENR_EXTI_Pos) ///< EXTI Block enable 422 #define RCC_APB2ENR_SYSCFG_Pos (14) 423 #define RCC_APB2ENR_SYSCFG (0x01U << RCC_APB2ENR_SYSCFG_Pos) ///< SYSCFG enable 424 #define RCC_APB2ENR_COMP_Pos (15) 425 #define RCC_APB2ENR_COMP (0x01U << RCC_APB2ENR_COMP_Pos) ///< COMP enable 426 //////////////////////////////////////////////////////////////////////////////// 427 /// @brief RCC_APB1ENR Register Bit Definition 428 //////////////////////////////////////////////////////////////////////////////// 429 #define RCC_APB1ENR_TIM2_Pos (0) 430 #define RCC_APB1ENR_TIM2 (0x01U << RCC_APB1ENR_TIM2_Pos) ///< Timer 2 clock enable 431 432 #define RCC_APB1ENR_TIM3_Pos (1) 433 #define RCC_APB1ENR_TIM3 (0x01U << RCC_APB1ENR_TIM3_Pos) ///< Timer 3 clock enabled 434 435 #define RCC_APB1ENR_TIM4_Pos (2) 436 #define RCC_APB1ENR_TIM4 (0x01U << RCC_APB1ENR_TIM4_Pos) ///< Timer 4 clock enable 437 438 439 #define RCC_APB1ENR_TIM5_Pos (3) 440 #define RCC_APB1ENR_TIM5 (0x01U << RCC_APB1ENR_TIM5_Pos) ///< TIM5 Timer clock enable 441 #define RCC_APB1ENR_TIM6_Pos (4) 442 #define RCC_APB1ENR_TIM6 (0x01U << RCC_APB1ENR_TIM6_Pos) ///< TIM6 Timer clock enable 443 #define RCC_APB1ENR_TIM7_Pos (5) 444 #define RCC_APB1ENR_TIM7 (0x01U << RCC_APB1ENR_TIM7_Pos) ///< TIM7 Timer clock enable 445 446 #define RCC_APB1ENR_WWDG_Pos (11) 447 #define RCC_APB1ENR_WWDG (0x01U << RCC_APB1ENR_WWDG_Pos) ///< Window Watchdog clock enable 448 449 450 #define RCC_APB1ENR_SPI2_Pos (14) 451 #define RCC_APB1ENR_SPI2 (0x01U << RCC_APB1ENR_SPI2_Pos) ///< SPI 2 clock enable 452 #define RCC_APB1ENR_SPI3_Pos (15) 453 #define RCC_APB1ENR_SPI3 (0x01U << RCC_APB1ENR_SPI3_Pos) ///< SPI 3 clock enable 454 455 #define RCC_APB1ENR_UART2_Pos (17) 456 #define RCC_APB1ENR_UART2 (0x01U << RCC_APB1ENR_UART2_Pos) ///< UART 2 clock enable 457 #define RCC_APB1ENR_UART3_Pos (18) 458 #define RCC_APB1ENR_UART3 (0x01U << RCC_APB1ENR_UART3_Pos) ///< UART 3 clock enable 459 #define RCC_APB1ENR_UART4_Pos (19) 460 #define RCC_APB1ENR_UART4 (0x01U << RCC_APB1ENR_UART4_Pos) ///< UART 4 clock enable 461 #define RCC_APB1ENR_UART5_Pos (20) 462 #define RCC_APB1ENR_UART5 (0x01U << RCC_APB1ENR_UART5_Pos) ///< UART 5 clock enable 463 #define RCC_APB1ENR_I2C1_Pos (21) 464 #define RCC_APB1ENR_I2C1 (0x01U << RCC_APB1ENR_I2C1_Pos) ///< I2C 1 clock enable 465 #define RCC_APB1ENR_I2C2_Pos (22) 466 #define RCC_APB1ENR_I2C2 (0x01U << RCC_APB1ENR_I2C2_Pos) ///< I2C 2 clock enable 467 #define RCC_APB1ENR_CRS_Pos (24) 468 #define RCC_APB1ENR_CRS (0x01U << RCC_APB1ENR_CRS_Pos) ///< CRS 4 clock enable 469 #define RCC_APB1ENR_CAN_Pos (25) 470 #define RCC_APB1ENR_CAN (0x01U << RCC_APB1ENR_CAN_Pos) ///< CAN 5 clock enable 471 472 473 474 #define RCC_APB1ENR_BKP_Pos (27) 475 #define RCC_APB1ENR_BKP (0x01U << RCC_APB1ENR_BKP_Pos) ///< Backup interface clock enable 476 477 #define RCC_APB1ENR_PWR_Pos (28) 478 #define RCC_APB1ENR_PWR (0x01U << RCC_APB1ENR_PWR_Pos) ///< Power interface clock enable 479 480 #define RCC_APB1ENR_DBGMCU_Pos (28) 481 #define RCC_APB1ENR_DBGMCU (0x01U << RCC_APB1ENR_DBGMCU_Pos) ///< DBGMCU clock enable 482 483 484 #define RCC_APB1ENR_DAC_Pos (29) 485 #define RCC_APB1ENR_DAC (0x01U << RCC_APB1ENR_DAC_Pos) ///< DAC interface clock enable 486 #define RCC_APB1ENR_UART7_Pos (30) 487 #define RCC_APB1ENR_UART7 (0x01U << RCC_APB1ENR_UART7_Pos) ///< UART7 interface clock enable 488 #define RCC_APB1ENR_UART8_Pos (31) 489 #define RCC_APB1ENR_UART8 (0x01U << RCC_APB1ENR_UART8_Pos) ///< UART8 interface clock enable 490 //////////////////////////////////////////////////////////////////////////////// 491 /// @brief RCC_BDCR Register Bit Definition 492 //////////////////////////////////////////////////////////////////////////////// 493 #define RCC_BDCR_LSEON_Pos (0) 494 #define RCC_BDCR_LSEON (0x01U << RCC_BDCR_LSEON_Pos) ///< External Low Speed oscillator enable 495 #define RCC_BDCR_LSERDY_Pos (1) 496 #define RCC_BDCR_LSERDY (0x01U << RCC_BDCR_LSERDY_Pos) ///< External Low Speed oscillator Ready 497 #define RCC_BDCR_LSEBYP_Pos (2) 498 #define RCC_BDCR_LSEBYP (0x01U << RCC_BDCR_LSEBYP_Pos) ///< External Low Speed oscillator Bypass 499 500 #define RCC_BDCR_RTCSEL_Pos (8) 501 #define RCC_BDCR_RTCSEL (0x03U << RCC_BDCR_RTCSEL_Pos) ///< RTCSEL[1:0] bits (RTC clock source selection) 502 #define RCC_BDCR_RTCSEL_LSE (0x01U << RCC_BDCR_RTCSEL_Pos) ///< LSE oscillator clock used as RTC clock 503 #define RCC_BDCR_RTCSEL_LSI (0x02U << RCC_BDCR_RTCSEL_Pos) ///< LSI oscillator clock used as RTC clock 504 #define RCC_BDCR_RTCSEL_HSE (0x03U << RCC_BDCR_RTCSEL_Pos) ///< HSE oscillator clock divided by 128 used as RTC clock 505 506 #define RCC_BDCR_RTCEN_Pos (15) 507 #define RCC_BDCR_RTCEN (0x01U << RCC_BDCR_RTCEN_Pos) ///< RTC clock enable 508 #define RCC_BDCR_BDRST_Pos (16) 509 #define RCC_BDCR_BDRST (0x01U << RCC_BDCR_BDRST_Pos) ///< Backup domain software reset 510 #define RCC_BDCR_DBP_Pos (24) 511 #define RCC_BDCR_DBP (0x01U << RCC_BDCR_DBP_Pos) ///< DBP clock enable 512 513 514 //////////////////////////////////////////////////////////////////////////////// 515 /// @brief RCC_CSR Register Bit Definition 516 //////////////////////////////////////////////////////////////////////////////// 517 #define RCC_CSR_LSION_Pos (0) 518 #define RCC_CSR_LSION (0x01U << RCC_CSR_LSION_Pos) ///< Internal Low Speed oscillator enable 519 #define RCC_CSR_LSIRDY_Pos (1) 520 #define RCC_CSR_LSIRDY (0x01U << RCC_CSR_LSIRDY_Pos) ///< Internal Low Speed oscillator Ready 521 #define RCC_CSR_LSIOENLV_Pos (5) 522 #define RCC_CSR_LSIOENLV (0x01U << RCC_CSR_LSIOENLV_Pos) ///< LSI output enable lower voltage 523 #define RCC_CSR_PVDRSTEN_Pos (6) 524 #define RCC_CSR_PVDRSTEN (0x01U << RCC_CSR_PVDRSTEN_Pos) ///< PVD reset enable 525 #define RCC_CSR_LOCKUPEN_Pos (7) 526 #define RCC_CSR_LOCKUPEN (0x01U << RCC_CSR_LOCKUPEN_Pos) ///< CPU lockup reset enable 527 #define RCC_CSR_VDTRSTNEN_Pos (8) 528 #define RCC_CSR_VDTRSTNEN (0x01U << RCC_CSR_VDTRSTNEN_Pos) ///< Voltage detect reset enable 529 #define RCC_CSR_VDTRSTF_Pos (21) 530 #define RCC_CSR_VDTRSTF (0x01U << RCC_CSR_VDTRSTF_Pos) ///< Voltage detect reset flag 531 #define RCC_CSR_PVDRSTF_Pos (22) 532 #define RCC_CSR_PVDRSTF (0x01U << RCC_CSR_PVDRSTF_Pos) ///< PVD reset flag 533 #define RCC_CSR_LOCKUPF_Pos (23) 534 #define RCC_CSR_LOCKUPF (0x01U << RCC_CSR_LOCKUPF_Pos) ///< CPU lockup reset flag 535 536 #define RCC_CSR_RMVF_Pos (24) 537 #define RCC_CSR_RMVF (0x01U << RCC_CSR_RMVF_Pos) ///< Remove reset flag 538 #define RCC_CSR_PINRSTF_Pos (26) 539 #define RCC_CSR_PINRSTF (0x01U << RCC_CSR_PINRSTF_Pos) ///< PIN reset flag 540 541 #define RCC_CSR_PORRSTF_Pos (27) 542 #define RCC_CSR_PORRSTF (0x01U << RCC_CSR_PORRSTF_Pos) ///< POR/PDR reset flag 543 544 #define RCC_CSR_SFTRSTF_Pos (28) 545 #define RCC_CSR_SFTRSTF (0x01U << RCC_CSR_SFTRSTF_Pos) ///< Software Reset flag 546 547 #define RCC_CSR_IWDGRSTF_Pos (29) 548 #define RCC_CSR_IWDGRSTF (0x01U << RCC_CSR_IWDGRSTF_Pos) ///< Independent Watchdog reset flag 549 550 #define RCC_CSR_WWDGRSTF_Pos (30) 551 #define RCC_CSR_WWDGRSTF (0x01U << RCC_CSR_WWDGRSTF_Pos) ///< Window watchdog reset flag 552 553 //////////////////////////////////////////////////////////////////////////////// 554 /// @brief RCC_AHBRSTR Register Bit Definition 555 //////////////////////////////////////////////////////////////////////////////// 556 #define RCC_AHBRSTR_GPIOA_Pos (0) 557 #define RCC_AHBRSTR_GPIOA (0x01U << RCC_AHBRSTR_GPIOA_Pos) ///< GPIOA clock reset 558 #define RCC_AHBRSTR_GPIOB_Pos (1) 559 #define RCC_AHBRSTR_GPIOB (0x01U << RCC_AHBRSTR_GPIOB_Pos) ///< GPIOB clock reset 560 #define RCC_AHBRSTR_GPIOC_Pos (2) 561 #define RCC_AHBRSTR_GPIOC (0x01U << RCC_AHBRSTR_GPIOC_Pos) ///< GPIOC clock reset 562 #define RCC_AHBRSTR_GPIOD_Pos (3) 563 #define RCC_AHBRSTR_GPIOD (0x01U << RCC_AHBRSTR_GPIOD_Pos) ///< GPIOD clock reset 564 #define RCC_AHBRSTR_GPIOE_Pos (4) 565 #define RCC_AHBRSTR_GPIOE (0x01U << RCC_AHBRSTR_GPIOE_Pos) ///< GPIOE clock reset 566 #define RCC_AHBRSTR_GPIOF_Pos (5) 567 #define RCC_AHBRSTR_GPIOF (0x01U << RCC_AHBRSTR_GPIOF_Pos) ///< GPIOF clock reset 568 #define RCC_AHBRSTR_GPIOG_Pos (6) 569 #define RCC_AHBRSTR_GPIOG (0x01U << RCC_AHBRSTR_GPIOG_Pos) ///< GPIOG clock reset 570 #define RCC_AHBRSTR_GPIOH_Pos (7) 571 #define RCC_AHBRSTR_GPIOH (0x01U << RCC_AHBRSTR_GPIOH_Pos) ///< GPIOH clock reset 572 #define RCC_AHBRSTR_SDIO_Pos (10) 573 #define RCC_AHBRSTR_SDIO (0x01U << RCC_AHBRSTR_SDIO_Pos) ///< SDIO clock reset 574 #define RCC_AHBRSTR_CRC_Pos (12) 575 #define RCC_AHBRSTR_CRC (0x01U << RCC_AHBRSTR_CRC_Pos) ///< CRC clock reset 576 #define RCC_AHBRSTR_DMA1_Pos (21) 577 #define RCC_AHBRSTR_DMA1 (0x01U << RCC_AHBRSTR_DMA1_Pos) ///< DMA1 clock reset 578 #define RCC_AHBRSTR_DMA2_Pos (22) 579 #define RCC_AHBRSTR_DMA2 (0x01U << RCC_AHBRSTR_DMA2_Pos) ///< DMA2 clock reset 580 #define RCC_AHBRSTR_ETHMAC_Pos (25) 581 #define RCC_AHBRSTR_ETHMAC (0x01U << RCC_AHBRSTR_ETHMAC_Pos) ///< ETHMAC clock reset 582 //////////////////////////////////////////////////////////////////////////////// 583 /// @brief RCC_SYSCFG Register Bit Definition 584 //////////////////////////////////////////////////////////////////////////////// 585 586 #define RCC_SYSCFG_PROGCHECKEN_Pos (0) 587 #define RCC_SYSCFG_PROGCHECKEN (0x01U << RCC_SYSCFG_PROGCHECKEN_Pos) ///< Whether to check the number in Flash when writing to Flash 588 #define RCC_SYSCFG_SECTOR1KCFG_Pos (1) 589 #define RCC_SYSCFG_SECTOR1KCFG (0x01U << RCC_SYSCFG_SECTOR1KCFG_Pos) ///< The size of the Flash page when erased. 590 #define RCC_SYSCFG_DATAPREFETCH_Pos (2) 591 #define RCC_SYSCFG_DATAPREFETCH (0x01U << RCC_SYSCFG_DATAPREFETCH_Pos) ///< DATA prefetch module enable bit 592 #define RCC_SYSCFG_PAD_OSC_TRIM_Pos (8) 593 #define RCC_SYSCFG_PAD_OSC_TRIM (0x1FU << RCC_SYSCFG_PAD_OSC_TRIM_Pos) ///< Calibration value of external crystal vibration 594 #define RCC_SYSCFG_OSC_LPFEN_Pos (14) 595 #define RCC_SYSCFG_OSC_LPFEN (0x01U << RCC_SYSCFG_OSC_LPFEN_Pos) ///< External crystal oscillator low pass filtering enables 596 //////////////////////////////////////////////////////////////////////////////// 597 /// @brief RCC_CFGR2 Register Bit Definition 598 //////////////////////////////////////////////////////////////////////////////// 599 #define RCC_CFGR2_TIMADVCKSEL_Pos (1) 600 #define RCC_CFGR2_TIMADVCKSEL (0x01U << RCC_CFGR2_TIMADVCKSEL_Pos) ///< TIMADV_CKSEL 601 #define RCC_CFGR2_TIMADV_PRE_Pos (1) ///< 602 #define RCC_CFGR2_TIMADV_PRE (0x07U << RCC_CFGR2_TIMADV_PRE_Pos) ///< SYSCLK's advance points are controlled by the software Frequency coefficient 603 #define RCC_CFGR2_FSMC_PRE_Pos (8) 604 #define RCC_CFGR2_FSMC_PRE (0x1FU << RCC_CFGR2_FSMC_PRE_Pos) ///< FSMC Output clock frequency division factor 605 #define RCC_CFGR2_APB1_CLK_HV_PRE_Pos (16) 606 #define RCC_CFGR2_APB1_CLK_HV_PRE (0x0FU << RCC_CFGR2_APB1_CLK_HV_PRE_Pos) ///< APB1 Output clock frequency division factor 607 //////////////////////////////////////////////////////////////////////////////// 608 /// @brief RCC_ICSCR Register Bit Definition 609 //////////////////////////////////////////////////////////////////////////////// 610 #define RCC_ICSCR_TIME_CRS_SEL_Pos (0) 611 #define RCC_ICSCR_TIME_CRS_SEL (0x01U << RCC_ICSCR_TIME_CRS_SEL_Pos) ///< Whether to use the CRS module as source 612 #define RCC_ICSCR_HSI_CAL_SEL_Pos (11) ///< 613 #define RCC_ICSCR_HSI_CAL_SEL (0x1FU << RCC_ICSCR_HSI_CAL_SEL_Pos) ///< Select the internal high speed clock calibration value 614 #define RCC_ICSCR_HSI_CAL_SFT_Pos (16) 615 #define RCC_ICSCR_HSI_CAL_SFT (0x3FU << RCC_ICSCR_HSI_CAL_SFT_Pos) ///< Internal high-speed clock calibration 616 //////////////////////////////////////////////////////////////////////////////// 617 /// @brief RCC_PLLCFGR Register Bit Definition 618 //////////////////////////////////////////////////////////////////////////////// 619 #define RCC_PLLCFGR_PLLSRC_Pos (0) 620 #define RCC_PLLCFGR_PLLSRC (0x01U << RCC_PLLCFGR_PLLSRC_Pos) ///< PLL entry clock source 621 #define RCC_PLLCFGR_PLLXTPRE_Pos (1) ///< 622 #define RCC_PLLCFGR_PLLXTPRE (0x01U << RCC_PLLCFGR_PLLXTPRE_Pos) ///< HSE divider for PLL entry 623 #define RCC_PLLCFGR_PLL_ICTRL_Pos (2) 624 #define RCC_PLLCFGR_PLL_ICTRL (0x03U << RCC_PLLCFGR_PLL_ICTRL_Pos) ///< PLL CP current control signals 625 #define RCC_PLLCFGR_PLL_LDS_Pos (4) 626 #define RCC_PLLCFGR_PLL_LDS (0x03U << RCC_PLLCFGR_PLL_LDS_Pos) ///< PLL lock detector accuracy select 627 #define RCC_PLLCFGR_PLL_DP_Pos (8) ///< 628 #define RCC_PLLCFGR_PLL_DP (0x07U << RCC_PLLCFGR_PLL_DP_Pos) ///< PLL divider factor DP 629 #define RCC_PLLCFGR_PLL_DN_Pos (16) 630 #define RCC_PLLCFGR_PLL_DN (0x7FU << RCC_PLLCFGR_PLL_DN_Pos) ///< PLL divider factor DN 631 //////////////////////////////////////////////////////////////////////////////// 632 /// @brief RCC_HSIDLY Register Bit Definition 633 //////////////////////////////////////////////////////////////////////////////// 634 #define RCC_HSIDLY_HSI_EQU_CNT (0xFFU) ///< HSI delay time 635 //////////////////////////////////////////////////////////////////////////////// 636 /// @brief RCC_HSEDLY Register Bit Definition 637 //////////////////////////////////////////////////////////////////////////////// 638 #define RCC_HSEDLY_HSI_EQU_CNT (0xFFFFU) ///< HSE delay time 639 //////////////////////////////////////////////////////////////////////////////// 640 /// @brief RCC_PLLDLY Register Bit Definition 641 //////////////////////////////////////////////////////////////////////////////// 642 #define RCC_PLLDLY_HSI_EQU_CNT (0xFFU) ///< PLL delay time 643 644 645 646 /// @} 647 648 /// @} 649 650 /// @} 651 652 //////////////////////////////////////////////////////////////////////////////// 653 #endif 654 //////////////////////////////////////////////////////////////////////////////// 655