1 /********************************** (C) COPYRIGHT  *******************************
2 * File Name          : ch32f20x_rcc.h
3 * Author             : WCH
4 * Version            : V1.0.0
5 * Date               : 2021/08/08
6 * Description        : This file provides all the RCC firmware functions.
7 *******************************************************************************/
8 #ifndef __CH32F20x_RCC_H
9 #define __CH32F20x_RCC_H
10 
11 #ifdef __cplusplus
12  extern "C" {
13 #endif
14 
15 #include "ch32f20x.h"
16 
17 /* RCC_Exported_Types */
18 typedef struct
19 {
20   uint32_t SYSCLK_Frequency;  /* returns SYSCLK clock frequency expressed in Hz */
21   uint32_t HCLK_Frequency;    /* returns HCLK clock frequency expressed in Hz */
22   uint32_t PCLK1_Frequency;   /* returns PCLK1 clock frequency expressed in Hz */
23   uint32_t PCLK2_Frequency;   /* returns PCLK2 clock frequency expressed in Hz */
24   uint32_t ADCCLK_Frequency;  /* returns ADCCLK clock frequency expressed in Hz */
25 }RCC_ClocksTypeDef;
26 
27 /* HSE_configuration */
28 #define RCC_HSE_OFF                      ((uint32_t)0x00000000)
29 #define RCC_HSE_ON                       ((uint32_t)0x00010000)
30 #define RCC_HSE_Bypass                   ((uint32_t)0x00040000)
31 
32 /* PLL_entry_clock_source */
33 #define RCC_PLLSource_HSI_Div2           ((uint32_t)0x00000000)
34 #define RCC_PLLSource_HSE_Div1           ((uint32_t)0x00010000)
35 #define RCC_PLLSource_HSE_Div2           ((uint32_t)0x00030000)
36 
37 /* PLL_multiplication_factor for other CH32F20x  */
38 #define RCC_PLLMul_2                     ((uint32_t)0x00000000)
39 #define RCC_PLLMul_3                     ((uint32_t)0x00040000)
40 #define RCC_PLLMul_4                     ((uint32_t)0x00080000)
41 #define RCC_PLLMul_5                     ((uint32_t)0x000C0000)
42 #define RCC_PLLMul_6                     ((uint32_t)0x00100000)
43 #define RCC_PLLMul_7                     ((uint32_t)0x00140000)
44 #define RCC_PLLMul_8                     ((uint32_t)0x00180000)
45 #define RCC_PLLMul_9                     ((uint32_t)0x001C0000)
46 #define RCC_PLLMul_10                    ((uint32_t)0x00200000)
47 #define RCC_PLLMul_11                    ((uint32_t)0x00240000)
48 #define RCC_PLLMul_12                    ((uint32_t)0x00280000)
49 #define RCC_PLLMul_13                    ((uint32_t)0x002C0000)
50 #define RCC_PLLMul_14                    ((uint32_t)0x00300000)
51 #define RCC_PLLMul_15                    ((uint32_t)0x00340000)
52 #define RCC_PLLMul_16                    ((uint32_t)0x00380000)
53 #define RCC_PLLMul_18                    ((uint32_t)0x003C0000)
54 
55 /* PLL_multiplication_factor for CH32F207 */
56 #define RCC_PLLMul_18_EXTEN              ((uint32_t)0x00000000)
57 #define RCC_PLLMul_3_EXTEN               ((uint32_t)0x00040000)
58 #define RCC_PLLMul_4_EXTEN               ((uint32_t)0x00080000)
59 #define RCC_PLLMul_5_EXTEN               ((uint32_t)0x000C0000)
60 #define RCC_PLLMul_6_EXTEN               ((uint32_t)0x00100000)
61 #define RCC_PLLMul_7_EXTEN               ((uint32_t)0x00140000)
62 #define RCC_PLLMul_8_EXTEN               ((uint32_t)0x00180000)
63 #define RCC_PLLMul_9_EXTEN               ((uint32_t)0x001C0000)
64 #define RCC_PLLMul_10_EXTEN              ((uint32_t)0x00200000)
65 #define RCC_PLLMul_11_EXTEN              ((uint32_t)0x00240000)
66 #define RCC_PLLMul_12_EXTEN              ((uint32_t)0x00280000)
67 #define RCC_PLLMul_13_EXTEN              ((uint32_t)0x002C0000)
68 #define RCC_PLLMul_14_EXTEN              ((uint32_t)0x00300000)
69 #define RCC_PLLMul_6_5_EXTEN             ((uint32_t)0x00340000)
70 #define RCC_PLLMul_15_EXTEN              ((uint32_t)0x00380000)
71 #define RCC_PLLMul_16_EXTEN              ((uint32_t)0x003C0000)
72 
73 
74 /* PREDIV1_division_factor */
75 #define RCC_PREDIV1_Div1                 ((uint32_t)0x00000000)
76 #define RCC_PREDIV1_Div2                 ((uint32_t)0x00000001)
77 #define RCC_PREDIV1_Div3                 ((uint32_t)0x00000002)
78 #define RCC_PREDIV1_Div4                 ((uint32_t)0x00000003)
79 #define RCC_PREDIV1_Div5                 ((uint32_t)0x00000004)
80 #define RCC_PREDIV1_Div6                 ((uint32_t)0x00000005)
81 #define RCC_PREDIV1_Div7                 ((uint32_t)0x00000006)
82 #define RCC_PREDIV1_Div8                 ((uint32_t)0x00000007)
83 #define RCC_PREDIV1_Div9                 ((uint32_t)0x00000008)
84 #define RCC_PREDIV1_Div10                ((uint32_t)0x00000009)
85 #define RCC_PREDIV1_Div11                ((uint32_t)0x0000000A)
86 #define RCC_PREDIV1_Div12                ((uint32_t)0x0000000B)
87 #define RCC_PREDIV1_Div13                ((uint32_t)0x0000000C)
88 #define RCC_PREDIV1_Div14                ((uint32_t)0x0000000D)
89 #define RCC_PREDIV1_Div15                ((uint32_t)0x0000000E)
90 #define RCC_PREDIV1_Div16                ((uint32_t)0x0000000F)
91 
92 /* PREDIV1_clock_source */
93 #define RCC_PREDIV1_Source_HSE           ((uint32_t)0x00000000)
94 #define RCC_PREDIV1_Source_PLL2          ((uint32_t)0x00010000)
95 
96 /* PREDIV2_division_factor */
97 #define RCC_PREDIV2_Div1                 ((uint32_t)0x00000000)
98 #define RCC_PREDIV2_Div2                 ((uint32_t)0x00000010)
99 #define RCC_PREDIV2_Div3                 ((uint32_t)0x00000020)
100 #define RCC_PREDIV2_Div4                 ((uint32_t)0x00000030)
101 #define RCC_PREDIV2_Div5                 ((uint32_t)0x00000040)
102 #define RCC_PREDIV2_Div6                 ((uint32_t)0x00000050)
103 #define RCC_PREDIV2_Div7                 ((uint32_t)0x00000060)
104 #define RCC_PREDIV2_Div8                 ((uint32_t)0x00000070)
105 #define RCC_PREDIV2_Div9                 ((uint32_t)0x00000080)
106 #define RCC_PREDIV2_Div10                ((uint32_t)0x00000090)
107 #define RCC_PREDIV2_Div11                ((uint32_t)0x000000A0)
108 #define RCC_PREDIV2_Div12                ((uint32_t)0x000000B0)
109 #define RCC_PREDIV2_Div13                ((uint32_t)0x000000C0)
110 #define RCC_PREDIV2_Div14                ((uint32_t)0x000000D0)
111 #define RCC_PREDIV2_Div15                ((uint32_t)0x000000E0)
112 #define RCC_PREDIV2_Div16                ((uint32_t)0x000000F0)
113 
114 /* PLL2_multiplication_factor */
115 #define RCC_PLL2Mul_2_5                  ((uint32_t)0x00000000)
116 #define RCC_PLL2Mul_12_5                 ((uint32_t)0x00000100)
117 #define RCC_PLL2Mul_4                    ((uint32_t)0x00000200)
118 #define RCC_PLL2Mul_5                    ((uint32_t)0x00000300)
119 #define RCC_PLL2Mul_6                    ((uint32_t)0x00000400)
120 #define RCC_PLL2Mul_7                    ((uint32_t)0x00000500)
121 #define RCC_PLL2Mul_8                    ((uint32_t)0x00000600)
122 #define RCC_PLL2Mul_9                    ((uint32_t)0x00000700)
123 #define RCC_PLL2Mul_10                   ((uint32_t)0x00000800)
124 #define RCC_PLL2Mul_11                   ((uint32_t)0x00000900)
125 #define RCC_PLL2Mul_12                   ((uint32_t)0x00000A00)
126 #define RCC_PLL2Mul_13                   ((uint32_t)0x00000B00)
127 #define RCC_PLL2Mul_14                   ((uint32_t)0x00000C00)
128 #define RCC_PLL2Mul_15                   ((uint32_t)0x00000D00)
129 #define RCC_PLL2Mul_16                   ((uint32_t)0x00000E00)
130 #define RCC_PLL2Mul_20                   ((uint32_t)0x00000F00)
131 
132 /* PLL3_multiplication_factor */
133 #define RCC_PLL3Mul_2_5                  ((uint32_t)0x00000000)
134 #define RCC_PLL3Mul_12_5                 ((uint32_t)0x00001000)
135 #define RCC_PLL3Mul_4                    ((uint32_t)0x00002000)
136 #define RCC_PLL3Mul_5                    ((uint32_t)0x00003000)
137 #define RCC_PLL3Mul_6                    ((uint32_t)0x00004000)
138 #define RCC_PLL3Mul_7                    ((uint32_t)0x00005000)
139 #define RCC_PLL3Mul_8                    ((uint32_t)0x00006000)
140 #define RCC_PLL3Mul_9                    ((uint32_t)0x00007000)
141 #define RCC_PLL3Mul_10                   ((uint32_t)0x00008000)
142 #define RCC_PLL3Mul_11                   ((uint32_t)0x00009000)
143 #define RCC_PLL3Mul_12                   ((uint32_t)0x0000A000)
144 #define RCC_PLL3Mul_13                   ((uint32_t)0x0000B000)
145 #define RCC_PLL3Mul_14                   ((uint32_t)0x0000C000)
146 #define RCC_PLL3Mul_15                   ((uint32_t)0x0000D000)
147 #define RCC_PLL3Mul_16                   ((uint32_t)0x0000E000)
148 #define RCC_PLL3Mul_20                   ((uint32_t)0x0000F000)
149 
150 /* System_clock_source */
151 #define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
152 #define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
153 #define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
154 
155 /* AHB_clock_source */
156 #define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
157 #define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
158 #define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
159 #define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
160 #define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
161 #define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
162 #define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
163 #define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
164 #define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
165 
166 /* APB1_APB2_clock_source */
167 #define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
168 #define RCC_HCLK_Div2                    ((uint32_t)0x00000400)
169 #define RCC_HCLK_Div4                    ((uint32_t)0x00000500)
170 #define RCC_HCLK_Div8                    ((uint32_t)0x00000600)
171 #define RCC_HCLK_Div16                   ((uint32_t)0x00000700)
172 
173 /* RCC_Interrupt_source */
174 #define RCC_IT_LSIRDY                    ((uint8_t)0x01)
175 #define RCC_IT_LSERDY                    ((uint8_t)0x02)
176 #define RCC_IT_HSIRDY                    ((uint8_t)0x04)
177 #define RCC_IT_HSERDY                    ((uint8_t)0x08)
178 #define RCC_IT_PLLRDY                    ((uint8_t)0x10)
179 #define RCC_IT_PLL2RDY                   ((uint8_t)0x20)
180 #define RCC_IT_PLL3RDY                   ((uint8_t)0x40)
181 #define RCC_IT_CSS                       ((uint8_t)0x80)
182 
183 /* USB_Device_clock_source */
184 #define RCC_USBCLKSource_PLLCLK_Div1     ((uint8_t)0x00)
185 #define RCC_USBCLKSource_PLLCLK_Div2     ((uint8_t)0x01)
186 #define RCC_USBCLKSource_PLLCLK_Div3     ((uint8_t)0x02)
187 
188 /* USB_OTG_FS_clock_source */
189 #define RCC_OTGFSCLKSource_PLLCLK_Div1   ((uint8_t)0x00)
190 #define RCC_OTGFSCLKSource_PLLCLK_Div2   ((uint8_t)0x01)
191 #define RCC_OTGFSCLKSource_PLLCLK_Div3   ((uint8_t)0x02)
192 
193 /* I2S2_clock_source */
194 #define RCC_I2S2CLKSource_SYSCLK         ((uint8_t)0x00)
195 #define RCC_I2S2CLKSource_PLL3_VCO       ((uint8_t)0x01)
196 
197 /* I2S3_clock_source */
198 #define RCC_I2S3CLKSource_SYSCLK         ((uint8_t)0x00)
199 #define RCC_I2S3CLKSource_PLL3_VCO       ((uint8_t)0x01)
200 
201 /* ADC_clock_source */
202 #define RCC_PCLK2_Div2                   ((uint32_t)0x00000000)
203 #define RCC_PCLK2_Div4                   ((uint32_t)0x00004000)
204 #define RCC_PCLK2_Div6                   ((uint32_t)0x00008000)
205 #define RCC_PCLK2_Div8                   ((uint32_t)0x0000C000)
206 
207 /* LSE_configuration */
208 #define RCC_LSE_OFF                      ((uint8_t)0x00)
209 #define RCC_LSE_ON                       ((uint8_t)0x01)
210 #define RCC_LSE_Bypass                   ((uint8_t)0x04)
211 
212 /* RTC_clock_source */
213 #define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
214 #define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
215 #define RCC_RTCCLKSource_HSE_Div128      ((uint32_t)0x00000300)
216 
217 /* AHB_peripheral */
218 #define RCC_AHBPeriph_DMA1               ((uint32_t)0x00000001)
219 #define RCC_AHBPeriph_DMA2               ((uint32_t)0x00000002)
220 #define RCC_AHBPeriph_SRAM               ((uint32_t)0x00000004)
221 #define RCC_AHBPeriph_FLITF              ((uint32_t)0x00000010)
222 #define RCC_AHBPeriph_CRC                ((uint32_t)0x00000040)
223 #define RCC_AHBPeriph_FSMC               ((uint32_t)0x00000100)
224 #define RCC_AHBPeriph_RNG                ((uint32_t)0x00000200)
225 #define RCC_AHBPeriph_SDIO               ((uint32_t)0x00000400)
226 #define RCC_AHBPeriph_USBHS              ((uint32_t)0x00000800)
227 #define RCC_AHBPeriph_OTG_FS             ((uint32_t)0x00001000)
228 #define RCC_AHBPeriph_DVP                ((uint32_t)0x00002000)
229 #define RCC_AHBPeriph_ETH_MAC            ((uint32_t)0x00004000)
230 #define RCC_AHBPeriph_ETH_MAC_Tx         ((uint32_t)0x00008000)
231 #define RCC_AHBPeriph_ETH_MAC_Rx         ((uint32_t)0x00010000)
232 
233 /* APB2_peripheral */
234 #define RCC_APB2Periph_AFIO              ((uint32_t)0x00000001)
235 #define RCC_APB2Periph_GPIOA             ((uint32_t)0x00000004)
236 #define RCC_APB2Periph_GPIOB             ((uint32_t)0x00000008)
237 #define RCC_APB2Periph_GPIOC             ((uint32_t)0x00000010)
238 #define RCC_APB2Periph_GPIOD             ((uint32_t)0x00000020)
239 #define RCC_APB2Periph_GPIOE             ((uint32_t)0x00000040)
240 #define RCC_APB2Periph_GPIOF             ((uint32_t)0x00000080)
241 #define RCC_APB2Periph_GPIOG             ((uint32_t)0x00000100)
242 #define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)
243 #define RCC_APB2Periph_ADC2              ((uint32_t)0x00000400)
244 #define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)
245 #define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
246 #define RCC_APB2Periph_TIM8              ((uint32_t)0x00002000)
247 #define RCC_APB2Periph_USART1            ((uint32_t)0x00004000)
248 #define RCC_APB2Periph_ADC3              ((uint32_t)0x00008000)
249 #define RCC_APB2Periph_TIM15             ((uint32_t)0x00010000)
250 #define RCC_APB2Periph_TIM16             ((uint32_t)0x00020000)
251 #define RCC_APB2Periph_TIM17             ((uint32_t)0x00040000)
252 #define RCC_APB2Periph_TIM9              ((uint32_t)0x00080000)
253 #define RCC_APB2Periph_TIM10             ((uint32_t)0x00100000)
254 #define RCC_APB2Periph_TIM11             ((uint32_t)0x00200000)
255 
256 /* APB1_peripheral */
257 #define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
258 #define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
259 #define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
260 #define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
261 #define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
262 #define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
263 #define RCC_APB1Periph_UART6             ((uint32_t)0x00000040)
264 #define RCC_APB1Periph_UART7             ((uint32_t)0x00000080)
265 #define RCC_APB1Periph_UART8             ((uint32_t)0x00000100)
266 #define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
267 #define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
268 #define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
269 #define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
270 #define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
271 #define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
272 #define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
273 #define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
274 #define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
275 #define RCC_APB1Periph_USB               ((uint32_t)0x00800000)
276 #define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
277 #define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
278 #define RCC_APB1Periph_BKP               ((uint32_t)0x08000000)
279 #define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
280 #define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
281 #define RCC_APB1Periph_CEC               ((uint32_t)0x40000000)
282 
283 /* Clock_source_to_output_on_MCO_pin */
284 #define RCC_MCO_NoClock                  ((uint8_t)0x00)
285 #define RCC_MCO_SYSCLK                   ((uint8_t)0x04)
286 #define RCC_MCO_HSI                      ((uint8_t)0x05)
287 #define RCC_MCO_HSE                      ((uint8_t)0x06)
288 #define RCC_MCO_PLLCLK_Div2              ((uint8_t)0x07)
289 #define RCC_MCO_PLL2CLK                  ((uint8_t)0x08)
290 #define RCC_MCO_PLL3CLK_Div2             ((uint8_t)0x09)
291 #define RCC_MCO_XT1                      ((uint8_t)0x0A)
292 #define RCC_MCO_PLL3CLK                  ((uint8_t)0x0B)
293 
294 /* RCC_Flag */
295 #define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
296 #define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
297 #define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
298 #define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
299 #define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
300 #define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
301 #define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
302 #define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
303 #define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
304 #define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
305 #define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
306 #define RCC_FLAG_PLL2RDY                 ((uint8_t)0x3B)
307 #define RCC_FLAG_PLL3RDY                 ((uint8_t)0x3D)
308 
309 /* SysTick_clock_source */
310 #define SysTick_CLKSource_HCLK_Div8      ((uint32_t)0xFFFFFFFB)
311 #define SysTick_CLKSource_HCLK           ((uint32_t)0x00000004)
312 
313 /* RNG_clock_source */
314 #define RCC_RNGCLKSource_SYSCLK          ((uint32_t)0x00)
315 #define RCC_RNGCLKSource_PLL3_VCO        ((uint32_t)0x01)
316 
317 /* ETH1G_clock_source */
318 #define RCC_ETH1GCLKSource_PLL2_VCO      ((uint32_t)0x00)
319 #define RCC_ETH1GCLKSource_PLL3_VCO      ((uint32_t)0x01)
320 #define RCC_ETH1GCLKSource_PB1_IN        ((uint32_t)0x02)
321 
322 /* USBFS_clock_source */
323 #define RCC_USBPLL_Div1                  ((uint32_t)0x00)
324 #define RCC_USBPLL_Div2                  ((uint32_t)0x01)
325 #define RCC_USBPLL_Div3                  ((uint32_t)0x02)
326 #define RCC_USBPLL_Div4                  ((uint32_t)0x03)
327 #define RCC_USBPLL_Div5                  ((uint32_t)0x04)
328 #define RCC_USBPLL_Div6                  ((uint32_t)0x05)
329 #define RCC_USBPLL_Div7                  ((uint32_t)0x06)
330 #define RCC_USBPLL_Div8                  ((uint32_t)0x07)
331 
332 /* USBHSPLL_clock_source */
333 #define RCC_HSBHSPLLCLKSource_HSE        ((uint32_t)0x00)
334 #define RCC_HSBHSPLLCLKSource_HSI        ((uint32_t)0x01)
335 
336 /* USBHSPLLCKREF_clock_select */
337 #define RCC_USBHSPLLCKREFCLK_3M          ((uint32_t)0x00)
338 #define RCC_USBHSPLLCKREFCLK_4M          ((uint32_t)0x01)
339 #define RCC_USBHSPLLCKREFCLK_8M          ((uint32_t)0x02)
340 #define RCC_USBHSPLLCKREFCLK_5M          ((uint32_t)0x03)
341 
342 /* USBCLK48M_clock_source */
343 #define RCC_USBCLK48MCLKSource_PLLCLK    ((uint32_t)0x00)
344 #define RCC_USBCLK48MCLKSource_USBPHY    ((uint32_t)0x01)
345 
346 
347 void RCC_DeInit(void);
348 void RCC_HSEConfig(uint32_t RCC_HSE);
349 ErrorStatus RCC_WaitForHSEStartUp(void);
350 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
351 void RCC_HSICmd(FunctionalState NewState);
352 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
353 void RCC_PLLCmd(FunctionalState NewState);
354 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
355 uint8_t RCC_GetSYSCLKSource(void);
356 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
357 void RCC_PCLK1Config(uint32_t RCC_HCLK);
358 void RCC_PCLK2Config(uint32_t RCC_HCLK);
359 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
360 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
361 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
362 void RCC_LSEConfig(uint8_t RCC_LSE);
363 void RCC_LSICmd(FunctionalState NewState);
364 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
365 void RCC_RTCCLKCmd(FunctionalState NewState);
366 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
367 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
368 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
369 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
370 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
371 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
372 void RCC_BackupResetCmd(FunctionalState NewState);
373 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
374 void RCC_MCOConfig(uint8_t RCC_MCO);
375 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
376 void RCC_ClearFlag(void);
377 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
378 void RCC_ClearITPendingBit(uint8_t RCC_IT);
379 
380 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
381 void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
382 void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
383 void RCC_PLL2Cmd(FunctionalState NewState);
384 void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
385 void RCC_PLL3Cmd(FunctionalState NewState);
386 void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
387 void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
388 void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
389 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
390 
391 void RCC_ADCCLKADJcmd(FunctionalState NewState);
392 void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource);
393 void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource);
394 void RCC_ETH1G_125Mcmd(FunctionalState NewState);
395 void RCC_USBHSConfig(uint32_t RCC_USBHS);
396 void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource);
397 void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource);
398 void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState);
399 void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource);
400 
401 #ifdef __cplusplus
402 }
403 #endif
404 
405 #endif
406 
407 
408 
409 
410 
411