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Searched defs:RCC_PLLHSIPRE_PLLSRCDIV_DISABLE (Results 1 – 3 of 3) sorted by relevance

/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/
A Dn32g43x.h1741 #define RCC_PLLHSIPRE_PLLSRCDIV_DISABLE ((uint32_t)0x00000000) /*!< PLL source clock not divided fo… macro
/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/
A Dn32l40x.h1764 #define RCC_PLLHSIPRE_PLLSRCDIV_DISABLE ((uint32_t)0x00000000) /*!< PLL source clock not divided fo… macro
/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/
A Dn32l43x.h1790 #define RCC_PLLHSIPRE_PLLSRCDIV_DISABLE ((uint32_t)0x00000000) /*!< PLL source clock not divided fo… macro

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