1 /********************************** (C) COPYRIGHT *******************************
2 * File Name : ch32f20x_rcc.c
3 * Author : WCH
4 * Version : V1.0.0
5 * Date : 2021/08/08
6 * Description : This file provides all the RCC firmware functions.
7 *******************************************************************************/
8 #include "ch32f20x_rcc.h"
9
10 /* RCC registers bit address in the alias region */
11 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
12
13 /* CFGR0 Register */
14
15 /* Alias word address of USBPRE bit */
16 #define CFGR0_OFFSET (RCC_OFFSET + 0x04)
17 #define USBPRE_BitNumber 0x16
18 #define CFGR0_USBPRE_BB (PERIPH_BB_BASE + (CFGR0_OFFSET * 32) + (USBPRE_BitNumber * 4))
19
20
21 /* BDCTLR Register */
22 #define BDCTLR_OFFSET (RCC_OFFSET + 0x20)
23
24 /* RCC registers bit mask */
25
26 /* CTLR register bit mask */
27 #define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
28 #define CTLR_HSEBYP_Set ((uint32_t)0x00040000)
29 #define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
30 #define CTLR_HSEON_Set ((uint32_t)0x00010000)
31 #define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
32
33 #define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF)
34 #define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000)
35 #define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000)
36 #define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000)
37 #define CFGR0_SWS_Mask ((uint32_t)0x0000000C)
38 #define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC)
39 #define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
40 #define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0)
41 #define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
42 #define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700)
43 #define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
44 #define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800)
45 #define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
46 #define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
47
48 /* RSTSCKR register bit mask */
49 #define RSTSCKR_RMVF_Set ((uint32_t)0x01000000)
50
51 /* CFGR2 register bit mask */
52 #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000)
53 #define CFGR2_PREDIV1 ((uint32_t)0x0000000F)
54 #define CFGR2_PREDIV2 ((uint32_t)0x000000F0)
55 #define CFGR2_PLL2MUL ((uint32_t)0x00000F00)
56 #define CFGR2_PLL3MUL ((uint32_t)0x0000F000)
57
58 /* RCC Flag Mask */
59 #define FLAG_Mask ((uint8_t)0x1F)
60
61 /* INTR register byte 2 (Bits[15:8]) base address */
62 #define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009)
63
64 /* INTR register byte 3 (Bits[23:16]) base address */
65 #define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
66
67 /* CFGR0 register byte 4 (Bits[31:24]) base address */
68 #define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007)
69
70 /* BDCTLR register base address */
71 #define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET)
72
73
74 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
75 static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
76
77 /*******************************************************************************
78 * Function Name : RCC_DeInit
79 * Description : Resets the RCC clock configuration to the default reset state.
80 * Input : None
81 * Return : None
82 *******************************************************************************/
RCC_DeInit(void)83 void RCC_DeInit(void)
84 {
85 RCC->CTLR |= (uint32_t)0x00000001;
86 RCC->CFGR0 &= (uint32_t)0xF8FF0000;
87 RCC->CTLR &= (uint32_t)0xFEF6FFFF;
88 RCC->CTLR &= (uint32_t)0xFFFBFFFF;
89 RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
90 RCC->INTR = 0x009F0000;
91 }
92
93 /*******************************************************************************
94 * Function Name : RCC_HSEConfig
95 * Description : Configures the External High Speed oscillator (HSE).
96 * Input : RCC_HSE:
97 * RCC_HSE_OFF: HSE oscillator OFF.
98 * RCC_HSE_ON: HSE oscillator ON.
99 * RCC_HSE_Bypass: HSE oscillator bypassed with external clock.
100 * Return : None
101 *******************************************************************************/
RCC_HSEConfig(uint32_t RCC_HSE)102 void RCC_HSEConfig(uint32_t RCC_HSE)
103 {
104 RCC->CTLR &= CTLR_HSEON_Reset;
105 RCC->CTLR &= CTLR_HSEBYP_Reset;
106
107 switch(RCC_HSE)
108 {
109 case RCC_HSE_ON:
110 RCC->CTLR |= CTLR_HSEON_Set;
111 break;
112
113 case RCC_HSE_Bypass:
114 RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set;
115 break;
116
117 default:
118 break;
119 }
120 }
121
122 /*******************************************************************************
123 * Function Name : RCC_WaitForHSEStartUp
124 * Description : Waits for HSE start-up.
125 * Input : None
126 * Return : SUCCESS: HSE oscillator is stable and ready to use.
127 * ERROR: HSE oscillator not yet ready.
128 *******************************************************************************/
RCC_WaitForHSEStartUp(void)129 ErrorStatus RCC_WaitForHSEStartUp(void)
130 {
131 __IO uint32_t StartUpCounter = 0;
132
133 ErrorStatus status = ERROR;
134 FlagStatus HSEStatus = RESET;
135
136 do
137 {
138 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
139 StartUpCounter++;
140 } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
141
142 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
143 {
144 status = SUCCESS;
145 }
146 else
147 {
148 status = ERROR;
149 }
150
151 return (status);
152 }
153
154 /*******************************************************************************
155 * Function Name : RCC_AdjustHSICalibrationValue
156 * Description : Adjusts the Internal High Speed oscillator (HSI) calibration value.
157 * Input : HSICalibrationValue: specifies the calibration trimming value.
158 * This parameter must be a number between 0 and 0x1F.
159 * Return : None
160 *******************************************************************************/
RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)161 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
162 {
163 uint32_t tmpreg = 0;
164
165 tmpreg = RCC->CTLR;
166 tmpreg &= CTLR_HSITRIM_Mask;
167 tmpreg |= (uint32_t)HSICalibrationValue << 3;
168 RCC->CTLR = tmpreg;
169 }
170
171 /*******************************************************************************
172 * Function Name : RCC_HSICmd
173 * Description : Enables or disables the Internal High Speed oscillator (HSI).
174 * Input : NewState: ENABLE or DISABLE.
175 * Return : None
176 *******************************************************************************/
RCC_HSICmd(FunctionalState NewState)177 void RCC_HSICmd(FunctionalState NewState)
178 {
179 if(NewState)
180 {
181 RCC->CTLR |= ((uint32_t)1<<0);
182 }
183 else{
184 RCC->CTLR &= ~((uint32_t)1<<0);
185 }
186 }
187
188 /*******************************************************************************
189 * Function Name : RCC_PLLConfig
190 * Description : Configures the PLL clock source and multiplication factor.
191 * Input : RCC_PLLSource: specifies the PLL entry clock source.
192 * RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2
193 * selected as PLL clock entry.
194 * RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL
195 * clock entry.
196 * RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2
197 * selected as PLL clock entry.
198 * RCC_PLLMul: specifies the PLL multiplication factor.
199 * This parameter can be RCC_PLLMul_x where x:[2,16].
200 * For CH32F207:
201 * RCC_PLLMul_18_EXTEN
202 * RCC_PLLMul_3_EXTEN
203 * RCC_PLLMul_4_EXTEN
204 * RCC_PLLMul_5_EXTEN
205 * RCC_PLLMul_6_EXTEN
206 * RCC_PLLMul_7_EXTEN
207 * RCC_PLLMul_8_EXTEN
208 * RCC_PLLMul_9_EXTEN
209 * RCC_PLLMul_10_EXTEN
210 * RCC_PLLMul_11_EXTEN
211 * RCC_PLLMul_12_EXTEN
212 * RCC_PLLMul_13_EXTEN
213 * RCC_PLLMul_14_EXTEN
214 * RCC_PLLMul_6_5_EXTEN
215 * RCC_PLLMul_15_EXTEN
216 * RCC_PLLMul_16_EXTEN
217 * For other CH32F20x:
218 * RCC_PLLMul_2
219 * RCC_PLLMul_3
220 * RCC_PLLMul_4
221 * RCC_PLLMul_5
222 * RCC_PLLMul_6
223 * RCC_PLLMul_7
224 * RCC_PLLMul_8
225 * RCC_PLLMul_9
226 * RCC_PLLMul_10
227 * RCC_PLLMul_11
228 * RCC_PLLMul_12
229 * RCC_PLLMul_13
230 * RCC_PLLMul_14
231 * RCC_PLLMul_15
232 * RCC_PLLMul_16
233 * RCC_PLLMul_18
234 * Return : None
235 *******************************************************************************/
RCC_PLLConfig(uint32_t RCC_PLLSource,uint32_t RCC_PLLMul)236 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
237 {
238 uint32_t tmpreg = 0;
239
240 tmpreg = RCC->CFGR0;
241 tmpreg &= CFGR0_PLL_Mask;
242 tmpreg |= RCC_PLLSource | RCC_PLLMul;
243 RCC->CFGR0 = tmpreg;
244 }
245
246 /*******************************************************************************
247 * Function Name : RCC_PLLCmd
248 * Description : Enables or disables the PLL.
249 * Input : NewState: ENABLE or DISABLE.
250 * Return : None
251 *******************************************************************************/
RCC_PLLCmd(FunctionalState NewState)252 void RCC_PLLCmd(FunctionalState NewState)
253 {
254 if(NewState)
255 {
256 RCC->CTLR |= ((uint32_t)1<<24);
257 }
258 else{
259 RCC->CTLR &= ~((uint32_t)1<<24);
260 }
261 }
262
263 /*******************************************************************************
264 * Function Name : RCC_SYSCLKConfig
265 * Description : Configures the system clock (SYSCLK).
266 * Input : RCC_SYSCLKSource: specifies the clock source used as system clock.
267 * RCC_SYSCLKSource_HSI: HSI selected as system clock.
268 * RCC_SYSCLKSource_HSE: HSE selected as system clock.
269 * RCC_SYSCLKSource_PLLCLK: PLL selected as system clock.
270 * Return : None
271 *******************************************************************************/
RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)272 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
273 {
274 uint32_t tmpreg = 0;
275
276 tmpreg = RCC->CFGR0;
277 tmpreg &= CFGR0_SW_Mask;
278 tmpreg |= RCC_SYSCLKSource;
279 RCC->CFGR0 = tmpreg;
280 }
281
282 /*******************************************************************************
283 * Function Name : RCC_GetSYSCLKSource
284 * Description : Returns the clock source used as system clock.
285 * Input : None
286 * Return : 0x00: HSI used as system clock.
287 * 0x04: HSE used as system clock.
288 * 0x08: PLL used as system clock.
289 *******************************************************************************/
RCC_GetSYSCLKSource(void)290 uint8_t RCC_GetSYSCLKSource(void)
291 {
292 return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask));
293 }
294
295 /*******************************************************************************
296 * Function Name : RCC_HCLKConfig
297 * Description : Configures the AHB clock (HCLK).
298 * Input : RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
299 * the system clock (SYSCLK).
300 * RCC_SYSCLK_Div1: AHB clock = SYSCLK.
301 * RCC_SYSCLK_Div2: AHB clock = SYSCLK/2.
302 * RCC_SYSCLK_Div4: AHB clock = SYSCLK/4.
303 * RCC_SYSCLK_Div8: AHB clock = SYSCLK/8.
304 * RCC_SYSCLK_Div16: AHB clock = SYSCLK/16.
305 * RCC_SYSCLK_Div64: AHB clock = SYSCLK/64.
306 * RCC_SYSCLK_Div128: AHB clock = SYSCLK/128.
307 * RCC_SYSCLK_Div256: AHB clock = SYSCLK/256.
308 * RCC_SYSCLK_Div512: AHB clock = SYSCLK/512.
309 * Return : None
310 *******************************************************************************/
RCC_HCLKConfig(uint32_t RCC_SYSCLK)311 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
312 {
313 uint32_t tmpreg = 0;
314
315 tmpreg = RCC->CFGR0;
316 tmpreg &= CFGR0_HPRE_Reset_Mask;
317 tmpreg |= RCC_SYSCLK;
318 RCC->CFGR0 = tmpreg;
319 }
320
321 /*******************************************************************************
322 * Function Name : RCC_PCLK1Config
323 * Description : Configures the Low Speed APB clock (PCLK1).
324 * Input : RCC_HCLK: defines the APB1 clock divider. This clock is derived from
325 * the AHB clock (HCLK).
326 * RCC_HCLK_Div1: APB1 clock = HCLK.
327 * RCC_HCLK_Div2: APB1 clock = HCLK/2.
328 * RCC_HCLK_Div4: APB1 clock = HCLK/4.
329 * RCC_HCLK_Div8: APB1 clock = HCLK/8.
330 * RCC_HCLK_Div16: APB1 clock = HCLK/16.
331 * Return : None
332 *******************************************************************************/
RCC_PCLK1Config(uint32_t RCC_HCLK)333 void RCC_PCLK1Config(uint32_t RCC_HCLK)
334 {
335 uint32_t tmpreg = 0;
336
337 tmpreg = RCC->CFGR0;
338 tmpreg &= CFGR0_PPRE1_Reset_Mask;
339 tmpreg |= RCC_HCLK;
340 RCC->CFGR0 = tmpreg;
341 }
342
343 /*******************************************************************************
344 * Function Name : RCC_PCLK2Config
345 * Description : Configures the High Speed APB clock (PCLK2).
346 * Input : RCC_HCLK: defines the APB2 clock divider. This clock is derived from
347 * the AHB clock (HCLK).
348 * RCC_HCLK_Div1: APB2 clock = HCLK.
349 * RCC_HCLK_Div2: APB2 clock = HCLK/2.
350 * RCC_HCLK_Div4: APB2 clock = HCLK/4.
351 * RCC_HCLK_Div8: APB2 clock = HCLK/8.
352 * RCC_HCLK_Div16: APB2 clock = HCLK/16.
353 * Return : None
354 *******************************************************************************/
RCC_PCLK2Config(uint32_t RCC_HCLK)355 void RCC_PCLK2Config(uint32_t RCC_HCLK)
356 {
357 uint32_t tmpreg = 0;
358
359 tmpreg = RCC->CFGR0;
360 tmpreg &= CFGR0_PPRE2_Reset_Mask;
361 tmpreg |= RCC_HCLK << 3;
362 RCC->CFGR0 = tmpreg;
363 }
364
365 /*******************************************************************************
366 * Function Name : RCC_ITConfig
367 * Description : Enables or disables the specified RCC interrupts.
368 * Input : RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
369 * RCC_IT_LSIRDY: LSI ready interrupt.
370 * RCC_IT_LSERDY: LSE ready interrupt.
371 * RCC_IT_HSIRDY: HSI ready interrupt.
372 * RCC_IT_HSERDY: HSE ready interrupt.
373 * RCC_IT_PLLRDY: PLL ready interrupt.
374 * NewState: ENABLE or DISABLE.
375 * Return : None
376 *******************************************************************************/
RCC_ITConfig(uint8_t RCC_IT,FunctionalState NewState)377 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
378 {
379 if (NewState != DISABLE)
380 {
381 *(__IO uint8_t *) INTR_BYTE2_ADDRESS |= RCC_IT;
382 }
383 else
384 {
385 *(__IO uint8_t *) INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
386 }
387 }
388
389 /*******************************************************************************
390 * Function Name : RCC_USBCLKConfig
391 * Description : Configures the USB clock (USBCLK).
392 * Input : RCC_USBCLKSource: specifies the USB clock source. This clock is
393 * derived from the PLL output.
394 * RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source(48Mhz).
395 * RCC_USBCLKSource_PLLCLK_Div2: PLL clock selected as USB clock source(96MHz).
396 * RCC_USBCLKSource_PLLCLK_Div3: PLL clock selected as USB clock source(144MHz).
397 * Return : None
398 *******************************************************************************/
RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)399 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
400 {
401 RCC->CFGR0 &= ~((uint32_t)3<<22);
402 RCC->CFGR0 |= RCC_USBCLKSource<<22;
403 }
404
405 /*******************************************************************************
406 * Function Name : RCC_ADCCLKConfig
407 * Description : Configures the ADC clock (ADCCLK).
408 * Input : RCC_PCLK2: defines the ADC clock divider. This clock is derived from
409 * the APB2 clock (PCLK2).
410 * RCC_PCLK2_Div2: ADC clock = PCLK2/2.
411 * RCC_PCLK2_Div4: ADC clock = PCLK2/4.
412 * RCC_PCLK2_Div6: ADC clock = PCLK2/6.
413 * RCC_PCLK2_Div8: ADC clock = PCLK2/8.
414 * Return : None
415 ********************************************************************************/
RCC_ADCCLKConfig(uint32_t RCC_PCLK2)416 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
417 {
418 uint32_t tmpreg = 0;
419
420 tmpreg = RCC->CFGR0;
421 tmpreg &= CFGR0_ADCPRE_Reset_Mask;
422 tmpreg |= RCC_PCLK2;
423 RCC->CFGR0 = tmpreg;
424 }
425
426 /*******************************************************************************
427 * Function Name : RCC_LSEConfig
428 * Description : Configures the External Low Speed oscillator (LSE).
429 * Input : RCC_LSE: specifies the new state of the LSE.
430 * RCC_LSE_OFF: LSE oscillator OFF.
431 * RCC_LSE_ON: LSE oscillator ON.
432 * RCC_LSE_Bypass: LSE oscillator bypassed with external clock.
433 * Return : None
434 ********************************************************************************/
RCC_LSEConfig(uint8_t RCC_LSE)435 void RCC_LSEConfig(uint8_t RCC_LSE)
436 {
437 *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF;
438 *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF;
439
440 switch(RCC_LSE)
441 {
442 case RCC_LSE_ON:
443 *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_ON;
444 break;
445
446 case RCC_LSE_Bypass:
447 *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
448 break;
449
450 default:
451 break;
452 }
453 }
454
455 /*******************************************************************************
456 * Function Name : RCC_LSICmd
457 * Description : Enables or disables the Internal Low Speed oscillator (LSI).
458 * Input : NewState: ENABLE or DISABLE.
459 * Return : None
460 ********************************************************************************/
RCC_LSICmd(FunctionalState NewState)461 void RCC_LSICmd(FunctionalState NewState)
462 {
463 if(NewState)
464 {
465 RCC->RSTSCKR |= ((uint32_t)1<<0);
466 }
467 else{
468 RCC->RSTSCKR &= ~((uint32_t)1<<0);
469 }
470 }
471
472 /*******************************************************************************
473 * Function Name : RCC_RTCCLKConfig
474 * Description : Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
475 * Input : RCC_RTCCLKSource: specifies the RTC clock source.
476 * RCC_RTCCLKSource_LSE: LSE selected as RTC clock.
477 * RCC_RTCCLKSource_LSI: LSI selected as RTC clock.
478 * RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock.
479 * Return : None
480 ********************************************************************************/
RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)481 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
482 {
483 RCC->BDCTLR |= RCC_RTCCLKSource;
484 }
485
486 /*******************************************************************************
487 * Function Name : RCC_RTCCLKCmd
488 * Description : This function must be used only after the RTC clock was selected
489 * using the RCC_RTCCLKConfig function.
490 * Input : NewState: ENABLE or DISABLE.
491 * Return : None
492 ********************************************************************************/
RCC_RTCCLKCmd(FunctionalState NewState)493 void RCC_RTCCLKCmd(FunctionalState NewState)
494 {
495 if(NewState)
496 {
497 RCC->BDCTLR |= ((uint32_t)1<<15);
498 }
499 else{
500 RCC->BDCTLR &= ~((uint32_t)1<<15);
501 }
502 }
503
504 /*******************************************************************************
505 * Function Name : RCC_GetClocksFreq
506 * Description : The result of this function could be not correct when using
507 * fractional value for HSE crystal.
508 * Input : RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
509 * the clocks frequencies.
510 * Return : None
511 ********************************************************************************/
RCC_GetClocksFreq(RCC_ClocksTypeDef * RCC_Clocks)512 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
513 {
514 uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0, Pll_6_5 = 0;
515
516 tmp = RCC->CFGR0 & CFGR0_SWS_Mask;
517
518 switch (tmp)
519 {
520 case 0x00:
521 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
522 break;
523
524 case 0x04:
525 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
526 break;
527
528 case 0x08:
529 pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask;
530 pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask;
531
532 pllmull = ( pllmull >> 18) + 2;
533
534 if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){ /* for other CH32F20x */
535 if(pllmull == 17) pllmull = 18;
536 }
537 else{ /* for CH32F207 */
538 if(pllmull == 2) pllmull = 18;
539 if(pllmull == 15){
540 pllmull = 13; /* *6.5 */
541 Pll_6_5 = 1;
542 }
543 if(pllmull == 16) pllmull = 15;
544 if(pllmull == 17) pllmull = 16;
545 }
546
547
548 if (pllsource == 0x00)
549 {
550 if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
551 RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE) * pllmull;
552 }
553 else{
554 RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >>1) * pllmull;
555 }
556 }
557 else
558 {
559 if ((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET)
560 {
561 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
562 }
563 else
564 {
565 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
566 }
567 }
568
569 if(Pll_6_5 == 1) RCC_Clocks->SYSCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency / 2);
570
571 break;
572
573 default:
574 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
575 break;
576 }
577
578 tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask;
579 tmp = tmp >> 4;
580 presc = APBAHBPrescTable[tmp];
581 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
582 tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask;
583 tmp = tmp >> 8;
584 presc = APBAHBPrescTable[tmp];
585 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
586 tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask;
587 tmp = tmp >> 11;
588 presc = APBAHBPrescTable[tmp];
589 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
590 tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask;
591 tmp = tmp >> 14;
592 presc = ADCPrescTable[tmp];
593 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
594 }
595
596 /*******************************************************************************
597 * Function Name : RCC_AHBPeriphClockCmd
598 * Description : Enables or disables the AHB peripheral clock.
599 * Input : RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
600 * RCC_AHBPeriph_DMA1.
601 * RCC_AHBPeriph_DMA2.
602 * RCC_AHBPeriph_SRAM.
603 * RCC_AHBPeriph_FLITF.
604 * RCC_AHBPeriph_CRC.
605 * RCC_AHBPeriph_FSMC
606 * RCC_AHBPeriph_RNG
607 * RCC_AHBPeriph_SDIO
608 * RCC_AHBPeriph_USBHS
609 * RCC_AHBPeriph_USBOTG
610 * RCC_AHBPeriph_DVP
611 * RCC_AHBPeriph_ETH_MAC
612 * RCC_AHBPeriph_ETH_MAC_Tx
613 * RCC_AHBPeriph_ETH_MAC_Rx
614 * NewState: ENABLE or DISABLE.
615 * Return : None
616 *******************************************************************************/
RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph,FunctionalState NewState)617 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
618 {
619 if (NewState != DISABLE)
620 {
621 RCC->AHBPCENR |= RCC_AHBPeriph;
622 }
623 else
624 {
625 RCC->AHBPCENR &= ~RCC_AHBPeriph;
626 }
627 }
628
629 /*******************************************************************************
630 * Function Name : RCC_APB2PeriphClockCmd
631 * Description : Enables or disables the High Speed APB (APB2) peripheral clock.
632 * Input : RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
633 * RCC_APB2Periph_AFIO.
634 * RCC_APB2Periph_GPIOA.
635 * RCC_APB2Periph_GPIOB.
636 * RCC_APB2Periph_GPIOC.
637 * RCC_APB2Periph_GPIOD.
638 * RCC_APB2Periph_GPIOE
639 * RCC_APB2Periph_ADC1.
640 * RCC_APB2Periph_ADC2
641 * RCC_APB2Periph_TIM1.
642 * RCC_APB2Periph_SPI1.
643 * RCC_APB2Periph_TIM8
644 * RCC_APB2Periph_TIM9
645 * RCC_APB2Periph_TIM10
646 * RCC_APB2Periph_USART1.
647 * NewState: ENABLE or DISABLE
648 * Return : None
649 *******************************************************************************/
RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph,FunctionalState NewState)650 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
651 {
652 if (NewState != DISABLE)
653 {
654 RCC->APB2PCENR |= RCC_APB2Periph;
655 }
656 else
657 {
658 RCC->APB2PCENR &= ~RCC_APB2Periph;
659 }
660 }
661
662 /*******************************************************************************
663 * Function Name : RCC_APB1PeriphClockCmd
664 * Description : Enables or disables the Low Speed APB (APB1) peripheral clock.
665 * Input : RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
666 * RCC_APB1Periph_TIM2.
667 * RCC_APB1Periph_TIM3.
668 * RCC_APB1Periph_TIM4.
669 * RCC_APB1Periph_TIM5
670 * RCC_APB1Periph_TIM6
671 * RCC_APB1Periph_TIM7
672 * RCC_APB1Periph_UART6
673 * RCC_APB1Periph_UART7
674 * RCC_APB1Periph_UART8
675 * RCC_APB1Periph_WWDG.
676 * RCC_APB1Periph_SPI2.
677 * RCC_APB1Periph_USART2.
678 * RCC_APB1Periph_USART3.
679 * RCC_APB1Periph_UART4
680 * RCC_APB1Periph_UART5
681 * RCC_APB1Periph_I2C1.
682 * RCC_APB1Periph_I2C2.
683 * RCC_APB1Periph_USB.
684 * RCC_APB1Periph_CAN1.
685 * RCC_APB1Periph_BKP.
686 * RCC_APB1Periph_PWR.
687 * RCC_APB1Periph_DAC.
688 * NewState: ENABLE or DISABLE.
689 * Return : None
690 *******************************************************************************/
RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph,FunctionalState NewState)691 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
692 {
693 if (NewState != DISABLE)
694 {
695 RCC->APB1PCENR |= RCC_APB1Periph;
696 }
697 else
698 {
699 RCC->APB1PCENR &= ~RCC_APB1Periph;
700 }
701 }
702
703 /*******************************************************************************
704 * Function Name : RCC_APB2PeriphResetCmd
705 * Description : Forces or releases High Speed APB (APB2) peripheral reset.
706 * Input : RCC_APB2Periph: specifies the APB2 peripheral to reset.
707 * RCC_APB2Periph_AFIO.
708 * RCC_APB2Periph_GPIOA.
709 * RCC_APB2Periph_GPIOB.
710 * RCC_APB2Periph_GPIOC.
711 * RCC_APB2Periph_GPIOD.
712 * RCC_APB2Periph_GPIOE
713 * RCC_APB2Periph_ADC1.
714 * RCC_APB2Periph_ADC2
715 * RCC_APB2Periph_TIM1.
716 * RCC_APB2Periph_SPI1.
717 * RCC_APB2Periph_TIM8
718 * RCC_APB2Periph_TIM9
719 * RCC_APB2Periph_TIM10
720 * RCC_APB2Periph_USART1.
721 * NewState: ENABLE or DISABLE.
722 * Return : None
723 *******************************************************************************/
RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph,FunctionalState NewState)724 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
725 {
726 if (NewState != DISABLE)
727 {
728 RCC->APB2PRSTR |= RCC_APB2Periph;
729 }
730 else
731 {
732 RCC->APB2PRSTR &= ~RCC_APB2Periph;
733 }
734 }
735
736 /*******************************************************************************
737 * Function Name : RCC_APB1PeriphResetCmd
738 * Description : Forces or releases Low Speed APB (APB1) peripheral reset.
739 * Input : RCC_APB1Periph: specifies the APB1 peripheral to reset.
740 * RCC_APB1Periph_TIM2.
741 * RCC_APB1Periph_TIM3.
742 * RCC_APB1Periph_TIM4.
743 * RCC_APB1Periph_TIM5
744 * RCC_APB1Periph_TIM6
745 * RCC_APB1Periph_TIM7
746 * RCC_APB1Periph_UART6
747 * RCC_APB1Periph_UART7
748 * RCC_APB1Periph_UART8
749 * RCC_APB1Periph_WWDG.
750 * RCC_APB1Periph_SPI2.
751 * RCC_APB1Periph_USART2.
752 * RCC_APB1Periph_USART3.
753 * RCC_APB1Periph_UART4
754 * RCC_APB1Periph_UART5
755 * RCC_APB1Periph_I2C1.
756 * RCC_APB1Periph_I2C2.
757 * RCC_APB1Periph_USB.
758 * RCC_APB1Periph_CAN1.
759 * RCC_APB1Periph_BKP.
760 * RCC_APB1Periph_PWR.
761 * RCC_APB1Periph_DAC.
762 * NewState: ENABLE or DISABLE.
763 * Return : None
764 *******************************************************************************/
RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph,FunctionalState NewState)765 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
766 {
767 if (NewState != DISABLE)
768 {
769 RCC->APB1PRSTR |= RCC_APB1Periph;
770 }
771 else
772 {
773 RCC->APB1PRSTR &= ~RCC_APB1Periph;
774 }
775 }
776
777 /*******************************************************************************
778 * Function Name : RCC_BackupResetCmd
779 * Description : Forces or releases the Backup domain reset.
780 * Input : NewState: ENABLE or DISABLE.
781 * Return : None
782 *******************************************************************************/
RCC_BackupResetCmd(FunctionalState NewState)783 void RCC_BackupResetCmd(FunctionalState NewState)
784 {
785 if(NewState)
786 {
787 RCC->BDCTLR |= ((uint32_t)1<<16);
788 }
789 else{
790 RCC->BDCTLR &= ~((uint32_t)1<<16);
791 }
792 }
793
794 /*******************************************************************************
795 * Function Name : RCC_ClockSecuritySystemCmd
796 * Description : Enables or disables the Clock Security System.
797 * Input : NewState: ENABLE or DISABLE.
798 * Return : None
799 *******************************************************************************/
RCC_ClockSecuritySystemCmd(FunctionalState NewState)800 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
801 {
802 if(NewState)
803 {
804 RCC->CTLR |= ((uint32_t)1<<19);
805 }
806 else{
807 RCC->CTLR &= ~((uint32_t)1<<19);
808 }
809 }
810
811 /*******************************************************************************
812 * Function Name : RCC_MCOConfig
813 * Description : Selects the clock source to output on MCO pin.
814 * Input : RCC_MCO: specifies the clock source to output.
815 * RCC_MCO_NoClock: No clock selected.
816 * RCC_MCO_SYSCLK: System clock selected.
817 * RCC_MCO_HSI: HSI oscillator clock selected.
818 * RCC_MCO_HSE: HSE oscillator clock selected.
819 * RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected.
820 * RCC_MCO_PLL2CLK: PLL2 clock selected
821 * RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected
822 * RCC_MCO_XT1: External 3-25 MHz oscillator clock selected
823 * RCC_MCO_PLL3CLK: PLL3 clock selected
824 * Return : None
825 *******************************************************************************/
RCC_MCOConfig(uint8_t RCC_MCO)826 void RCC_MCOConfig(uint8_t RCC_MCO)
827 {
828 *(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO;
829 }
830
831 /*******************************************************************************
832 * Function Name : RCC_GetFlagStatus
833 * Description : Checks whether the specified RCC flag is set or not.
834 * Input : RCC_FLAG: specifies the flag to check.
835 * RCC_FLAG_HSIRDY: HSI oscillator clock ready.
836 * RCC_FLAG_HSERDY: HSE oscillator clock ready.
837 * RCC_FLAG_PLLRDY: PLL clock ready.
838 * RCC_FLAG_PLL2RDY: PLL2 clock ready.
839 * RCC_FLAG_PLL3RDY: PLL3 clock ready.
840 * RCC_FLAG_LSERDY: LSE oscillator clock ready.
841 * RCC_FLAG_LSIRDY: LSI oscillator clock ready.
842 * RCC_FLAG_PINRST: Pin reset.
843 * RCC_FLAG_PORRST: POR/PDR reset.
844 * RCC_FLAG_SFTRST: Software reset.
845 * RCC_FLAG_IWDGRST: Independent Watchdog reset.
846 * RCC_FLAG_WWDGRST: Window Watchdog reset.
847 * RCC_FLAG_LPWRRST: Low Power reset.
848 * Return : FlagStatus: SET or RESET.
849 *******************************************************************************/
RCC_GetFlagStatus(uint8_t RCC_FLAG)850 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
851 {
852 uint32_t tmp = 0;
853 uint32_t statusreg = 0;
854
855 FlagStatus bitstatus = RESET;
856 tmp = RCC_FLAG >> 5;
857
858 if (tmp == 1)
859 {
860 statusreg = RCC->CTLR;
861 }
862 else if (tmp == 2)
863 {
864 statusreg = RCC->BDCTLR;
865 }
866 else
867 {
868 statusreg = RCC->RSTSCKR;
869 }
870
871 tmp = RCC_FLAG & FLAG_Mask;
872
873 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
874 {
875 bitstatus = SET;
876 }
877 else
878 {
879 bitstatus = RESET;
880 }
881
882 return bitstatus;
883 }
884
885 /*******************************************************************************
886 * Function Name : RCC_ClearFlag
887 * Description : Clears the RCC reset flags.
888 * Input : None
889 * Return : None
890 *******************************************************************************/
RCC_ClearFlag(void)891 void RCC_ClearFlag(void)
892 {
893 RCC->RSTSCKR |= RSTSCKR_RMVF_Set;
894 }
895
896 /*******************************************************************************
897 * Function Name : RCC_GetITStatus
898 * Description : Checks whether the specified RCC interrupt has occurred or not.
899 * Input : RCC_IT: specifies the RCC interrupt source to check.
900 * RCC_IT_LSIRDY: LSI ready interrupt.
901 * RCC_IT_LSERDY: LSE ready interrupt.
902 * RCC_IT_HSIRDY: HSI ready interrupt.
903 * RCC_IT_HSERDY: HSE ready interrupt.
904 * RCC_IT_PLLRDY: PLL ready interrupt.
905 * RCC_IT_PLL2RDY: PLL2 ready interrupt.
906 * RCC_IT_PLL3RDY: PLL3 ready interrupt.
907 * RCC_IT_CSS: Clock Security System interrupt.
908 * Return : ITStatus: SET or RESET.
909 *******************************************************************************/
RCC_GetITStatus(uint8_t RCC_IT)910 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
911 {
912 ITStatus bitstatus = RESET;
913
914 if ((RCC->INTR & RCC_IT) != (uint32_t)RESET)
915 {
916 bitstatus = SET;
917 }
918 else
919 {
920 bitstatus = RESET;
921 }
922
923 return bitstatus;
924 }
925
926 /*******************************************************************************
927 * Function Name : RCC_ClearITPendingBit
928 * Description : Clears the RCC's interrupt pending bits.
929 * Input : RCC_IT: specifies the interrupt pending bit to clear.
930 * RCC_IT_LSIRDY: LSI ready interrupt.
931 * RCC_IT_LSERDY: LSE ready interrupt.
932 * RCC_IT_HSIRDY: HSI ready interrupt.
933 * RCC_IT_HSERDY: HSE ready interrupt.
934 * RCC_IT_PLLRDY: PLL ready interrupt.
935 * RCC_IT_PLL2RDY: PLL2 ready interrupt.
936 * RCC_IT_PLL3RDY: PLL3 ready interrupt.
937 * RCC_IT_CSS: Clock Security System interrupt.
938 * Return : None
939 *******************************************************************************/
RCC_ClearITPendingBit(uint8_t RCC_IT)940 void RCC_ClearITPendingBit(uint8_t RCC_IT)
941 {
942 *(__IO uint8_t *) INTR_BYTE3_ADDRESS = RCC_IT;
943 }
944
945 /*******************************************************************************
946 * Function Name : RCC_PREDIV1Config
947 * Description : Configures the PREDIV1 division factor.
948 * Input : RCC_PREDIV1_Source: specifies the PREDIV1 clock source.
949 * RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock
950 * RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock
951 * RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
952 * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
953 * Return : None
954 *******************************************************************************/
RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source,uint32_t RCC_PREDIV1_Div)955 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
956 {
957 uint32_t tmpreg = 0;
958
959 tmpreg = RCC->CFGR2;
960 tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
961 tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;
962 RCC->CFGR2 = tmpreg;
963 }
964
965 /*******************************************************************************
966 * Function Name : RCC_PREDIV2Config
967 * Description : Configures the PREDIV2 division factor.
968 * Input : RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.
969 * This parameter can be RCC_PREDIV2_Divx where x:[1,16]
970 * Return : None
971 *******************************************************************************/
RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)972 void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
973 {
974 uint32_t tmpreg = 0;
975
976 tmpreg = RCC->CFGR2;
977 tmpreg &= ~CFGR2_PREDIV2;
978 tmpreg |= RCC_PREDIV2_Div;
979 RCC->CFGR2 = tmpreg;
980 }
981
982 /*******************************************************************************
983 * Function Name : RCC_PLL2Config
984 * Description : Configures the PLL2 multiplication factor.
985 * Input : RCC_PLL2Mul: specifies the PLL2 multiplication factor.
986 * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
987 * Return : None
988 *******************************************************************************/
RCC_PLL2Config(uint32_t RCC_PLL2Mul)989 void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
990 {
991 uint32_t tmpreg = 0;
992
993 tmpreg = RCC->CFGR2;
994 tmpreg &= ~CFGR2_PLL2MUL;
995 tmpreg |= RCC_PLL2Mul;
996 RCC->CFGR2 = tmpreg;
997 }
998
999 /*******************************************************************************
1000 * Function Name : RCC_PLL2Cmd
1001 * Description : Enables or disables the PLL2.
1002 * Input : NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.
1003 * Return : None
1004 *******************************************************************************/
RCC_PLL2Cmd(FunctionalState NewState)1005 void RCC_PLL2Cmd(FunctionalState NewState)
1006 {
1007 if(NewState)
1008 {
1009 RCC->CTLR |= ((uint32_t)1<<26);
1010 }
1011 else{
1012 RCC->CTLR &= ~((uint32_t)1<<26);
1013 }
1014 }
1015
1016 /*******************************************************************************
1017 * Function Name : RCC_PLL3Config
1018 * Description : Configures the PLL3 multiplication factor.
1019 * Input : RCC_PLL3Mul: specifies the PLL3 multiplication factor.
1020 * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}
1021 * Return : None
1022 *******************************************************************************/
RCC_PLL3Config(uint32_t RCC_PLL3Mul)1023 void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
1024 {
1025 uint32_t tmpreg = 0;
1026
1027 tmpreg = RCC->CFGR2;
1028 tmpreg &= ~CFGR2_PLL3MUL;
1029 tmpreg |= RCC_PLL3Mul;
1030 RCC->CFGR2 = tmpreg;
1031 }
1032
1033 /*******************************************************************************
1034 * Function Name : RCC_PLL3Cmd
1035 * Description : Enables or disables the PLL3.
1036 * Input : NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.
1037 * Return : None
1038 *******************************************************************************/
RCC_PLL3Cmd(FunctionalState NewState)1039 void RCC_PLL3Cmd(FunctionalState NewState)
1040 {
1041 if(NewState)
1042 {
1043 RCC->CTLR |= ((uint32_t)1<<28);
1044 }
1045 else{
1046 RCC->CTLR &= ~((uint32_t)1<<28);
1047 }
1048 }
1049
1050 /*******************************************************************************
1051 * Function Name : RCC_OTGFSCLKConfig
1052 * Description : Configures the USB OTG FS clock (OTGFSCLK).
1053 * Input : RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.
1054 * RCC_OTGFSCLKSource_PLLCLK_Div1: PLL clock divided by 1 selected as USB OTG FS clock source
1055 * RCC_OTGFSCLKSource_PLLCLK_Div2: PLL clock divided by 2 selected as USB OTG FS clock source
1056 * RCC_OTGFSCLKSource_PLLCLK_Div3: PLL clock divided by 3 selected as USB OTG FS clock source
1057 * Return : None
1058 *******************************************************************************/
RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)1059 void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
1060 {
1061 RCC->CFGR0 &= ~((uint32_t)3<<22);
1062 RCC->CFGR0 |= RCC_OTGFSCLKSource<<22;
1063 }
1064
1065 /*******************************************************************************
1066 * Function Name : RCC_I2S2CLKConfig
1067 * Description : Configures the I2S2 clock source(I2S2CLK).
1068 * Input : RCC_I2S2CLKSource: specifies the I2S2 clock source.
1069 * RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry
1070 * RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry
1071 * Return : None
1072 *******************************************************************************/
RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)1073 void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
1074 {
1075 RCC->CFGR2 &= ~((uint32_t)1<<17);
1076 RCC->CFGR2 |= RCC_I2S2CLKSource<<17;
1077 }
1078
1079 /*******************************************************************************
1080 * Function Name : RCC_I2S3CLKConfig
1081 * Description : Configures the I2S3 clock source(I2S2CLK).
1082 * Input : RCC_I2S3CLKSource: specifies the I2S3 clock source.
1083 * RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry
1084 * RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry
1085 * Return : None
1086 *******************************************************************************/
RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)1087 void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
1088 {
1089 RCC->CFGR2 &= ~((uint32_t)1<<18);
1090 RCC->CFGR2 |= RCC_I2S3CLKSource<<18;
1091 }
1092
1093 /*******************************************************************************
1094 * Function Name : RCC_AHBPeriphResetCmd
1095 * Description : Forces or releases AHB peripheral reset.
1096 * Input : RCC_AHBPeriph: specifies the AHB peripheral to reset.
1097 * RCC_AHBPeriph_OTG_FS
1098 * RCC_AHBPeriph_ETH_MAC
1099 * NewState: ENABLE or DISABLE.
1100 * Return : None
1101 *******************************************************************************/
RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph,FunctionalState NewState)1102 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
1103 {
1104 if (NewState != DISABLE)
1105 {
1106 RCC->AHBRSTR |= RCC_AHBPeriph;
1107 }
1108 else
1109 {
1110 RCC->AHBRSTR &= ~RCC_AHBPeriph;
1111 }
1112 }
1113
1114 /*******************************************************************************
1115 * Function Name : RCC_ADCCLKADJcmd
1116 * Description : Enable ADC clock duty cycle adjustment.
1117 * Input : NewState: ENABLE or DISABLE.
1118 * Return : None
1119 *******************************************************************************/
RCC_ADCCLKADJcmd(FunctionalState NewState)1120 void RCC_ADCCLKADJcmd(FunctionalState NewState)
1121 {
1122 if (NewState != DISABLE)
1123 {
1124 RCC->CFGR0 |= ((uint32_t)1<<31);
1125 }
1126 else
1127 {
1128 RCC->CFGR0 &= ~((uint32_t)1<<31);
1129 }
1130 }
1131
1132 /*******************************************************************************
1133 * Function Name : RCC_RNGCLKConfig
1134 * Description : Configures the RNG clock source.
1135 * Input : RCC_RNGCLKSource: specifies the RNG clock source.
1136 * RCC_RNGCLKSource_SYSCLK: system clock selected as RNG clock entry
1137 * RCC_RNGCLKSource_PLL3_VCO: PLL3 VCO clock selected as RNG clock entry
1138 * Return : None
1139 *******************************************************************************/
RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource)1140 void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource)
1141 {
1142 RCC->CFGR2 &= ~((uint32_t)1<<19);
1143 RCC->CFGR2 |= RCC_RNGCLKSource<<19;
1144 }
1145
1146 /*******************************************************************************
1147 * Function Name : RCC_ETH1GCLKConfig
1148 * Description : Configures the ETH1G clock source.
1149 * Input : RCC_RNGCLKSource: specifies the ETH1G clock source.
1150 * RCC_ETH1GCLKSource_PLL2_VCO: system clock selected as ETH1G clock entry
1151 * RCC_ETH1GCLKSource_PLL3_VCO: PLL3 VCO clock selected as ETH1G clock entry
1152 * RCC_ETH1GCLKSource_PB1_IN�� GPIO PB1 input clock selected as ETH1G clock entry
1153 * Return : None
1154 *******************************************************************************/
RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource)1155 void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource)
1156 {
1157 RCC->CFGR2 &= ~((uint32_t)3<<20);
1158 RCC->CFGR2 |= RCC_ETH1GCLKSource<<20;
1159 }
1160
1161 /*******************************************************************************
1162 * Function Name : RCC_ETH1G_125Mcmd
1163 * Description : Enable ETH1G 125M.
1164 * Input : NewState: ENABLE or DISABLE.
1165 * Return : None
1166 *******************************************************************************/
RCC_ETH1G_125Mcmd(FunctionalState NewState)1167 void RCC_ETH1G_125Mcmd(FunctionalState NewState)
1168 {
1169 if (NewState != DISABLE)
1170 {
1171 RCC->CFGR2 |= ((uint32_t)1<<22);
1172 }
1173 else
1174 {
1175 RCC->CFGR2 &= ~((uint32_t)1<<22);
1176 }
1177 }
1178
1179 /*******************************************************************************
1180 * Function Name : RCC_USBHSConfig
1181 * Description : Configures the USBHS clock.
1182 * Input : RCC_USBHS: defines the USBHS clock divider.
1183 * RCC_USBPLL_Div1: USBHS clock = USBPLL.
1184 * RCC_USBPLL_Div2: USBHS clock = USBPLL/2.
1185 * RCC_USBPLL_Div3: USBHS clock = USBPLL/3.
1186 * RCC_USBPLL_Div4: USBHS clock = USBPLL/4.
1187 * RCC_USBPLL_Div5: USBHS clock = USBPLL/5.
1188 * RCC_USBPLL_Div6: USBHS clock = USBPLL/6.
1189 * RCC_USBPLL_Div7: USBHS clock = USBPLL/7.
1190 * RCC_USBPLL_Div8: USBHS clock = USBPLL/8.
1191 * Return : None
1192 *******************************************************************************/
RCC_USBHSConfig(uint32_t RCC_USBHS)1193 void RCC_USBHSConfig(uint32_t RCC_USBHS)
1194 {
1195 RCC->CFGR2 &= ~((uint32_t)7<<24);
1196 RCC->CFGR2 |= RCC_USBHS<<24;
1197 }
1198
1199 /*******************************************************************************
1200 * Function Name : RCC_USBHSPLLCLKConfig
1201 * Description : Configures the USBHSPLL clock source.
1202 * Input : RCC_RNGCLKSource: specifies the USBHSPLL clock source.
1203 * RCC_HSBHSPLLCLKSource_HSE: HSE clock selected as USBHSPLL clock entry
1204 * RCC_HSBHSPLLCLKSource_HSI: HSI clock selected as USBHSPLL clock entry
1205 * Return : None
1206 *******************************************************************************/
RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource)1207 void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource)
1208 {
1209 RCC->CFGR2 &= ~((uint32_t)1<<27);
1210 RCC->CFGR2 |= RCC_USBHSPLLCLKSource<<27;
1211 }
1212
1213 /*******************************************************************************
1214 * Function Name : RCC_USBHSPLLCKREFCLKConfig
1215 * Description : Configures the USBHSPLL reference clock.
1216 * Input : RCC_USBHSPLLCKREFCLKSource: Select reference clock.
1217 * RCC_USBHSPLLCKREFCLK_3M: reference clock 3Mhz.
1218 * RCC_USBHSPLLCKREFCLK_4M: reference clock 4Mhz.
1219 * RCC_USBHSPLLCKREFCLK_8M: reference clock 8Mhz.
1220 * RCC_USBHSPLLCKREFCLK_5M: reference clock 5Mhz.
1221 * Return : None
1222 *******************************************************************************/
RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource)1223 void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource)
1224 {
1225 RCC->CFGR2 &= ~((uint32_t)3<<28);
1226 RCC->CFGR2 |= RCC_USBHSPLLCKREFCLKSource<<28;
1227 }
1228
1229 /*******************************************************************************
1230 * Function Name : RCC_USBHSPHYPLLALIVEcmd
1231 * Description : Enable USBHS PHY control.
1232 * Input : NewState: ENABLE or DISABLE.
1233 * Return : None
1234 *******************************************************************************/
RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState)1235 void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState)
1236 {
1237 if (NewState != DISABLE)
1238 {
1239 RCC->CFGR2 |= ((uint32_t)1<<30);
1240 }
1241 else
1242 {
1243 RCC->CFGR2 &= ~((uint32_t)1<<30);
1244 }
1245 }
1246
1247 /*******************************************************************************
1248 * Function Name : RCC_USBCLK48MConfig
1249 * Description : Configures the USB clock 48MHz source.
1250 * Input : RCC_USBCLK48MSource: specifies the USB clock 48MHz source.
1251 * RCC_USBCLK48MCLKSource_PLLCLK: PLLCLK clock selected as USB clock 48MHz clock entry
1252 * RCC_USBCLK48MCLKSource_USBPHY: USBPHY clock selected as USB clock 48MHz clock entry
1253 * Return : None
1254 *******************************************************************************/
RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource)1255 void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource)
1256 {
1257 RCC->CFGR2 &= ~((uint32_t)1<<31);
1258 RCC->CFGR2 |= RCC_USBCLK48MSource<<31;
1259 }
1260