1 /**************************************************************************** 2 * arch/risc-v/include/csr.h 3 * 4 * Licensed to the Apache Software Foundation (ASF) under one or more 5 * contributor license agreements. See the NOTICE file distributed with 6 * this work for additional information regarding copyright ownership. The 7 * ASF licenses this file to you under the Apache License, Version 2.0 (the 8 * "License"); you may not use this file except in compliance with the 9 * License. You may obtain a copy of the License at 10 * 11 * http://www.apache.org/licenses/LICENSE-2.0 12 * 13 * Unless required by applicable law or agreed to in writing, software 14 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT 15 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the 16 * License for the specific language governing permissions and limitations 17 * under the License. 18 * 19 ****************************************************************************/ 20 21 /* This file should never be included directly but, rather, only indirectly 22 * through nuttx/irq.h 23 */ 24 25 #ifndef __ARCH_RISCV_INCLUDE_CSR_H 26 #define __ARCH_RISCV_INCLUDE_CSR_H 27 28 /**************************************************************************** 29 * Included Files 30 ****************************************************************************/ 31 32 /**************************************************************************** 33 * Pre-processor Definitions 34 ****************************************************************************/ 35 36 /* User Trap Registers */ 37 38 #define CSR_USTATUS 0x000 39 #define CSR_UIE 0x004 40 #define CSR_UTVEC 0x005 41 42 /* User Trap Handling Registers */ 43 44 #define CSR_USCRATCH 0x040 45 #define CSR_UEPC 0x041 46 #define CSR_UCAUSE 0x042 47 #define CSR_UTVAL 0x043 48 #define CSR_UIP 0x044 49 50 /* User Floating-Point Registers */ 51 52 #define CSR_FFLAGS 0x001 53 #define CSR_FRM 0x002 54 #define CSR_FCSR 0x003 55 56 /* User Counter/Times Registers */ 57 58 #define CSR_CYCLE 0xC00 59 #define CSR_TIME 0xC01 60 #define CSR_INSTRET 0xC02 61 #define CSR_HPCOUNTER3 0xC03 62 #define CSR_HPCOUNTER4 0xC04 63 #define CSR_HPCOUNTER5 0xC05 64 #define CSR_HPCOUNTER6 0xC06 65 #define CSR_HPCOUNTER7 0xC07 66 #define CSR_HPCOUNTER8 0xC08 67 #define CSR_HPCOUNTER9 0xC09 68 #define CSR_HPCOUNTER10 0xC0A 69 #define CSR_HPCOUNTER11 0xC0B 70 #define CSR_HPCOUNTER12 0xC0C 71 #define CSR_HPCOUNTER13 0xC0D 72 #define CSR_HPCOUNTER14 0xC0E 73 #define CSR_HPCOUNTER15 0xC0F 74 #define CSR_HPCOUNTER16 0xC10 75 #define CSR_HPCOUNTER17 0xC11 76 #define CSR_HPCOUNTER18 0xC12 77 #define CSR_HPCOUNTER19 0xC13 78 #define CSR_HPCOUNTER20 0xC14 79 #define CSR_HPCOUNTER21 0xC15 80 #define CSR_HPCOUNTER22 0xC16 81 #define CSR_HPCOUNTER24 0xC17 82 #define CSR_HPCOUNTER25 0xC18 83 #define CSR_HPCOUNTER26 0xC19 84 #define CSR_HPCOUNTER27 0xC1A 85 #define CSR_HPCOUNTER28 0xC1B 86 #define CSR_HPCOUNTER29 0xC1C 87 #define CSR_HPCOUNTER30 0xC1D 88 #define CSR_HPCOUNTER31 0xC1F 89 #define CSR_CYCLEH 0xC80 90 #define CSR_TIMEH 0xC81 91 #define CSR_INSTRETH 0xC82 92 #define CSR_HPCOUNTER3H 0xC83 93 #define CSR_HPCOUNTER4H 0xC84 94 #define CSR_HPCOUNTER5H 0xC85 95 #define CSR_HPCOUNTER6H 0xC86 96 #define CSR_HPCOUNTER7H 0xC87 97 #define CSR_HPCOUNTER8H 0xC88 98 #define CSR_HPCOUNTER9H 0xC89 99 #define CSR_HPCOUNTER10H 0xC8A 100 #define CSR_HPCOUNTER11H 0xC8B 101 #define CSR_HPCOUNTER12H 0xC8C 102 #define CSR_HPCOUNTER13H 0xC8D 103 #define CSR_HPCOUNTER14H 0xC8E 104 #define CSR_HPCOUNTER15H 0xC8F 105 #define CSR_HPCOUNTER16H 0xC90 106 #define CSR_HPCOUNTER17H 0xC91 107 #define CSR_HPCOUNTER18H 0xC92 108 #define CSR_HPCOUNTER19H 0xC93 109 #define CSR_HPCOUNTER20H 0xC94 110 #define CSR_HPCOUNTER21H 0xC95 111 #define CSR_HPCOUNTER22H 0xC96 112 #define CSR_HPCOUNTER24H 0xC97 113 #define CSR_HPCOUNTER25H 0xC98 114 #define CSR_HPCOUNTER26H 0xC99 115 #define CSR_HPCOUNTER27H 0xC9A 116 #define CSR_HPCOUNTER28H 0xC9B 117 #define CSR_HPCOUNTER29H 0xC9C 118 #define CSR_HPCOUNTER30H 0xC9D 119 #define CSR_HPCOUNTER31H 0xC9F 120 121 /* Supervisor Trap Setup Registers */ 122 123 #define CSR_SSTATUS 0x100 124 #define CSR_SEDELEG 0x102 125 #define CSR_SIDELEG 0x103 126 #define CSR_SIE 0x104 127 #define CSR_STVEC 0x105 128 #define CSR_SCOUNTEREN 0x106 129 130 /* Supervisor Trap Handling Registers */ 131 132 #define CSR_SSCRATCH 0x140 133 #define CSR_SEPC 0x141 134 #define CSR_SCAUSE 0x142 135 #define CSR_STVAL 0x143 136 #define CSR_SIP 0x144 137 138 /* Supervisor Protection and Translation Registers */ 139 140 #define CSR_SATP 0x180 141 142 /* Machine Information Registers */ 143 144 #define CSR_MVENDORID 0xF11 145 #define CSR_MARCHID 0xF12 146 #define CSR_MIMPID 0xF13 147 #define CSR_MHARTID 0xF14 148 149 /* Machine Trap Registers */ 150 151 #define CSR_MSTATUS 0x300 152 #define CSR_MISA 0x301 153 #define CSR_MEDELEG 0x302 154 #define CSR_MIDELEG 0x303 155 #define CSR_MIE 0x304 156 #define CSR_MTVEC 0x305 157 #define CSR_MCOUNTEREN 0x306 158 159 /* Machine Trap Handling */ 160 161 #define CSR_MSCRATCH 0x340 162 #define CSR_MEPC 0x341 163 #define CSR_MCAUSE 0x342 164 #define CSR_MTVAL 0x343 165 #define CSR_MIP 0x344 166 167 /* Machine Protection and Translation */ 168 169 #define CSR_PMPCFG0 0x3A0 170 #define CSR_PMPCFG1 0x3A1 171 #define CSR_PMPCFG2 0x3A2 172 #define CSR_PMPCFG3 0x3A3 173 #define CSR_PMPADDR0 0x3B0 174 #define CSR_PMPADDR1 0x3B1 175 #define CSR_PMPADDR2 0x3B2 176 #define CSR_PMPADDR3 0x3B3 177 #define CSR_PMPADDR4 0x3B4 178 #define CSR_PMPADDR5 0x3B5 179 #define CSR_PMPADDR6 0x3B6 180 #define CSR_PMPADDR7 0x3B7 181 #define CSR_PMPADDR8 0x3B8 182 #define CSR_PMPADDR9 0x3B9 183 #define CSR_PMPADDR10 0x3BA 184 #define CSR_PMPADDR11 0x3BB 185 #define CSR_PMPADDR12 0x3BC 186 #define CSR_PMPADDR13 0x3BD 187 #define CSR_PMPADDR14 0x3BE 188 #define CSR_PMPADDR15 0x3BF 189 190 /* Machine Timers and Counters */ 191 192 #define CSR_MCYCLE 0xB00 193 #define CSR_MINSTRET 0xB02 194 #define CSR_MHPMCOUNTER3 0xB03 195 #define CSR_MHPMCOUNTER4 0xB04 196 #define CSR_MHPMCOUNTER5 0xB05 197 #define CSR_MHPMCOUNTER6 0xB06 198 #define CSR_MHPMCOUNTER7 0xB07 199 #define CSR_MHPMCOUNTER8 0xB08 200 #define CSR_MHPMCOUNTER9 0xB09 201 #define CSR_MHPMCOUNTER10 0xB0A 202 #define CSR_MHPMCOUNTER11 0xB0B 203 #define CSR_MHPMCOUNTER12 0xB0C 204 #define CSR_MHPMCOUNTER13 0xB0D 205 #define CSR_MHPMCOUNTER14 0xB0E 206 #define CSR_MHPMCOUNTER15 0xB0F 207 #define CSR_MHPMCOUNTER16 0xB10 208 #define CSR_MHPMCOUNTER17 0xB11 209 #define CSR_MHPMCOUNTER18 0xB12 210 #define CSR_MHPMCOUNTER19 0xB13 211 #define CSR_MHPMCOUNTER20 0xB14 212 #define CSR_MHPMCOUNTER21 0xB15 213 #define CSR_MHPMCOUNTER22 0xB16 214 #define CSR_MHPMCOUNTER23 0xB17 215 #define CSR_MHPMCOUNTER24 0xB18 216 #define CSR_MHPMCOUNTER25 0xB19 217 #define CSR_MHPMCOUNTER26 0xB1A 218 #define CSR_MHPMCOUNTER27 0xB1B 219 #define CSR_MHPMCOUNTER28 0xB1C 220 #define CSR_MHPMCOUNTER29 0xB1D 221 #define CSR_MHPMCOUNTER30 0xB1E 222 #define CSR_MHPMCOUNTER31 0xB1F 223 #define CSR_MCYCLEH 0xB80 224 #define CSR_MINSTRETH 0xB82 225 #define CSR_MHPMCOUNTER3H 0xB83 226 #define CSR_MHPMCOUNTER4H 0xB84 227 #define CSR_MHPMCOUNTER5H 0xB85 228 #define CSR_MHPMCOUNTER6H 0xB86 229 #define CSR_MHPMCOUNTER7H 0xB87 230 #define CSR_MHPMCOUNTER8H 0xB88 231 #define CSR_MHPMCOUNTER9H 0xB89 232 #define CSR_MHPMCOUNTER10H 0xB8A 233 #define CSR_MHPMCOUNTER11H 0xB8B 234 #define CSR_MHPMCOUNTER12H 0xB8C 235 #define CSR_MHPMCOUNTER13H 0xB8D 236 #define CSR_MHPMCOUNTER14H 0xB8E 237 #define CSR_MHPMCOUNTER15H 0xB8F 238 #define CSR_MHPMCOUNTER16H 0xB90 239 #define CSR_MHPMCOUNTER17H 0xB91 240 #define CSR_MHPMCOUNTER18H 0xB92 241 #define CSR_MHPMCOUNTER19H 0xB93 242 #define CSR_MHPMCOUNTER20H 0xB94 243 #define CSR_MHPMCOUNTER21H 0xB95 244 #define CSR_MHPMCOUNTER22H 0xB96 245 #define CSR_MHPMCOUNTER23H 0xB97 246 #define CSR_MHPMCOUNTER24H 0xB98 247 #define CSR_MHPMCOUNTER25H 0xB99 248 #define CSR_MHPMCOUNTER26H 0xB9A 249 #define CSR_MHPMCOUNTER27H 0xB9B 250 #define CSR_MHPMCOUNTER28H 0xB9C 251 #define CSR_MHPMCOUNTER29H 0xB9D 252 #define CSR_MHPMCOUNTER30H 0xB9E 253 #define CSR_MHPMCOUNTER31H 0xB9F 254 255 /* Machine Counter Setup */ 256 257 #define CSR_MPHEVENT3 0x323 258 #define CSR_MPHEVENT4 0x324 259 #define CSR_MPHEVENT5 0x325 260 #define CSR_MPHEVENT6 0x326 261 #define CSR_MPHEVENT7 0x327 262 #define CSR_MPHEVENT8 0x328 263 #define CSR_MPHEVENT9 0x329 264 #define CSR_MPHEVENT10 0x32A 265 #define CSR_MPHEVENT11 0x32B 266 #define CSR_MPHEVENT12 0x32C 267 #define CSR_MPHEVENT13 0x32D 268 #define CSR_MPHEVENT14 0x32E 269 #define CSR_MPHEVENT15 0x32F 270 #define CSR_MPHEVENT16 0x330 271 #define CSR_MPHEVENT17 0x331 272 #define CSR_MPHEVENT18 0x332 273 #define CSR_MPHEVENT19 0x333 274 #define CSR_MPHEVENT20 0x334 275 #define CSR_MPHEVENT21 0x335 276 #define CSR_MPHEVENT22 0x336 277 #define CSR_MPHEVENT23 0x337 278 #define CSR_MPHEVENT24 0x338 279 #define CSR_MPHEVENT25 0x339 280 #define CSR_MPHEVENT26 0x33A 281 #define CSR_MPHEVENT27 0x33B 282 #define CSR_MPHEVENT28 0x33C 283 #define CSR_MPHEVENT29 0x33D 284 #define CSR_MPHEVENT30 0x33E 285 #define CSR_MPHEVENT31 0x33F 286 287 /* Debug/Trace Registers */ 288 289 #define CSR_TSELECT 0x7A0 290 #define CSR_TDATA1 0x7A1 291 #define CSR_TDATA2 0x7A2 292 #define CSR_TDATA3 0x7A3 293 294 /* Debug interface CSRs */ 295 296 #define CSR_DCSR 0x7B0 297 #define CSR_DPC 0x7B1 298 #define CSR_DSCRATCH 0x7B2 299 300 /* In mstatus register */ 301 #define MSTATUS_SIE (0x1 << 1) /* Superior Interrupt Enable */ 302 #define MSTATUS_MIE (0x1 << 3) /* Machine Interrupt Enable */ 303 #define MSTATUS_MPIE (0x1 << 7) /* Machine Previous Interrupt Enable */ 304 #define MSTATUS_MPPM (0x3 << 11) /* Machine Previous Privilege (m-mode) */ 305 #define MSTATUS_FS (0x3 << 13) /* Machine Floating-point Status */ 306 #define MSTATUS_FS_INIT (0x1 << 13) 307 #define MSTATUS_FS_CLEAN (0x2 << 13) 308 #define MSTATUS_FS_DIRTY (0x3 << 13) 309 310 /* In mie (machine interrupt enable) register */ 311 312 #define MIE_MSIE (0x1 << 3) /* Machine Software Interrupt Enable */ 313 #define MIE_MTIE (0x1 << 7) /* Machine Timer Interrupt Enable */ 314 #define MIE_MEIE (0x1 << 11) /* Machine External Interrupt Enable */ 315 316 /* In mip (machine interrupt pending) register */ 317 318 #define MIP_MTIP (0x1 << 7) 319 320 #define CSR_STR(csr) #csr 321 322 #define READ_CSR(reg) \ 323 ({ \ 324 unsigned long tmp; \ 325 asm volatile("csrr %0, " CSR_STR(reg) : "=r"(tmp)); \ 326 tmp; \ 327 }) 328 329 #define WRITE_CSR(reg, val) \ 330 ({ \ 331 asm volatile("csrw " CSR_STR(reg) ", %0" :: "rK"(val)); \ 332 }) 333 334 #define SET_CSR(reg, bits) \ 335 ({ \ 336 asm volatile("csrs " CSR_STR(reg) ", %0" :: "rK"(bits)); \ 337 }) 338 339 #define CLEAR_CSR(reg, bits) \ 340 ({ \ 341 asm volatile("csrc " CSR_STR(reg) ", %0" :: "rK"(bits)); \ 342 }) 343 344 /* In pmpcfg (PMP configuration) register */ 345 346 #define PMPCFG_R (1 << 0) /* readable ? */ 347 #define PMPCFG_W (1 << 1) /* writeable ? */ 348 #define PMPCFG_X (1 << 2) /* excutable ? */ 349 #define PMPCFG_A_OFF (0 << 3) /* null region (disabled) */ 350 #define PMPCFG_A_TOR (1 << 3) /* top of range */ 351 #define PMPCFG_A_NA4 (2 << 3) /* naturally aligned four-byte region */ 352 #define PMPCFG_A_NAPOT (3 << 3) /* naturally aligned power-of-two region */ 353 #define PMPCFG_A_MASK (3 << 3) /* address-matching mode mask */ 354 #define PMPCFG_L (1 << 7) /* locked ? */ 355 356 /**************************************************************************** 357 * Public Types 358 ****************************************************************************/ 359 360 /**************************************************************************** 361 * Public Function Prototypes 362 ****************************************************************************/ 363 364 #endif /* __ARCH_RISCV_INCLUDE_CSR_H */ 365