1 // SPDX-License-Identifier: (GPL-2.0+ or MIT) 2 /* 3 * Copyright (c) 2020 huangzhenwei@allwinnertech.com 4 */ 5 6 #ifndef _DT_BINDINGS_RESET_SUN8IW20_H_ 7 #define _DT_BINDINGS_RESET_SUN8IW20_H_ 8 9 #define RST_MBUS 0 10 #define RST_BUS_DE0 1 11 #define RST_BUS_DI 2 12 #define RST_BUS_G2D 3 13 #define RST_BUS_CE 4 14 #define RST_BUS_VE 5 15 #define RST_BUS_DMA 6 16 #define RST_BUS_MSGBOX0 7 17 #define RST_BUS_MSGBOX1 8 18 #define RST_BUS_MSGBOX2 9 19 #define RST_BUS_SPINLOCK 10 20 #define RST_BUS_HSTIMER 11 21 #define RST_BUS_DBG 12 22 #define RST_BUS_PWM 13 23 #define RST_BUS_DRAM 14 24 #define RST_BUS_MMC0 15 25 #define RST_BUS_MMC1 16 26 #define RST_BUS_MMC2 17 27 #define RST_BUS_UART0 18 28 #define RST_BUS_UART1 19 29 #define RST_BUS_UART2 20 30 #define RST_BUS_UART3 21 31 #define RST_BUS_UART4 22 32 #define RST_BUS_UART5 23 33 #define RST_BUS_I2C0 24 34 #define RST_BUS_I2C1 25 35 #define RST_BUS_I2C2 26 36 #define RST_BUS_I2C3 27 37 #define RST_BUS_CAN0 28 38 #define RST_BUS_CAN1 29 39 #define RST_BUS_SPI0 30 40 #define RST_BUS_SPI1 31 41 #define RST_BUS_EMAC0 32 42 #define RST_BUS_IR_TX 33 43 #define RST_BUS_GPADC 34 44 #define RST_BUS_THS 35 45 #define RST_BUS_I2S0 36 46 #define RST_BUS_I2S1 37 47 #define RST_BUS_I2S2 38 48 #define RST_BUS_SPDIF 39 49 #define RST_BUS_DMIC 40 50 #define RST_BUS_AUDIO_CODEC 41 51 #define RST_USB_PHY0 42 52 #define RST_USB_PHY1 43 53 #define RST_BUS_OHCI0 44 54 #define RST_BUS_OHCI1 45 55 #define RST_BUS_EHCI0 46 56 #define RST_BUS_EHCI1 47 57 #define RST_BUS_OTG 48 58 #define RST_BUS_LRADC 49 59 #define RST_BUS_DPSS_TOP0 50 60 #define RST_BUS_HDMI_SUB 51 61 #define RST_BUS_HDMI_MAIN 52 62 #define RST_BUS_MIPI_DSI 53 63 #define RST_BUS_TCON_LCD0 54 64 #define RST_BUS_TCON_TV 55 65 #define RST_BUS_LVDS0 56 66 #define RST_BUS_TVE 57 67 #define RST_BUS_TVE_TOP 58 68 #define RST_BUS_TVD 59 69 #define RST_BUS_TVD_TOP 60 70 #define RST_BUS_LEDC 61 71 #define RST_BUS_CSI 62 72 #define RST_BUS_TPADC 63 73 #define RST_BUS_DSP 64 74 #define RST_BUS_DSP_CFG 65 75 #define RST_BUS_DSP_DBG 66 76 #define RST_BUS_RISCV_CFG 67 77 #define RST_BUS_RISCV_SOFT 69 78 #define RST_BUS_RISCV_CPU_SOFT 70 79 80 #define RST_BUS_NUMBER (RST_BUS_RISCV_CFG + 1) 81 82 83 #endif /* _DT_BINDINGS_RESET_SUN8IW20_H_ */ 84