1;***************************************************************************** 2;* @file start_cmem7.h 3;* 4;* @brief CMEM7 startup file 5;* 6;* 7;* @version V1.0 8;* @date 3. September 2013 9;* 10;* @note 11;* 12;***************************************************************************** 13;* @attention 14;* 15;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 16;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 17;* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 18;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 19;* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 20;* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 21;* 22;* <h2><center>© COPYRIGHT 2013 Capital-micro </center></h2> 23;***************************************************************************** 24 25; Amount of memory (in bytes) allocated for Stack 26; Tailor this value to your application needs 27; <h> Stack Configuration 28; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 29; </h> 30 31Stack_Size EQU 0x00000400 32 33 AREA STACK, NOINIT, READWRITE, ALIGN=3 34Stack_Mem SPACE Stack_Size 35__initial_sp 36 37 38; <h> Heap Configuration 39; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 40; </h> 41 42Heap_Size EQU 0x00000200 43 44 AREA HEAP, NOINIT, READWRITE, ALIGN=3 45__heap_base 46Heap_Mem SPACE Heap_Size 47__heap_limit 48 49 PRESERVE8 50 THUMB 51 52 53; Vector Table Mapped to Address 0 at Reset 54 AREA RESET, DATA, READONLY 55 EXPORT __Vectors 56 EXPORT __Vectors_End 57 EXPORT __Vectors_Size 58 59__Vectors DCD __initial_sp ; Top of Stack 60 DCD Reset_Handler ; Reset Handler 61 DCD NMI_Handler ; NMI Handler 62 DCD HardFault_Handler ; Hard Fault Handler 63 DCD MemManage_Handler ; MPU Fault Handler 64 DCD BusFault_Handler ; Bus Fault Handler 65 DCD UsageFault_Handler ; Usage Fault Handler 66 DCD 0 ; Reserved 67 DCD 0 ; Reserved 68 DCD 0 ; Reserved 69 DCD 0 ; Reserved 70 DCD SVC_Handler ; SVCall Handler 71 DCD DebugMon_Handler ; Debug Monitor Handler 72 DCD 0 ; Reserved 73 DCD PendSV_Handler ; PendSV Handler 74 DCD SysTick_Handler ; SysTick Handler 75 76 ; External Interrupts 77 DCD ETH_IRQHandler ; ETH 78 DCD USB_IRQHandler ; USB 79 DCD DMAC_IRQHandler ; DMAC 80 DCD CAN0_IRQHandler ; CAN0 81 DCD CAN1_IRQHandler ; CAN1 82 DCD FP0_IRQHandler ; FP[0:15] 83 DCD FP1_IRQHandler 84 DCD FP2_IRQHandler 85 DCD FP3_IRQHandler 86 DCD FP4_IRQHandler 87 DCD FP5_IRQHandler 88 DCD FP6_IRQHandler 89 DCD FP7_IRQHandler 90 DCD FP8_IRQHandler 91 DCD FP9_IRQHandler 92 DCD FP10_IRQHandler 93 DCD FP11_IRQHandler 94 DCD FP12_IRQHandler 95 DCD FP13_IRQHandler 96 DCD FP14_IRQHandler 97 DCD FP15_IRQHandler ; 21 98 DCD UART0_IRQHandler ; UART0 99 DCD UART1_IRQHandler ; UART1 100 DCD ADC_IRQHandler ; ADC 101 DCD GPIO_IRQHandler ; GPIO 102 DCD SPI1_IRQHandler ; SPI1 103 DCD I2C1_IRQHandler ; I2C1 104 DCD SPI0_IRQHandler ; SPI0 105 DCD I2C0_IRQHandler ; I2C0 106 DCD RTC_1S_IRQHandler ; RTC 1S 107 DCD RTC_1MS_IRQHandler ; RTC 1MS 108 DCD WDG_IRQHandler ; Watchdog 109 DCD TIMER_IRQHandler ; Timer 0 || 1 || 2 || 3 110 DCD DDRC_SW_PROC_IRQHandler ; DDRC sw proc 111 DCD ETH_PMT_IRQHandler ; ETH pmt 112 DCD PAD_IRQHandler ; PAD 113 DCD DDRC_LANE_SYNC_IRQHandler ; DDRC lane sync 114 DCD UART2_IRQHandler ; UART2 115 116__Vectors_End 117 118__Vectors_Size EQU __Vectors_End - __Vectors 119 120 AREA |.text|, CODE, READONLY 121 122; Reset handler 123Reset_Handler PROC 124 EXPORT Reset_Handler [WEAK] 125 IMPORT SystemInit 126 IMPORT __main 127 LDR R0, =SystemInit 128 BLX R0 129 LDR R0, =__main 130 BX R0 131 ENDP 132 133; Dummy Exception Handlers (infinite loops which can be modified) 134 135NMI_Handler PROC 136 EXPORT NMI_Handler [WEAK] 137 B . 138 ENDP 139HardFault_Handler\ 140 PROC 141 EXPORT HardFault_Handler [WEAK] 142 B . 143 ENDP 144MemManage_Handler\ 145 PROC 146 EXPORT MemManage_Handler [WEAK] 147 B . 148 ENDP 149BusFault_Handler\ 150 PROC 151 EXPORT BusFault_Handler [WEAK] 152 B . 153 ENDP 154UsageFault_Handler\ 155 PROC 156 EXPORT UsageFault_Handler [WEAK] 157 B . 158 ENDP 159SVC_Handler PROC 160 EXPORT SVC_Handler [WEAK] 161 B . 162 ENDP 163DebugMon_Handler\ 164 PROC 165 EXPORT DebugMon_Handler [WEAK] 166 B . 167 ENDP 168PendSV_Handler PROC 169 EXPORT PendSV_Handler [WEAK] 170 B . 171 ENDP 172SysTick_Handler PROC 173 EXPORT SysTick_Handler [WEAK] 174 B . 175 ENDP 176 177Default_Handler PROC 178 EXPORT ETH_IRQHandler [WEAK] 179 EXPORT USB_IRQHandler [WEAK] 180 EXPORT DMAC_IRQHandler [WEAK] 181 EXPORT CAN0_IRQHandler [WEAK] 182 EXPORT CAN1_IRQHandler [WEAK] 183 EXPORT FP0_IRQHandler [WEAK] 184 EXPORT FP1_IRQHandler [WEAK] 185 EXPORT FP2_IRQHandler [WEAK] 186 EXPORT FP3_IRQHandler [WEAK] 187 EXPORT FP4_IRQHandler [WEAK] 188 EXPORT FP5_IRQHandler [WEAK] 189 EXPORT FP6_IRQHandler [WEAK] 190 EXPORT FP7_IRQHandler [WEAK] 191 EXPORT FP8_IRQHandler [WEAK] 192 EXPORT FP9_IRQHandler [WEAK] 193 EXPORT FP10_IRQHandler [WEAK] 194 EXPORT FP11_IRQHandler [WEAK] 195 EXPORT FP12_IRQHandler [WEAK] 196 EXPORT FP13_IRQHandler [WEAK] 197 EXPORT FP14_IRQHandler [WEAK] 198 EXPORT FP15_IRQHandler [WEAK] 199 EXPORT UART0_IRQHandler [WEAK] 200 EXPORT UART1_IRQHandler [WEAK] 201 EXPORT ADC_IRQHandler [WEAK] 202 EXPORT GPIO_IRQHandler [WEAK] 203 EXPORT SPI1_IRQHandler [WEAK] 204 EXPORT I2C1_IRQHandler [WEAK] 205 EXPORT SPI0_IRQHandler [WEAK] 206 EXPORT I2C0_IRQHandler [WEAK] 207 EXPORT RTC_1S_IRQHandler [WEAK] 208 EXPORT RTC_1MS_IRQHandler [WEAK] 209 EXPORT WDG_IRQHandler [WEAK] 210 EXPORT TIMER_IRQHandler [WEAK] 211 EXPORT DDRC_SW_PROC_IRQHandler [WEAK] 212 EXPORT ETH_PMT_IRQHandler [WEAK] 213 EXPORT PAD_IRQHandler [WEAK] 214 EXPORT DDRC_LANE_SYNC_IRQHandler [WEAK] 215 EXPORT UART2_IRQHandler [WEAK] 216ETH_IRQHandler 217USB_IRQHandler 218DMAC_IRQHandler 219CAN0_IRQHandler 220CAN1_IRQHandler 221FP0_IRQHandler 222FP1_IRQHandler 223FP2_IRQHandler 224FP3_IRQHandler 225FP4_IRQHandler 226FP5_IRQHandler 227FP6_IRQHandler 228FP7_IRQHandler 229FP8_IRQHandler 230FP9_IRQHandler 231FP10_IRQHandler 232FP11_IRQHandler 233FP12_IRQHandler 234FP13_IRQHandler 235FP14_IRQHandler 236FP15_IRQHandler 237UART0_IRQHandler 238UART1_IRQHandler 239ADC_IRQHandler 240GPIO_IRQHandler 241SPI1_IRQHandler 242I2C1_IRQHandler 243SPI0_IRQHandler 244I2C0_IRQHandler 245RTC_1S_IRQHandler 246RTC_1MS_IRQHandler 247WDG_IRQHandler 248TIMER_IRQHandler 249DDRC_SW_PROC_IRQHandler 250ETH_PMT_IRQHandler 251PAD_IRQHandler 252DDRC_LANE_SYNC_IRQHandler 253UART2_IRQHandler 254 B . 255 256 ENDP 257 258 ALIGN 259 260;******************************************************************************* 261; User Stack and Heap initialization 262;******************************************************************************* 263 IF :DEF:__MICROLIB 264 265 EXPORT __initial_sp 266 EXPORT __heap_base 267 EXPORT __heap_limit 268 269 ELSE 270 271 IMPORT __use_two_region_memory 272 EXPORT __user_initial_stackheap 273 274__user_initial_stackheap 275 276 LDR R0, = Heap_Mem 277 LDR R1, =(Stack_Mem + Stack_Size) 278 LDR R2, = (Heap_Mem + Heap_Size) 279 LDR R3, = Stack_Mem 280 BX LR 281 282 ALIGN 283 284 ENDIF 285 286 END 287 288;******************* (C) COPYRIGHT 2011 Capital Micro *****END OF FILE***** 289