1 /** 2 ****************************************************************************** 3 * @file ald_rtchw.h 4 * @brief Header file of RTCHW Module driver. 5 * 6 * @version V1.0 7 * @date 16 Nov 2019 8 * @author AE Team 9 * @note 10 * Change Logs: 11 * Date Author Notes 12 * 16 Nov 2019 AE Team The first version 13 * 14 * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. 15 * 16 * SPDX-License-Identifier: Apache-2.0 17 * 18 * Licensed under the Apache License, Version 2.0 (the License); you may 19 * not use this file except in compliance with the License. 20 * You may obtain a copy of the License at 21 * 22 * www.apache.org/licenses/LICENSE-2.0 23 * 24 * Unless required by applicable law or agreed to in writing, software 25 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 26 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 27 * See the License for the specific language governing permissions and 28 * limitations under the License. 29 ********************************************************************************** 30 */ 31 32 #ifndef __ALD_RTCHW_H__ 33 #define __ALD_RTCHW_H__ 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 #include "utils.h" 40 41 42 /** @addtogroup ES32FXXX_ALD 43 * @{ 44 */ 45 46 /** @addtogroup RTCHW 47 * @{ 48 */ 49 50 /** @defgroup RTCHW_Public_Types RTCHW Public Types 51 * @{ 52 */ 53 /** 54 * @brief Hardware calibration algorithm 55 */ 56 typedef enum { 57 RTC_CALI_MODE_NORMAL = 0U, /**< Normal mode */ 58 RTC_CALI_MODE_SLEEP = 1U, /**< Low power mode */ 59 } rtc_hw_cali_mode_t; 60 61 /** 62 * @brief the parameters table of rtc calibration 63 */ 64 typedef struct { 65 uint32_t MODE_CALI; /**< Calibration Mode */ 66 uint32_t RTC_CALCR; /**< CALCR */ 67 uint32_t RTC_TEMPBDR; /**< TEMPBDR */ 68 uint32_t TEMP_TBDR; /**< TBDR */ 69 uint32_t RTC_LTAXR; /**< LTAXR */ 70 uint32_t RTC_HTAXR; /**< HTAXR */ 71 uint32_t RTC_LTCAR; /**< LTCAR */ 72 uint32_t RTC_LTCBR; /**< LTCBR */ 73 uint32_t RTC_LTCCR; /**< LTCCR */ 74 uint32_t RTC_LTCDR; /**< LTCDR */ 75 uint32_t RTC_HTCAR; /**< HTCAR */ 76 uint32_t RTC_HTCBR; /**< HTCBR */ 77 uint32_t RTC_HTCCR; /**< HTCCR */ 78 uint32_t RTC_HTCDR; /**< HTCDR */ 79 uint32_t TEMP_LTGR; /**< LTGR */ 80 uint32_t TEMP_HTGR; /**< HTGR */ 81 uint32_t TEMP_CR; /**< CR */ 82 uint32_t rsv0; /**< Reserved */ 83 uint32_t RTC_LTCER; /**< LTCER */ 84 uint32_t RTC_HTCER; /**< HTCER */ 85 uint32_t TEMP_PEAK; /**< PEAK */ 86 uint32_t FREQ_PEAK; /**< PEAK */ 87 uint32_t TEMP_CALI; /**< CALI */ 88 uint32_t TEMP_CALI_AFTER; /**< AFTER */ 89 uint32_t TEMP_TCALBDR; /**< TCALBDR */ 90 uint32_t TEMP_TCALBDR_MINUS; /**< TCALBDR_MINUS */ 91 uint32_t rsv1[4]; /**< Reserved */ 92 uint32_t SUM; /**< SUM */ 93 uint32_t SUM_MINUS; /**< SUM_MINUS */ 94 } RTCINFO_TypeDef; 95 96 /** 97 * @brief Hardware calibration structure 98 */ 99 typedef struct { 100 int16_t offset_rtc_bdr; /**< offset:0x00 */ 101 int16_t offset_temp_bdr; /**< offset:0x02 */ 102 int16_t offset_ltaxr; /**< offset:0x04 */ 103 int16_t offset_htaxr; /**< offset:0x06 */ 104 int16_t offset_ltcar; /**< offset:0x08 */ 105 int16_t offset_ltcbr; /**< offset:0x0A */ 106 int16_t offset_ltccr; /**< offset:0x0C */ 107 int16_t offset_ltcdr; /**< offset:0x0E */ 108 int16_t offset_htcar; /**< offset:0x10 */ 109 int16_t offset_htcbr; /**< offset:0x12 */ 110 int16_t offset_htccr; /**< offset:0x14 */ 111 int16_t offset_htcdr; /**< offset:0x16 */ 112 int16_t offset_ltgr; /**< offset:0x18 */ 113 int16_t offset_htgr; /**< offset:0x1A */ 114 int16_t offset_ltcer; /**< offset:0x1C */ 115 int16_t offset_htcer; /**< offset:0x1E */ 116 int16_t offset_temp_peak; /**< offset:0x20 */ 117 int16_t offset_freq_peak; /**< offset:0x22 */ 118 int16_t offset_tcalbdr; /**< offset:0x24 */ 119 int16_t crc; /**< offset:0x26 */ 120 int16_t rsv[8]; 121 } rtc_hw_cali_offset_t; 122 /** 123 * @} 124 */ 125 /** @defgroup RTCHW_Private_Macros RTCHW Private Macros 126 * @{ 127 */ 128 #ifndef RTC_LOCK 129 #define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0U)) 130 #define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55U)) 131 #endif 132 133 #ifndef TSENSE_LOCK 134 #define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U)) 135 #define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U)) 136 #endif 137 138 #define RTCINFO ((RTCINFO_TypeDef *)0x81000U) 139 /** 140 * @} 141 */ 142 143 /** @addtogroup RTCHW_Public_Functions 144 * @{ 145 */ 146 /* Calibration functions */ 147 void ald_rtc_hw_auto_cali(rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode); 148 /** 149 * @} 150 */ 151 /** 152 * @} 153 */ 154 /** 155 * @} 156 */ 157 #ifdef __cplusplus 158 } 159 #endif 160 #endif 161