1 //########################################################################### 2 // 3 // FILE: F2837xD_pievect.h 4 // 5 // TITLE: F2837xD Device PIE Vector Table Definitions 6 // 7 //########################################################################### 8 // $TI Release: F2837xD Support Library v3.05.00.00 $ 9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ 10 // $Copyright: 11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ 12 // 13 // Redistribution and use in source and binary forms, with or without 14 // modification, are permitted provided that the following conditions 15 // are met: 16 // 17 // Redistributions of source code must retain the above copyright 18 // notice, this list of conditions and the following disclaimer. 19 // 20 // Redistributions in binary form must reproduce the above copyright 21 // notice, this list of conditions and the following disclaimer in the 22 // documentation and/or other materials provided with the 23 // distribution. 24 // 25 // Neither the name of Texas Instruments Incorporated nor the names of 26 // its contributors may be used to endorse or promote products derived 27 // from this software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 // $ 41 //########################################################################### 42 43 #ifndef F2837xD_PIE_VECT_H 44 #define F2837xD_PIE_VECT_H 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 //--------------------------------------------------------------------------- 50 // PIE Interrupt Vector Table Definition: 51 // Create a user type called PINT (pointer to interrupt): 52 53 typedef __interrupt void (*PINT)(void); 54 55 // Define Vector Table: 56 struct PIE_VECT_TABLE { 57 PINT PIE1_RESERVED_INT; // Reserved 58 PINT PIE2_RESERVED_INT; // Reserved 59 PINT PIE3_RESERVED_INT; // Reserved 60 PINT PIE4_RESERVED_INT; // Reserved 61 PINT PIE5_RESERVED_INT; // Reserved 62 PINT PIE6_RESERVED_INT; // Reserved 63 PINT PIE7_RESERVED_INT; // Reserved 64 PINT PIE8_RESERVED_INT; // Reserved 65 PINT PIE9_RESERVED_INT; // Reserved 66 PINT PIE10_RESERVED_INT; // Reserved 67 PINT PIE11_RESERVED_INT; // Reserved 68 PINT PIE12_RESERVED_INT; // Reserved 69 PINT PIE13_RESERVED_INT; // Reserved 70 PINT TIMER1_INT; // CPU Timer 1 Interrupt 71 PINT TIMER2_INT; // CPU Timer 2 Interrupt 72 PINT DATALOG_INT; // Datalogging Interrupt 73 PINT RTOS_INT; // RTOS Interrupt 74 PINT EMU_INT; // Emulation Interrupt 75 PINT NMI_INT; // Non-Maskable Interrupt 76 PINT ILLEGAL_INT; // Illegal Operation Trap 77 PINT USER1_INT; // User Defined Trap 1 78 PINT USER2_INT; // User Defined Trap 2 79 PINT USER3_INT; // User Defined Trap 3 80 PINT USER4_INT; // User Defined Trap 4 81 PINT USER5_INT; // User Defined Trap 5 82 PINT USER6_INT; // User Defined Trap 6 83 PINT USER7_INT; // User Defined Trap 7 84 PINT USER8_INT; // User Defined Trap 8 85 PINT USER9_INT; // User Defined Trap 9 86 PINT USER10_INT; // User Defined Trap 10 87 PINT USER11_INT; // User Defined Trap 11 88 PINT USER12_INT; // User Defined Trap 12 89 PINT ADCA1_INT; // 1.1 - ADCA Interrupt 1 90 PINT ADCB1_INT; // 1.2 - ADCB Interrupt 1 91 PINT ADCC1_INT; // 1.3 - ADCC Interrupt 1 92 PINT XINT1_INT; // 1.4 - XINT1 Interrupt 93 PINT XINT2_INT; // 1.5 - XINT2 Interrupt 94 PINT ADCD1_INT; // 1.6 - ADCD Interrupt 1 95 PINT TIMER0_INT; // 1.7 - Timer 0 Interrupt 96 PINT WAKE_INT; // 1.8 - Standby and Halt Wakeup Interrupt 97 PINT EPWM1_TZ_INT; // 2.1 - ePWM1 Trip Zone Interrupt 98 PINT EPWM2_TZ_INT; // 2.2 - ePWM2 Trip Zone Interrupt 99 PINT EPWM3_TZ_INT; // 2.3 - ePWM3 Trip Zone Interrupt 100 PINT EPWM4_TZ_INT; // 2.4 - ePWM4 Trip Zone Interrupt 101 PINT EPWM5_TZ_INT; // 2.5 - ePWM5 Trip Zone Interrupt 102 PINT EPWM6_TZ_INT; // 2.6 - ePWM6 Trip Zone Interrupt 103 PINT EPWM7_TZ_INT; // 2.7 - ePWM7 Trip Zone Interrupt 104 PINT EPWM8_TZ_INT; // 2.8 - ePWM8 Trip Zone Interrupt 105 PINT EPWM1_INT; // 3.1 - ePWM1 Interrupt 106 PINT EPWM2_INT; // 3.2 - ePWM2 Interrupt 107 PINT EPWM3_INT; // 3.3 - ePWM3 Interrupt 108 PINT EPWM4_INT; // 3.4 - ePWM4 Interrupt 109 PINT EPWM5_INT; // 3.5 - ePWM5 Interrupt 110 PINT EPWM6_INT; // 3.6 - ePWM6 Interrupt 111 PINT EPWM7_INT; // 3.7 - ePWM7 Interrupt 112 PINT EPWM8_INT; // 3.8 - ePWM8 Interrupt 113 PINT ECAP1_INT; // 4.1 - eCAP1 Interrupt 114 PINT ECAP2_INT; // 4.2 - eCAP2 Interrupt 115 PINT ECAP3_INT; // 4.3 - eCAP3 Interrupt 116 PINT ECAP4_INT; // 4.4 - eCAP4 Interrupt 117 PINT ECAP5_INT; // 4.5 - eCAP5 Interrupt 118 PINT ECAP6_INT; // 4.6 - eCAP6 Interrupt 119 PINT PIE14_RESERVED_INT; // 4.7 - Reserved 120 PINT PIE15_RESERVED_INT; // 4.8 - Reserved 121 PINT EQEP1_INT; // 5.1 - eQEP1 Interrupt 122 PINT EQEP2_INT; // 5.2 - eQEP2 Interrupt 123 PINT EQEP3_INT; // 5.3 - eQEP3 Interrupt 124 PINT PIE16_RESERVED_INT; // 5.4 - Reserved 125 PINT PIE17_RESERVED_INT; // 5.5 - Reserved 126 PINT PIE18_RESERVED_INT; // 5.6 - Reserved 127 PINT PIE19_RESERVED_INT; // 5.7 - Reserved 128 PINT PIE20_RESERVED_INT; // 5.8 - Reserved 129 PINT SPIA_RX_INT; // 6.1 - SPIA Receive Interrupt 130 PINT SPIA_TX_INT; // 6.2 - SPIA Transmit Interrupt 131 PINT SPIB_RX_INT; // 6.3 - SPIB Receive Interrupt 132 PINT SPIB_TX_INT; // 6.4 - SPIB Transmit Interrupt 133 PINT MCBSPA_RX_INT; // 6.5 - McBSPA Receive Interrupt 134 PINT MCBSPA_TX_INT; // 6.6 - McBSPA Transmit Interrupt 135 PINT MCBSPB_RX_INT; // 6.7 - McBSPB Receive Interrupt 136 PINT MCBSPB_TX_INT; // 6.8 - McBSPB Transmit Interrupt 137 PINT DMA_CH1_INT; // 7.1 - DMA Channel 1 Interrupt 138 PINT DMA_CH2_INT; // 7.2 - DMA Channel 2 Interrupt 139 PINT DMA_CH3_INT; // 7.3 - DMA Channel 3 Interrupt 140 PINT DMA_CH4_INT; // 7.4 - DMA Channel 4 Interrupt 141 PINT DMA_CH5_INT; // 7.5 - DMA Channel 5 Interrupt 142 PINT DMA_CH6_INT; // 7.6 - DMA Channel 6 Interrupt 143 PINT PIE21_RESERVED_INT; // 7.7 - Reserved 144 PINT PIE22_RESERVED_INT; // 7.8 - Reserved 145 PINT I2CA_INT; // 8.1 - I2CA Interrupt 1 146 PINT I2CA_FIFO_INT; // 8.2 - I2CA Interrupt 2 147 PINT I2CB_INT; // 8.3 - I2CB Interrupt 1 148 PINT I2CB_FIFO_INT; // 8.4 - I2CB Interrupt 2 149 PINT SCIC_RX_INT; // 8.5 - SCIC Receive Interrupt 150 PINT SCIC_TX_INT; // 8.6 - SCIC Transmit Interrupt 151 PINT SCID_RX_INT; // 8.7 - SCID Receive Interrupt 152 PINT SCID_TX_INT; // 8.8 - SCID Transmit Interrupt 153 PINT SCIA_RX_INT; // 9.1 - SCIA Receive Interrupt 154 PINT SCIA_TX_INT; // 9.2 - SCIA Transmit Interrupt 155 PINT SCIB_RX_INT; // 9.3 - SCIB Receive Interrupt 156 PINT SCIB_TX_INT; // 9.4 - SCIB Transmit Interrupt 157 PINT CANA0_INT; // 9.5 - CANA Interrupt 0 158 PINT CANA1_INT; // 9.6 - CANA Interrupt 1 159 PINT CANB0_INT; // 9.7 - CANB Interrupt 0 160 PINT CANB1_INT; // 9.8 - CANB Interrupt 1 161 PINT ADCA_EVT_INT; // 10.1 - ADCA Event Interrupt 162 PINT ADCA2_INT; // 10.2 - ADCA Interrupt 2 163 PINT ADCA3_INT; // 10.3 - ADCA Interrupt 3 164 PINT ADCA4_INT; // 10.4 - ADCA Interrupt 4 165 PINT ADCB_EVT_INT; // 10.5 - ADCB Event Interrupt 166 PINT ADCB2_INT; // 10.6 - ADCB Interrupt 2 167 PINT ADCB3_INT; // 10.7 - ADCB Interrupt 3 168 PINT ADCB4_INT; // 10.8 - ADCB Interrupt 4 169 PINT CLA1_1_INT; // 11.1 - CLA1 Interrupt 1 170 PINT CLA1_2_INT; // 11.2 - CLA1 Interrupt 2 171 PINT CLA1_3_INT; // 11.3 - CLA1 Interrupt 3 172 PINT CLA1_4_INT; // 11.4 - CLA1 Interrupt 4 173 PINT CLA1_5_INT; // 11.5 - CLA1 Interrupt 5 174 PINT CLA1_6_INT; // 11.6 - CLA1 Interrupt 6 175 PINT CLA1_7_INT; // 11.7 - CLA1 Interrupt 7 176 PINT CLA1_8_INT; // 11.8 - CLA1 Interrupt 8 177 PINT XINT3_INT; // 12.1 - XINT3 Interrupt 178 PINT XINT4_INT; // 12.2 - XINT4 Interrupt 179 PINT XINT5_INT; // 12.3 - XINT5 Interrupt 180 PINT PIE23_RESERVED_INT; // 12.4 - Reserved 181 PINT PIE24_RESERVED_INT; // 12.5 - Reserved 182 PINT VCU_INT; // 12.6 - VCU Interrupt 183 PINT FPU_OVERFLOW_INT; // 12.7 - FPU Overflow Interrupt 184 PINT FPU_UNDERFLOW_INT; // 12.8 - FPU Underflow Interrupt 185 PINT PIE25_RESERVED_INT; // 1.9 - Reserved 186 PINT PIE26_RESERVED_INT; // 1.10 - Reserved 187 PINT PIE27_RESERVED_INT; // 1.11 - Reserved 188 PINT PIE28_RESERVED_INT; // 1.12 - Reserved 189 PINT IPC0_INT; // 1.13 - IPC Interrupt 0 190 PINT IPC1_INT; // 1.14 - IPC Interrupt 1 191 PINT IPC2_INT; // 1.15 - IPC Interrupt 2 192 PINT IPC3_INT; // 1.16 - IPC Interrupt 3 193 PINT EPWM9_TZ_INT; // 2.9 - ePWM9 Trip Zone Interrupt 194 PINT EPWM10_TZ_INT; // 2.10 - ePWM10 Trip Zone Interrupt 195 PINT EPWM11_TZ_INT; // 2.11 - ePWM11 Trip Zone Interrupt 196 PINT EPWM12_TZ_INT; // 2.12 - ePWM12 Trip Zone Interrupt 197 PINT PIE29_RESERVED_INT; // 2.13 - Reserved 198 PINT PIE30_RESERVED_INT; // 2.14 - Reserved 199 PINT PIE31_RESERVED_INT; // 2.15 - Reserved 200 PINT PIE32_RESERVED_INT; // 2.16 - Reserved 201 PINT EPWM9_INT; // 3.9 - ePWM9 Interrupt 202 PINT EPWM10_INT; // 3.10 - ePWM10 Interrupt 203 PINT EPWM11_INT; // 3.11 - ePWM11 Interrupt 204 PINT EPWM12_INT; // 3.12 - ePWM12 Interrupt 205 PINT PIE33_RESERVED_INT; // 3.13 - Reserved 206 PINT PIE34_RESERVED_INT; // 3.14 - Reserved 207 PINT PIE35_RESERVED_INT; // 3.15 - Reserved 208 PINT PIE36_RESERVED_INT; // 3.16 - Reserved 209 PINT PIE37_RESERVED_INT; // 4.9 - Reserved 210 PINT PIE38_RESERVED_INT; // 4.10 - Reserved 211 PINT PIE39_RESERVED_INT; // 4.11 - Reserved 212 PINT PIE40_RESERVED_INT; // 4.12 - Reserved 213 PINT PIE41_RESERVED_INT; // 4.13 - Reserved 214 PINT PIE42_RESERVED_INT; // 4.14 - Reserved 215 PINT PIE43_RESERVED_INT; // 4.15 - Reserved 216 PINT PIE44_RESERVED_INT; // 4.16 - Reserved 217 PINT SD1_INT; // 5.9 - SD1 Interrupt 218 PINT SD2_INT; // 5.10 - SD2 Interrupt 219 PINT PIE45_RESERVED_INT; // 5.11 - Reserved 220 PINT PIE46_RESERVED_INT; // 5.12 - Reserved 221 PINT PIE47_RESERVED_INT; // 5.13 - Reserved 222 PINT PIE48_RESERVED_INT; // 5.14 - Reserved 223 PINT PIE49_RESERVED_INT; // 5.15 - Reserved 224 PINT PIE50_RESERVED_INT; // 5.16 - Reserved 225 PINT SPIC_RX_INT; // 6.9 - SPIC Receive Interrupt 226 PINT SPIC_TX_INT; // 6.10 - SPIC Transmit Interrupt 227 PINT PIE51_RESERVED_INT; // 6.11 - Reserved 228 PINT PIE52_RESERVED_INT; // 6.12 - Reserved 229 PINT PIE53_RESERVED_INT; // 6.13 - Reserved 230 PINT PIE54_RESERVED_INT; // 6.14 - Reserved 231 PINT PIE55_RESERVED_INT; // 6.15 - Reserved 232 PINT PIE56_RESERVED_INT; // 6.16 - Reserved 233 PINT PIE57_RESERVED_INT; // 7.9 - Reserved 234 PINT PIE58_RESERVED_INT; // 7.10 - Reserved 235 PINT PIE59_RESERVED_INT; // 7.11 - Reserved 236 PINT PIE60_RESERVED_INT; // 7.12 - Reserved 237 PINT PIE61_RESERVED_INT; // 7.13 - Reserved 238 PINT PIE62_RESERVED_INT; // 7.14 - Reserved 239 PINT PIE63_RESERVED_INT; // 7.15 - Reserved 240 PINT PIE64_RESERVED_INT; // 7.16 - Reserved 241 PINT PIE65_RESERVED_INT; // 8.9 - Reserved 242 PINT PIE66_RESERVED_INT; // 8.10 - Reserved 243 PINT PIE67_RESERVED_INT; // 8.11 - Reserved 244 PINT PIE68_RESERVED_INT; // 8.12 - Reserved 245 PINT PIE69_RESERVED_INT; // 8.13 - Reserved 246 PINT PIE70_RESERVED_INT; // 8.14 - Reserved 247 #ifdef CPU1 248 PINT UPPA_INT; // 8.15 - uPPA Interrupt 249 PINT PIE72_RESERVED_INT; // 8.16 - Reserved 250 #elif defined(CPU2) 251 PINT PIE71_RESERVED_INT; // 8.15 - Reserved 252 PINT PIE72_RESERVED_INT; // 8.16 - Reserved 253 #endif 254 PINT PIE73_RESERVED_INT; // 9.9 - Reserved 255 PINT PIE74_RESERVED_INT; // 9.10 - Reserved 256 PINT PIE75_RESERVED_INT; // 9.11 - Reserved 257 PINT PIE76_RESERVED_INT; // 9.12 - Reserved 258 PINT PIE77_RESERVED_INT; // 9.13 - Reserved 259 PINT PIE78_RESERVED_INT; // 9.14 - Reserved 260 #ifdef CPU1 261 PINT USBA_INT; // 9.15 - USBA Interrupt 262 #elif defined(CPU2) 263 PINT PIE79_RESERVED_INT; // 9.15 - Reserved 264 #endif 265 PINT PIE80_RESERVED_INT; // 9.16 - Reserved 266 PINT ADCC_EVT_INT; // 10.9 - ADCC Event Interrupt 267 PINT ADCC2_INT; // 10.10 - ADCC Interrupt 2 268 PINT ADCC3_INT; // 10.11 - ADCC Interrupt 3 269 PINT ADCC4_INT; // 10.12 - ADCC Interrupt 4 270 PINT ADCD_EVT_INT; // 10.13 - ADCD Event Interrupt 271 PINT ADCD2_INT; // 10.14 - ADCD Interrupt 2 272 PINT ADCD3_INT; // 10.15 - ADCD Interrupt 3 273 PINT ADCD4_INT; // 10.16 - ADCD Interrupt 4 274 PINT PIE81_RESERVED_INT; // 11.9 - Reserved 275 PINT PIE82_RESERVED_INT; // 11.10 - Reserved 276 PINT PIE83_RESERVED_INT; // 11.11 - Reserved 277 PINT PIE84_RESERVED_INT; // 11.12 - Reserved 278 PINT PIE85_RESERVED_INT; // 11.13 - Reserved 279 PINT PIE86_RESERVED_INT; // 11.14 - Reserved 280 PINT PIE87_RESERVED_INT; // 11.15 - Reserved 281 PINT PIE88_RESERVED_INT; // 11.16 - Reserved 282 PINT EMIF_ERROR_INT; // 12.9 - EMIF Error Interrupt 283 PINT RAM_CORRECTABLE_ERROR_INT; // 12.10 - RAM Correctable Error Interrupt 284 PINT FLASH_CORRECTABLE_ERROR_INT; // 12.11 - Flash Correctable Error Interrupt 285 PINT RAM_ACCESS_VIOLATION_INT; // 12.12 - RAM Access Violation Interrupt 286 PINT SYS_PLL_SLIP_INT; // 12.13 - System PLL Slip Interrupt 287 PINT AUX_PLL_SLIP_INT; // 12.14 - Auxiliary PLL Slip Interrupt 288 PINT CLA_OVERFLOW_INT; // 12.15 - CLA Overflow Interrupt 289 PINT CLA_UNDERFLOW_INT; // 12.16 - CLA Underflow Interrupt 290 }; 291 292 //--------------------------------------------------------------------------- 293 // PieVect External References & Function Declarations: 294 // 295 296 extern volatile struct PIE_VECT_TABLE PieVectTable; 297 298 #ifdef __cplusplus 299 } 300 #endif /* extern "C" */ 301 302 303 #endif // end of F2837xD_PIEVECT_H definition 304 //=========================================================================== 305 // End of file. 306 //=========================================================================== 307