1 /* 2 * Copyright (c) 2006-2021, JuiceVm Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2021/04/22 Juice the first version 9 */ 10 11 12 #ifndef __RV_CONFIG_H__ 13 #define __RV_CONFIG_H__ 14 15 #define RV64I_SUPPORT_ENBALE 16 #define RV64_MMU_ENBALE 1 17 18 #define RV_ENDLESS_LOOP_CHECK_ENBALE 1 19 #if defined(RV_ENDLESS_LOOP_CHECK_ENBALE) && RV_ENDLESS_LOOP_CHECK_ENBALE == 1 20 #define RV_ENDLESS_LOOP_CHECK_BUF_SIZE (30) 21 #define RV_ENDLESS_LOOP_CHECK_EXIT_CNT (3) 22 #define RV_ENDLESS_LOOP_CHECK_MD5_HASH 1 23 #endif 24 25 // #define RISCV_ANGEL_ONLY 26 #define Machine_Mode_SUPPORT 27 #define Supervisor_Mode_SUPPORT 28 // #define User_Mode_SUPPORT 29 // #define Hypervisor_Mode_SUPPORT 30 31 #define ATOMIC_Module_SUPPORT 32 33 #define RV_CPU_CSR_DEF_Vendor_ID 0 34 #define RV_CPU_CSR_DEF_March_ID 0 35 #define RV_CPU_CSR_DEF_Mimp_ID 0 36 #define RV_CPU_CSR_DEF_Mhart_ID 0 37 38 #define JUICE_VM_LOG_MAX_NUM (600) 39 40 #define JUICE_VM_INC_CHANGELOG 0 41 42 #define RAM_SIZE_KB (1024) 43 #define RAM_SIZE_MB (1024*RAM_SIZE_KB) 44 45 #define RV_CPU_SIM_RAM_START_ADDR (0x80000000) 46 #define RV_CPU_SIM_RAM_SIZE (300 * RAM_SIZE_MB) 47 48 #define RV_CPU_SIM_CAUSETABLE_MAX_NUM 100//MXLEN-1 bit 49 50 #define RV_CPU_SIM_PERDEV_NUM 50 51 #define rv_peripheral_device_add_check_dev 1 52 53 // | MXLEN-1 MXLEN-2 | MXLEN-3 26| 25 0 | 54 // | MXL[1:0](WARL) | WLRL | Extensions[25:0] (WARL) | 55 // | 2 | MXLEN-28 | 26 | 56 // Figure 3.1: Machine ISA register (misa). 57 58 59 60 // Bit | Character | Description 61 // 0 | A | Atomic extension 62 // 1 | B | Tentatively reserved for Bit-Manipulation extension 63 // 2 | C | Compressed extension 64 // 3 | D | Double-precision floating-point extension 65 // 4 | E | RV32E base ISA 66 // 5 | F | Single-precision floating-point extension 67 // 6 | G | Reserved 68 // 7 | H | Hypervisor extension 69 // 8 | I | RV32I/64I/128I base ISA 70 // 9 | J | Tentatively reserved for Dynamically Translated Languages extension 71 // 10 | K | Reserved 72 // 11 | L | Tentatively reserved for Decimal Floating-Point extension 73 // 12 | M | Integer Multiply/Divide extension 74 // 13 | N | User-level interrupts supported 75 // 14 | O | Reserved 76 // 15 | P | Tentatively reserved for Packed-SIMD extension 77 // 16 | Q | Quad-precision floating-point extension 78 // 17 | R | Reserved 79 // 18 | S | Supervisor mode implemented 80 // 19 | T | Tentatively reserved for Transactional Memory extension 81 // 20 | U | User mode implemented 82 // 21 | V | Tentatively reserved for Vector extension 83 // 22 | W | Reserved 84 // 23 | X | Non-standard extensions present 85 // 24 | Y | Reserved 86 // 25 | Z | Reserved 87 #define RV_MISA_ATOMIC_EXT (1<<0) 88 #define RV_MISA_INTEGER_EXT (1<<8) 89 #define RV_MISA_UMODE_INT_EXT (1<<13) 90 #define RV_MISA_SMODE_IMP_EXT (1<<18) 91 #define RV_MISA_UMODE_IMP_EXT (1<<20) 92 93 // | MXL | XLEN | 94 // | 1 | 32 | 95 // | 2 | 64 | 96 // | 3 | 128 | 97 #define RV_MISA_XLEN_32 (1<<(32-2)) 98 #define RV_MISA_XLEN_64 (uint64_t)((uint64_t)(2)<<(64-2)) 99 // #define RV_MISA_XLEN_128 ((uint128_t)(3)<<(128-2)) 100 101 102 103 #define RV_MISA_CSR_REGISTER ((uint64_t)(RV_MISA_XLEN_64 | RV_MISA_ATOMIC_EXT | RV_MISA_INTEGER_EXT /*| RV_MISA_UMODE_INT_EXT*/ | RV_MISA_SMODE_IMP_EXT /*| RV_MISA_UMODE_IMP_EXT*/)) 104 105 106 #endif // __RV_CONFIG_H__ 107