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27 /**
28 * @file xil_mmu.h
29 *
30 * @addtogroup r5_mpu_apis Cortex R5 Processor MPU specific APIs
31 *
32 * MPU functions provides access to MPU operations such as enable MPU, disable
33 * MPU and set attribute for section of memory.
34 * Boot code invokes Init_MPU function to configure the MPU. A total of 10 MPU
35 * regions are allocated with another 6 being free for users. Overview of the
36 * memory attributes for different MPU regions is as given below,
37 *
38 *|                       | Memory Range            | Attributes of MPURegion     |
39 *|-----------------------|-------------------------|-----------------------------|
40 *| DDR                   | 0x00000000 - 0x7FFFFFFF | Normal write-back Cacheable |
41 *| PL                    | 0x80000000 - 0xBFFFFFFF | Strongly Ordered            |
42 *| QSPI                  | 0xC0000000 - 0xDFFFFFFF | Device Memory               |
43 *| PCIe                  | 0xE0000000 - 0xEFFFFFFF | Device Memory               |
44 *| STM_CORESIGHT         | 0xF8000000 - 0xF8FFFFFF | Device Memory               |
45 *| RPU_R5_GIC            | 0xF9000000 - 0xF90FFFFF | Device memory               |
46 *| FPS                   | 0xFD000000 - 0xFDFFFFFF | Device Memory               |
47 *| LPS                   | 0xFE000000 - 0xFFFFFFFF | Device Memory               |
48 *| OCM                   | 0xFFFC0000 - 0xFFFFFFFF | Normal write-back Cacheable |
49 *
50 *
51 * @note
52 * For a system where DDR is less than 2GB, region after DDR and before PL is
53 * marked as undefined in translation table. Memory range 0xFE000000-0xFEFFFFFF is
54 * allocated for upper LPS slaves, where as memory region 0xFF000000-0xFFFFFFFF is
55 * allocated for lower LPS slaves.
56 *
57 * @{
58 * <pre>
59 * MODIFICATION HISTORY:
60 *
61 * Ver   Who  Date     Changes
62 * ----- ---- -------- ---------------------------------------------------
63 * 5.00  pkp  02/10/14 Initial version
64 * 6.4   asa  08/16/17 Added many APIs for MPU access to make MPU usage
65 *                       user-friendly. The APIs added are: Xil_UpdateMPUConfig,
66 *                       Xil_GetMPUConfig, Xil_GetNumOfFreeRegions,
67 *                       Xil_GetNextMPURegion, Xil_DisableMPURegionByRegNum,
68 *                       Xil_GetMPUFreeRegMask, Xil_SetMPURegionByRegNum, and
69 *                       Xil_InitializeExistingMPURegConfig.
70 *                       Added a new array of structure of type XMpuConfig to
71 *                       represent the MPU configuration table.
72 * </pre>
73 *
74 
75 *
76 *
77 ******************************************************************************/
78 
79 #ifndef XIL_MPU_H
80 #define XIL_MPU_H
81 
82 #ifdef __cplusplus
83 extern "C" {
84 #endif /* __cplusplus */
85 #include "xil_types.h"
86 /***************************** Include Files *********************************/
87 
88 /***************** Macros (Inline Functions) Definitions *********************/
89 #define MPU_REG_DISABLED        0U
90 #define MPU_REG_ENABLED            1U
91 #define MAX_POSSIBLE_MPU_REGS    16U
92 /**************************** Type Definitions *******************************/
93 struct XMpuConfig{
94     u32 RegionStatus; /* Enabled or disabled */
95     INTPTR BaseAddress;/* MPU region base address */
96     u64 Size; /* MPU region size address */
97     u32 Attribute; /* MPU region size attribute */
98 };
99 
100 typedef struct XMpuConfig XMpu_Config[MAX_POSSIBLE_MPU_REGS];
101 
102 extern XMpu_Config Mpu_Config;
103 /************************** Constant Definitions *****************************/
104 
105 /************************** Variable Definitions *****************************/
106 
107 /************************** Function Prototypes ******************************/
108 
109 void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
110 void Xil_EnableMPU(void);
111 void Xil_DisableMPU(void);
112 u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib);
113 u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib);
114 void Xil_GetMPUConfig (XMpu_Config mpuconfig);
115 u32 Xil_GetNumOfFreeRegions (void);
116 u32 Xil_GetNextMPURegion(void);
117 u32 Xil_DisableMPURegionByRegNum (u32 reg_num);
118 u16 Xil_GetMPUFreeRegMask (void);
119 u32 Xil_SetMPURegionByRegNum (u32 reg_num, INTPTR addr, u64 size, u32 attrib);
120 void* Xil_MemMap(UINTPTR Physaddr, size_t size, u32 flags);
121 
122 #ifdef __cplusplus
123 }
124 #endif /* __cplusplus */
125 
126 #endif /* XIL_MPU_H */
127 /**
128 * @} End of "addtogroup r5_mpu_apis".
129 */
130