1 /** 2 * @file max32660.h 3 * @brief Device-specific perhiperal header file 4 */ 5 6 /******************************************************************************* 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included 17 * in all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 * Except as contained in this notice, the name of Maxim Integrated 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated 29 * Products, Inc. Branding Policy. 30 * 31 * The mere transfer of this software does not imply any licenses 32 * of trade secrets, proprietary technology, copyrights, patents, 33 * trademarks, maskwork rights, or any other form of intellectual 34 * property whatsoever. Maxim Integrated Products, Inc. retains all 35 * ownership rights. 36 * 37 * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ 38 * $Revision: 40072 $ 39 * 40 ******************************************************************************/ 41 42 #ifndef _MAX32660_REGS_H_ 43 #define _MAX32660_REGS_H_ 44 45 #ifndef TARGET_NUM 46 #define TARGET_NUM 32660 47 #endif 48 49 #include <stdint.h> 50 51 #ifndef FALSE 52 #define FALSE (0) 53 #endif 54 55 #ifndef TRUE 56 #define TRUE (1) 57 #endif 58 59 #if !defined (__GNUC__) 60 #define CMSIS_VECTAB_VIRTUAL 61 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h" 62 #endif /* !__GNUC__ */ 63 64 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ 65 #if defined ( __GNUC__ ) /* GCC */ 66 #define __weak __attribute__((weak)) 67 68 #elif defined ( __CC_ARM) /* Keil */ 69 70 #define inline __inline 71 #pragma anon_unions 72 73 #endif 74 75 typedef enum { 76 NonMaskableInt_IRQn = -14, 77 HardFault_IRQn = -13, 78 MemoryManagement_IRQn = -12, 79 BusFault_IRQn = -11, 80 UsageFault_IRQn = -10, 81 SVCall_IRQn = -5, 82 DebugMonitor_IRQn = -4, 83 PendSV_IRQn = -2, 84 SysTick_IRQn = -1, 85 86 /* Device-specific interrupt sources (external to ARM core) */ 87 /* table entry number */ 88 /* |||| */ 89 /* |||| table offset address */ 90 /* vvvv vvvvvv */ 91 92 PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */ 93 WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */ 94 RSV00_IRQn, /* 0x12 0x0048 18: RSV00 */ 95 RTC_IRQn, /* 0x13 0x004C 19: RTC */ 96 RSV1_IRQn, /* 0x14 0x0050 20: RSV1 */ 97 TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ 98 TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ 99 TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ 100 RSV02_IRQn, /* 0x18 0x0060 24: RSV02 */ 101 RSV03_IRQn, /* 0x19 0x0064 25: RSV03 */ 102 RSV04_IRQn, /* 0x1A 0x0068 26: RSV04 */ 103 RSV05_IRQn, /* 0x1B 0x006C 27: RSV05 */ 104 RSV06_IRQn, /* 0x1C 0x0070 28: RSV06 */ 105 I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */ 106 UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */ 107 UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */ 108 SPI17Y_IRQn, /* 0x20 0x0080 32: SPI17Y */ 109 SPIMSS_IRQn, /* 0x21 0x0084 33: SPIMSS */ 110 RSV07_IRQn, /* 0x22 0x0088 34: RSV07 */ 111 RSV08_IRQn, /* 0x23 0x008C 35: RSV08 */ 112 RSV09_IRQn, /* 0x24 0x0090 36: RSV09 */ 113 RSV10_IRQn, /* 0x25 0x0094 37: RSV10 */ 114 RSV11_IRQn, /* 0x26 0x0098 38: RSV11 */ 115 FLC_IRQn, /* 0x27 0x009C 39: FLC */ 116 GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ 117 RSV12_IRQn, /* 0x29 0x00A4 41: RSV12 */ 118 RSV13_IRQn, /* 0x2A 0x00A8 42: RSV13 */ 119 RSV14_IRQn, /* 0x2B 0x00AC 43: RSV14 */ 120 DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ 121 DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ 122 DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ 123 DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ 124 RSV15_IRQn, /* 0x30 0x00C0 48: RSV15 */ 125 RSV16_IRQn, /* 0x31 0x00C4 49: RSV16 */ 126 RSV17_IRQn, /* 0x32 0x00C8 50: RSV17 */ 127 RSV18_IRQn, /* 0x33 0x00CC 51: RSV18 */ 128 I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */ 129 RSV19_IRQn, /* 0x35 0x00D4 53: RSV19 */ 130 RSV20_IRQn, /* 0x36 0x00D8 54: RSV20 */ 131 RSV21_IRQn, /* 0x37 0x00DC 55: RSV21 */ 132 RSV22_IRQn, /* 0x38 0x00E0 56: RSV22 */ 133 RSV23_IRQn, /* 0x39 0x00E4 57: RSV23 */ 134 RSV24_IRQn, /* 0x3A 0x00E8 58: RSV24 */ 135 RSV25_IRQn, /* 0x3B 0x00EC 59: RSV25 */ 136 RSV26_IRQn, /* 0x3C 0x00F0 60: RSV26 */ 137 RSV27_IRQn, /* 0x3D 0x00F4 61: RSV27 */ 138 RSV28_IRQn, /* 0x3E 0x00F8 62: RSV28 */ 139 RSV29_IRQn, /* 0x3F 0x00FC 63: RSV29 */ 140 RSV30_IRQn, /* 0x40 0x0100 64: RSV30 */ 141 RSV31_IRQn, /* 0x41 0x0104 65: RSV31 */ 142 RSV32_IRQn, /* 0x42 0x0108 66: RSV32 */ 143 RSV33_IRQn, /* 0x43 0x010C 67: RSV33 */ 144 RSV34_IRQn, /* 0x44 0x0110 68: RSV34 */ 145 RSV35_IRQn, /* 0x45 0x0114 69: RSV35 */ 146 GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */ 147 MXC_IRQ_EXT_COUNT, 148 } IRQn_Type; 149 150 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) 151 152 153 /* ================================================================================ */ 154 /* ================ Processor and Core Peripheral Section ================ */ 155 /* ================================================================================ */ 156 157 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ 158 #define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ 159 #define __MPU_PRESENT 1 /*!< MPU present or not */ 160 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 161 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 162 #define __FPU_PRESENT 1 /*!< FPU present or not */ 163 164 #include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */ 165 #include "system_max32660.h" /*!< System Header */ 166 167 168 /* ================================================================================ */ 169 /* ================== Device Specific Memory Section ================== */ 170 /* ================================================================================ */ 171 172 #define MXC_FLASH_MEM_BASE 0x00000000UL 173 #define MXC_FLASH_PAGE_SIZE 0x00002000UL 174 #define MXC_FLASH_MEM_SIZE 0x00040000UL 175 #define MXC_INFO_MEM_BASE 0x00040000UL 176 #define MXC_INFO_MEM_SIZE 0x00001000UL 177 #define MXC_SRAM_MEM_BASE 0x20000000UL 178 #define MXC_SRAM_MEM_SIZE 0x00018000UL 179 180 /* ================================================================================ */ 181 /* ================ Device Specific Peripheral Section ================ */ 182 /* ================================================================================ */ 183 184 /* 185 Base addresses and configuration settings for all MAX32660 peripheral modules. 186 */ 187 188 /******************************************************************************/ 189 /* Global control */ 190 #define MXC_BASE_GCR ((uint32_t)0x40000000UL) 191 #define MXC_GCR ((mxc_gcr_regs_t*)MXC_BASE_GCR) 192 193 /******************************************************************************/ 194 /* Non-battery backed SI Registers */ 195 #define MXC_BASE_SIR ((uint32_t)0x40000400UL) 196 #define MXC_SIR ((mxc_sir_regs_t*)MXC_BASE_SIR) 197 198 /******************************************************************************/ 199 /* Watchdog */ 200 #define MXC_BASE_WDT0 ((uint32_t)0x40003000UL) 201 #define MXC_WDT0 ((mxc_wdt_regs_t*)MXC_BASE_WDT0) 202 203 /******************************************************************************/ 204 /* Real Time Clock */ 205 #define MXC_BASE_RTC ((uint32_t)0x40006000UL) 206 #define MXC_RTC ((mxc_rtc_regs_t*)MXC_BASE_RTC) 207 208 /******************************************************************************/ 209 /* Power Sequencer */ 210 #define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL) 211 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ) 212 213 214 /******************************************************************************/ 215 /* GPIO */ 216 #define MXC_CFG_GPIO_INSTANCES (1) 217 #define MXC_CFG_GPIO_PINS_PORT (14) 218 219 #define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL) 220 #define MXC_GPIO0 ((mxc_gpio_regs_t*)MXC_BASE_GPIO0) 221 222 #define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 :-1) 223 224 #define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0) 225 226 #define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : 0) 227 228 /******************************************************************************/ 229 /* Timer */ 230 #define MXC_CFG_TMR_INSTANCES (3) 231 232 #define MXC_BASE_TMR0 ((uint32_t)0x40010000UL) 233 #define MXC_TMR0 ((mxc_tmr_regs_t*)MXC_BASE_TMR0) 234 #define MXC_BASE_TMR1 ((uint32_t)0x40011000UL) 235 #define MXC_TMR1 ((mxc_tmr_regs_t*)MXC_BASE_TMR1) 236 #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) 237 #define MXC_TMR2 ((mxc_tmr_regs_t*)MXC_BASE_TMR2) 238 239 #define MXC_TMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ 240 (i) == 1 ? TMR1_IRQn : \ 241 (i) == 2 ? TMR2_IRQn : 0) 242 243 #define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \ 244 (i) == 1 ? MXC_BASE_TMR1 : \ 245 (i) == 2 ? MXC_BASE_TMR2 : 0) 246 247 #define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \ 248 (i) == 1 ? MXC_TMR1 : \ 249 (i) == 2 ? MXC_TMR2 : 0) 250 251 #define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \ 252 (p) == MXC_TMR1 ? 1 : \ 253 (p) == MXC_TMR2 ? 2 : -1) 254 255 /******************************************************************************/ 256 /* SPIMSS */ 257 258 #define MXC_SPIMSS_INSTANCES (1) 259 #define MXC_SPIMSS_FIFO_DEPTH (8) 260 261 #define MXC_BASE_SPIMSS ((uint32_t)0x40019000UL) 262 #define MXC_SPIMSS ((mxc_spimss_regs_t*)MXC_BASE_SPIMSS) 263 264 #define MXC_SPIMSS_GET_IDX(p) ((p) == MXC_SPIMSS ? 0 : -1) 265 #define MXC_SPIMSS_GET_SPI(i) ((i) == 0 ? MXC_SPIMSS : 0) 266 267 /******************************************************************************/ 268 /* I2C */ 269 #define MXC_I2C_INSTANCES (2) 270 #define MXC_I2C_FIFO_DEPTH (8) 271 272 #define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL) 273 #define MXC_I2C0 ((mxc_i2c_regs_t*)MXC_BASE_I2C0) 274 #define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL) 275 #define MXC_I2C1 ((mxc_i2c_regs_t*)MXC_BASE_I2C1) 276 277 #define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : \ 278 (i) == 1 ? I2C1_IRQn : 0) 279 280 #define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : \ 281 (i) == 1 ? MXC_BASE_I2C1 : 0) 282 283 #define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : \ 284 (i) == 1 ? MXC_I2C1 : 0) 285 286 #define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : \ 287 (p) == MXC_I2C1 ? 1 : -1) 288 289 /******************************************************************************/ 290 /* DMA */ 291 #define MXC_DMA_CHANNELS (4) 292 293 #define MXC_BASE_DMA ((uint32_t)0x40028000UL) 294 #define MXC_DMA ((mxc_dma_regs_t*)MXC_BASE_DMA) 295 296 /******************************************************************************/ 297 /* FLC */ 298 #define MXC_BASE_FLC ((uint32_t)0x40029000UL) 299 #define MXC_FLC ((mxc_flc_regs_t*)MXC_BASE_FLC) 300 301 /******************************************************************************/ 302 /* Instruction Cache */ 303 #define MXC_BASE_ICC ((uint32_t)0x4002A000UL) 304 #define MXC_ICC ((mxc_icc_regs_t*)MXC_BASE_ICC) 305 306 /******************************************************************************/ 307 /* UART / Serial Port Interface */ 308 309 #define MXC_UART_INSTANCES (2) 310 #define MXC_UART_FIFO_DEPTH (8) 311 312 #define MXC_BASE_UART0 ((uint32_t)0x40042000UL) 313 #define MXC_UART0 ((mxc_uart_regs_t*)MXC_BASE_UART0) 314 #define MXC_BASE_UART1 ((uint32_t)0x40043000UL) 315 #define MXC_UART1 ((mxc_uart_regs_t*)MXC_BASE_UART1) 316 317 #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \ 318 (i) == 1 ? UART1_IRQn : 0) 319 320 #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \ 321 (i) == 1 ? MXC_BASE_UART1 : 0) 322 323 #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \ 324 (i) == 1 ? MXC_UART1 : 0) 325 326 #define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \ 327 (p) == MXC_UART1 ? 1 : -1) 328 329 /******************************************************************************/ 330 /* SPI */ 331 332 333 #define MXC_SPI17Y_INSTANCES (4) 334 #define MXC_SPI17Y_SS_INSTANCES (1) 335 #define MXC_SPI17Y_FIFO_DEPTH (32) 336 337 #define MXC_BASE_SPI17Y ((uint32_t)0x40046000UL) 338 #define MXC_SPI17Y ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y) 339 340 #define MXC_SPI17Y_GET_IDX(p) ((p) == MXC_SPI17Y ? 0 : -1) 341 342 #define MXC_SPI17Y_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI17Y : 0) 343 344 #define MXC_SPI17Y_GET_SPI17Y(i) ((i) == 0 ? MXC_SPI17Y : 0) 345 346 /******************************************************************************/ 347 /* Bit Shifting */ 348 349 #define MXC_F_BIT_0 (1 << 0) 350 #define MXC_F_BIT_1 (1 << 1) 351 #define MXC_F_BIT_2 (1 << 2) 352 #define MXC_F_BIT_3 (1 << 3) 353 #define MXC_F_BIT_4 (1 << 4) 354 #define MXC_F_BIT_5 (1 << 5) 355 #define MXC_F_BIT_6 (1 << 6) 356 #define MXC_F_BIT_7 (1 << 7) 357 #define MXC_F_BIT_8 (1 << 8) 358 #define MXC_F_BIT_9 (1 << 9) 359 #define MXC_F_BIT_10 (1 << 10) 360 #define MXC_F_BIT_11 (1 << 11) 361 #define MXC_F_BIT_12 (1 << 12) 362 #define MXC_F_BIT_13 (1 << 13) 363 #define MXC_F_BIT_14 (1 << 14) 364 #define MXC_F_BIT_15 (1 << 15) 365 #define MXC_F_BIT_16 (1 << 16) 366 #define MXC_F_BIT_17 (1 << 17) 367 #define MXC_F_BIT_18 (1 << 18) 368 #define MXC_F_BIT_19 (1 << 19) 369 #define MXC_F_BIT_20 (1 << 20) 370 #define MXC_F_BIT_21 (1 << 21) 371 #define MXC_F_BIT_22 (1 << 22) 372 #define MXC_F_BIT_23 (1 << 23) 373 #define MXC_F_BIT_24 (1 << 24) 374 #define MXC_F_BIT_25 (1 << 25) 375 #define MXC_F_BIT_26 (1 << 26) 376 #define MXC_F_BIT_27 (1 << 27) 377 #define MXC_F_BIT_28 (1 << 28) 378 #define MXC_F_BIT_29 (1 << 29) 379 #define MXC_F_BIT_30 (1 << 30) 380 #define MXC_F_BIT_31 (1 << 31) 381 382 /******************************************************************************/ 383 /* Bit Banding */ 384 385 #define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \ 386 (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) 387 388 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) 389 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) 390 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) 391 392 #define MXC_SETFIELD(reg, mask, value) (reg = (reg & ~mask) | (value & mask)) 393 394 /******************************************************************************/ 395 /* SCB CPACR */ 396 397 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ 398 #define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ 399 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ 400 #define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ 401 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ 402 403 #endif /* _MAX32660_REGS_H_ */ 404