1 //########################################################################### 2 // 3 // FILE: F2837xD_sci.h 4 // 5 // TITLE: SCI Register Definitions. 6 // 7 //########################################################################### 8 // $TI Release: F2837xD Support Library v3.05.00.00 $ 9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ 10 // $Copyright: 11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ 12 // 13 // Redistribution and use in source and binary forms, with or without 14 // modification, are permitted provided that the following conditions 15 // are met: 16 // 17 // Redistributions of source code must retain the above copyright 18 // notice, this list of conditions and the following disclaimer. 19 // 20 // Redistributions in binary form must reproduce the above copyright 21 // notice, this list of conditions and the following disclaimer in the 22 // documentation and/or other materials provided with the 23 // distribution. 24 // 25 // Neither the name of Texas Instruments Incorporated nor the names of 26 // its contributors may be used to endorse or promote products derived 27 // from this software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 // $ 41 //########################################################################### 42 43 #ifndef __F2837xD_SCI_H__ 44 #define __F2837xD_SCI_H__ 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 51 //--------------------------------------------------------------------------- 52 // SCI Individual Register Bit Definitions: 53 54 struct SCICCR_BITS { // bits description 55 Uint16 SCICHAR:3; // 2:0 Character length control 56 Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control 57 Uint16 LOOPBKENA:1; // 4 Loop Back enable 58 Uint16 PARITYENA:1; // 5 Parity enable 59 Uint16 PARITY:1; // 6 Even or Odd Parity 60 Uint16 STOPBITS:1; // 7 Number of Stop Bits 61 Uint16 rsvd1:8; // 15:8 Reserved 62 }; 63 64 union SCICCR_REG { 65 Uint16 all; 66 struct SCICCR_BITS bit; 67 }; 68 69 struct SCICTL1_BITS { // bits description 70 Uint16 RXENA:1; // 0 SCI receiver enable 71 Uint16 TXENA:1; // 1 SCI transmitter enable 72 Uint16 SLEEP:1; // 2 SCI sleep 73 Uint16 TXWAKE:1; // 3 Transmitter wakeup method 74 Uint16 rsvd1:1; // 4 Reserved 75 Uint16 SWRESET:1; // 5 Software reset 76 Uint16 RXERRINTENA:1; // 6 Recieve __interrupt enable 77 Uint16 rsvd2:9; // 15:7 Reserved 78 }; 79 80 union SCICTL1_REG { 81 Uint16 all; 82 struct SCICTL1_BITS bit; 83 }; 84 85 struct SCIHBAUD_BITS { // bits description 86 Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCIHBAUD 87 Uint16 rsvd1:8; // 15:8 Reserved 88 }; 89 90 union SCIHBAUD_REG { 91 Uint16 all; 92 struct SCIHBAUD_BITS bit; 93 }; 94 95 struct SCILBAUD_BITS { // bits description 96 Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCILBAUD 97 Uint16 rsvd1:8; // 15:8 Reserved 98 }; 99 100 union SCILBAUD_REG { 101 Uint16 all; 102 struct SCILBAUD_BITS bit; 103 }; 104 105 struct SCICTL2_BITS { // bits description 106 Uint16 TXINTENA:1; // 0 Transmit __interrupt enable 107 Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable 108 Uint16 rsvd1:4; // 5:2 Reserved 109 Uint16 TXEMPTY:1; // 6 Transmitter empty flag 110 Uint16 TXRDY:1; // 7 Transmitter ready flag 111 Uint16 rsvd2:8; // 15:8 Reserved 112 }; 113 114 union SCICTL2_REG { 115 Uint16 all; 116 struct SCICTL2_BITS bit; 117 }; 118 119 struct SCIRXST_BITS { // bits description 120 Uint16 rsvd1:1; // 0 Reserved 121 Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag 122 Uint16 PE:1; // 2 Parity error flag 123 Uint16 OE:1; // 3 Overrun error flag 124 Uint16 FE:1; // 4 Framing error flag 125 Uint16 BRKDT:1; // 5 Break-detect flag 126 Uint16 RXRDY:1; // 6 Receiver ready flag 127 Uint16 RXERROR:1; // 7 Receiver error flag 128 Uint16 rsvd2:8; // 15:8 Reserved 129 }; 130 131 union SCIRXST_REG { 132 Uint16 all; 133 struct SCIRXST_BITS bit; 134 }; 135 136 struct SCIRXEMU_BITS { // bits description 137 Uint16 ERXDT:8; // 7:0 Receive emulation buffer data 138 Uint16 rsvd1:8; // 15:8 Reserved 139 }; 140 141 union SCIRXEMU_REG { 142 Uint16 all; 143 struct SCIRXEMU_BITS bit; 144 }; 145 146 struct SCIRXBUF_BITS { // bits description 147 Uint16 SAR:8; // 7:0 Receive Character bits 148 Uint16 rsvd1:6; // 13:8 Reserved 149 Uint16 SCIFFPE:1; // 14 Receiver error flag 150 Uint16 SCIFFFE:1; // 15 Receiver error flag 151 }; 152 153 union SCIRXBUF_REG { 154 Uint16 all; 155 struct SCIRXBUF_BITS bit; 156 }; 157 158 struct SCITXBUF_BITS { // bits description 159 Uint16 TXDT:8; // 7:0 Transmit data buffer 160 Uint16 rsvd1:8; // 15:8 Reserved 161 }; 162 163 union SCITXBUF_REG { 164 Uint16 all; 165 struct SCITXBUF_BITS bit; 166 }; 167 168 struct SCIFFTX_BITS { // bits description 169 Uint16 TXFFIL:5; // 4:0 Interrupt level 170 Uint16 TXFFIENA:1; // 5 Interrupt enable 171 Uint16 TXFFINTCLR:1; // 6 Clear INT flag 172 Uint16 TXFFINT:1; // 7 INT flag 173 Uint16 TXFFST:5; // 12:8 FIFO status 174 Uint16 TXFIFORESET:1; // 13 FIFO reset 175 Uint16 SCIFFENA:1; // 14 Enhancement enable 176 Uint16 SCIRST:1; // 15 SCI reset rx/tx channels 177 }; 178 179 union SCIFFTX_REG { 180 Uint16 all; 181 struct SCIFFTX_BITS bit; 182 }; 183 184 struct SCIFFRX_BITS { // bits description 185 Uint16 RXFFIL:5; // 4:0 Interrupt level 186 Uint16 RXFFIENA:1; // 5 Interrupt enable 187 Uint16 RXFFINTCLR:1; // 6 Clear INT flag 188 Uint16 RXFFINT:1; // 7 INT flag 189 Uint16 RXFFST:5; // 12:8 FIFO status 190 Uint16 RXFIFORESET:1; // 13 FIFO reset 191 Uint16 RXFFOVRCLR:1; // 14 Clear overflow 192 Uint16 RXFFOVF:1; // 15 FIFO overflow 193 }; 194 195 union SCIFFRX_REG { 196 Uint16 all; 197 struct SCIFFRX_BITS bit; 198 }; 199 200 struct SCIFFCT_BITS { // bits description 201 Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay 202 Uint16 rsvd1:5; // 12:8 Reserved 203 Uint16 CDC:1; // 13 Auto baud mode enable 204 Uint16 ABDCLR:1; // 14 Auto baud clear 205 Uint16 ABD:1; // 15 Auto baud detect 206 }; 207 208 union SCIFFCT_REG { 209 Uint16 all; 210 struct SCIFFCT_BITS bit; 211 }; 212 213 struct SCIPRI_BITS { // bits description 214 Uint16 rsvd1:3; // 2:0 Reserved 215 Uint16 FREESOFT:2; // 4:3 Emulation modes 216 Uint16 rsvd2:3; // 7:5 Reserved 217 Uint16 rsvd3:8; // 15:8 Reserved 218 }; 219 220 union SCIPRI_REG { 221 Uint16 all; 222 struct SCIPRI_BITS bit; 223 }; 224 225 struct SCI_REGS { 226 union SCICCR_REG SCICCR; // Communications control register 227 union SCICTL1_REG SCICTL1; // Control register 1 228 union SCIHBAUD_REG SCIHBAUD; // Baud rate (high) register 229 union SCILBAUD_REG SCILBAUD; // Baud rate (low) register 230 union SCICTL2_REG SCICTL2; // Control register 2 231 union SCIRXST_REG SCIRXST; // Recieve status register 232 union SCIRXEMU_REG SCIRXEMU; // Recieve emulation buffer register 233 union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer 234 Uint16 rsvd1; // Reserved 235 union SCITXBUF_REG SCITXBUF; // Transmit data buffer 236 union SCIFFTX_REG SCIFFTX; // FIFO transmit register 237 union SCIFFRX_REG SCIFFRX; // FIFO recieve register 238 union SCIFFCT_REG SCIFFCT; // FIFO control register 239 Uint16 rsvd2[2]; // Reserved 240 union SCIPRI_REG SCIPRI; // SCI Priority control 241 }; 242 243 //--------------------------------------------------------------------------- 244 // SCI External References & Function Declarations: 245 // 246 #ifdef CPU1 247 extern volatile struct SCI_REGS SciaRegs; 248 extern volatile struct SCI_REGS ScibRegs; 249 extern volatile struct SCI_REGS ScicRegs; 250 extern volatile struct SCI_REGS ScidRegs; 251 #endif 252 #ifdef CPU2 253 extern volatile struct SCI_REGS SciaRegs; 254 extern volatile struct SCI_REGS ScibRegs; 255 extern volatile struct SCI_REGS ScicRegs; 256 extern volatile struct SCI_REGS ScidRegs; 257 #endif 258 #ifdef __cplusplus 259 } 260 #endif /* extern "C" */ 261 262 #endif 263 264 //=========================================================================== 265 // End of file. 266 //=========================================================================== 267