1 /** 2 ****************************************************************************** 3 * @file sdio2.h 4 * @version V1.0 5 * @date 2022-08-03 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __HARDWARE_SDIO2_H__ 37 #define __HARDWARE_SDIO2_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 45 #define SDIO2_IO_ENABLE_OFFSET (0x0002) /* SDIO I/O Enable */ 46 #define SDIO2_FN1_BLK_SIZE_0_OFFSET (0x0028) /* SDIO block size infor */ 47 #define SDIO2_FN1_BLK_SIZE_1_OFFSET (0x0029) /* SDIO block size infor */ 48 #define SDIO2_DEV_SLEEP_OFFSET (0x0092) /* SDIO Device Sleep */ 49 #define SDIO2_CCR_FUNC_OFFSET (0x0100) /* Address offset of CCR between two functions */ 50 #define SDIO2_HOST_TO_CARD_EVENT_OFFSET (0x0100) 51 #define SDIO2_HOST_INT_CAUSE_OFFSET (0x0101) 52 #define SDIO2_HOST_INT_MASK_OFFSET (0x0102) 53 #define SDIO2_HOST_INT_STATUS_OFFSET (0x0103) 54 #define SDIO2_RD_BIT_MAP_OFFSET (0x0104) 55 #define SDIO2_WR_BIT_MAP_OFFSET (0x0106) 56 #define SDIO2_RD_LEN_OFFSET (0x0108) 57 #define SDIO2_HOST_TRANS_STATUS_OFFSET (0x0128) 58 #define SDIO2_CARD_TO_HOST_EVENT_OFFSET (0x0130) 59 #define SDIO2_CARD_INT_MASK_OFFSET (0x0134) 60 #define SDIO2_CARD_INT_STATUS_OFFSET (0x0138) 61 #define SDIO2_CARD_INT_MODE_OFFSET (0x013C) 62 #define SDIO2_SQ_READ_BASE_OFFSET (0x0140) 63 #define SDIO2_SQ_WRITE_BASE_OFFSET (0x0144) 64 #define SDIO2_READ_INDEX_OFFSET (0x0148) 65 #define SDIO2_WRITE_INDEX_OFFSET (0x0149) 66 #define SDIO2_DNLD_QUEUE_WRPTR_OFFSET (0x014A) 67 #define SDIO2_UPLD_QUEUE_WRPTR_OFFSET (0x014B) 68 #define SDIO2_DNLD_QUEUE_OFFSET (0x014C) 69 #define SDIO2_UPLD_QUEUE_OFFSET (0x0154) 70 #define SDIO2_CHIP_VERSION_OFFSET (0x015C) 71 #define SDIO2_IP_VERSION0_OFFSET (0x015E) 72 #define SDIO2_IP_VERSION1_OFFSET (0x015F) 73 #define SDIO2_SCRATCH2_OFFSET (0x0164) 74 #define SDIO2_SCRATCH1_OFFSET (0x0166) 75 #define SDIO2_OCR0_OFFSET (0x0168) 76 #define SDIO2_OCR1_OFFSET (0x0169) 77 #define SDIO2_OCR2_OFFSET (0x016A) 78 #define SDIO2_CONFIG_OFFSET (0x016B) 79 #define SDIO2_CONFIG2_OFFSET (0x016C) 80 #define SDIO2_DEBUG_OFFSET (0x0170) 81 #define SDIO2_DMA_ADDR_OFFSET (0x0174) 82 #define SDIO2_IO_PORT_OFFSET (0x0178) 83 84 85 // Bit Def. Scratch register 0 86 #define SDIO2_SCRATCH_OFFSET (0x0160) 87 88 // Bit Def. Block size 1 mask (Offset 0x29) 89 #define SDIO2_FN1_BLK_SIZE_1_MASK 0x01 90 91 // Bit Def. Host To Card Interrupt Event (Offset 0x100/200) 92 #define SDIO2_HCR_CONFIG_HostPwrUp (1 << 1) 93 94 // Bit Def. Host Transfer Status (Offset 0x128/228) 95 #define SDIO2_CCR_HOST_INT_DnLdReStart (1 << 0) 96 #define SDIO2_CCR_HOST_INT_UpLdReStart (1 << 1) 97 #define SDIO2_CCR_HOST_INT_DnLdCRC_err (1 << 2) 98 99 // Bit Def. Card To Host Interrupt Event (Offset 0x130/230) 100 #define SDIO2_CCR_CS_DnLdRdy (1 << 0) 101 #define SDIO2_CCR_CS_UpLdRdy (1 << 1) 102 #define SDIO2_CCR_CS_ReadCISRdy (1 << 2) 103 #define SDIO2_CCR_CS_IORdy (1 << 3) 104 105 // Bit Def. Card Interrupt Mask (Offset 0x134/234) 106 #define SDIO2_CCR_CIM_DnLdOvr (1 << 0) 107 #define SDIO2_CCR_CIM_UpLdOvr (1 << 1) 108 #define SDIO2_CCR_CIM_Abort (1 << 2) 109 #define SDIO2_CCR_CIM_PwrDn (1 << 3) 110 #define SDIO2_CCR_CIM_PwrUp (1 << 4) 111 112 #define SDIO2_CCR_CIM_MASK 0x0007 113 114 // Bit Def. Card Interrupt Status (Offset 0x138/238) 115 #define SDIO2_CCR_CIC_DnLdOvr (1 << 0) 116 #define SDIO2_CCR_CIC_UpLdOvr (1 << 1) 117 #define SDIO2_CCR_CIC_Abort (1 << 2) 118 #define SDIO2_CCR_CIC_PwrDn (1 << 3) 119 #define SDIO2_CCR_CIC_PwrUp (1 << 4) 120 121 #define SDIO2_CCR_CIC_MASK 0x001F 122 123 // Bit Def. Card Interrupt RSR (Offset 0x13C/23C) 124 #define SDIO2_CCR_CIO_DnLdOvr (1 << 0) 125 #define SDIO2_CCR_CIO_UpLdOvr (1 << 1) 126 #define SDIO2_CCR_CIO_Abort (1 << 2) 127 #define SDIO2_CCR_CIO_PwrDn (1 << 3) 128 #define SDIO2_CCR_CIO_PwrUp (1 << 4) 129 #define SDIO2_CCR_CIO_MASK 0x001F 130 131 //Config2 register mask 132 #define SDIO2_CONFIG2_MSK 0x00000C00 133 134 //CardIntMode register mask 135 136 #define SDIO2_CARD_INT_MODE_MSK 0x00000003 137 #define SDIO2_HOST_INT_MSK 0x00000002 138 139 #endif /* __HARDWARE_SDIO2_H__ */ 140