1 /** 2 ****************************************************************************** 3 * @file sec_eng_reg.h 4 * @version V1.0 5 * @date 2022-08-15 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __HARDWARE_SEC_ENG_H__ 37 #define __HARDWARE_SEC_ENG_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 45 #define SEC_ENG_SE_SHA_0_CTRL_OFFSET (0x0) /* se_sha_0_ctrl */ 46 #define SEC_ENG_SE_SHA_0_MSA_OFFSET (0x4) /* se_sha_0_msa */ 47 #define SEC_ENG_SE_SHA_0_STATUS_OFFSET (0x8) /* se_sha_0_status */ 48 #define SEC_ENG_SE_SHA_0_ENDIAN_OFFSET (0xC) /* se_sha_0_endian */ 49 #define SEC_ENG_SE_SHA_0_HASH_L_0_OFFSET (0x10) /* se_sha_0_hash_l_0 */ 50 #define SEC_ENG_SE_SHA_0_HASH_L_1_OFFSET (0x14) /* se_sha_0_hash_l_1 */ 51 #define SEC_ENG_SE_SHA_0_HASH_L_2_OFFSET (0x18) /* se_sha_0_hash_l_2 */ 52 #define SEC_ENG_SE_SHA_0_HASH_L_3_OFFSET (0x1C) /* se_sha_0_hash_l_3 */ 53 #define SEC_ENG_SE_SHA_0_HASH_L_4_OFFSET (0x20) /* se_sha_0_hash_l_4 */ 54 #define SEC_ENG_SE_SHA_0_HASH_L_5_OFFSET (0x24) /* se_sha_0_hash_l_5 */ 55 #define SEC_ENG_SE_SHA_0_HASH_L_6_OFFSET (0x28) /* se_sha_0_hash_l_6 */ 56 #define SEC_ENG_SE_SHA_0_HASH_L_7_OFFSET (0x2C) /* se_sha_0_hash_l_7 */ 57 #define SEC_ENG_SE_SHA_0_HASH_H_0_OFFSET (0x30) /* se_sha_0_hash_h_0 */ 58 #define SEC_ENG_SE_SHA_0_HASH_H_1_OFFSET (0x34) /* se_sha_0_hash_h_1 */ 59 #define SEC_ENG_SE_SHA_0_HASH_H_2_OFFSET (0x38) /* se_sha_0_hash_h_2 */ 60 #define SEC_ENG_SE_SHA_0_HASH_H_3_OFFSET (0x3C) /* se_sha_0_hash_h_3 */ 61 #define SEC_ENG_SE_SHA_0_HASH_H_4_OFFSET (0x40) /* se_sha_0_hash_h_4 */ 62 #define SEC_ENG_SE_SHA_0_HASH_H_5_OFFSET (0x44) /* se_sha_0_hash_h_5 */ 63 #define SEC_ENG_SE_SHA_0_HASH_H_6_OFFSET (0x48) /* se_sha_0_hash_h_6 */ 64 #define SEC_ENG_SE_SHA_0_HASH_H_7_OFFSET (0x4C) /* se_sha_0_hash_h_7 */ 65 #define SEC_ENG_SE_SHA_0_LINK_OFFSET (0x50) /* se_sha_0_link */ 66 #define SEC_ENG_SE_SHA_0_CTRL_PROT_OFFSET (0xFC) /* se_sha_0_ctrl_prot */ 67 #define SEC_ENG_SE_AES_0_CTRL_OFFSET (0x100) /* se_aes_0_ctrl */ 68 #define SEC_ENG_SE_AES_0_MSA_OFFSET (0x104) /* se_aes_0_msa */ 69 #define SEC_ENG_SE_AES_0_MDA_OFFSET (0x108) /* se_aes_0_mda */ 70 #define SEC_ENG_SE_AES_0_STATUS_OFFSET (0x10C) /* se_aes_0_status */ 71 #define SEC_ENG_SE_AES_0_IV_0_OFFSET (0x110) /* se_aes_0_iv_0 */ 72 #define SEC_ENG_SE_AES_0_IV_1_OFFSET (0x114) /* se_aes_0_iv_1 */ 73 #define SEC_ENG_SE_AES_0_IV_2_OFFSET (0x118) /* se_aes_0_iv_2 */ 74 #define SEC_ENG_SE_AES_0_IV_3_OFFSET (0x11C) /* se_aes_0_iv_3 */ 75 #define SEC_ENG_SE_AES_0_KEY_0_OFFSET (0x120) /* se_aes_0_key_0 */ 76 #define SEC_ENG_SE_AES_0_KEY_1_OFFSET (0x124) /* se_aes_0_key_1 */ 77 #define SEC_ENG_SE_AES_0_KEY_2_OFFSET (0x128) /* se_aes_0_key_2 */ 78 #define SEC_ENG_SE_AES_0_KEY_3_OFFSET (0x12C) /* se_aes_0_key_3 */ 79 #define SEC_ENG_SE_AES_0_KEY_4_OFFSET (0x130) /* se_aes_0_key_4 */ 80 #define SEC_ENG_SE_AES_0_KEY_5_OFFSET (0x134) /* se_aes_0_key_5 */ 81 #define SEC_ENG_SE_AES_0_KEY_6_OFFSET (0x138) /* se_aes_0_key_6 */ 82 #define SEC_ENG_SE_AES_0_KEY_7_OFFSET (0x13C) /* se_aes_0_key_7 */ 83 #define SEC_ENG_SE_AES_0_KEY_SEL_OFFSET (0x140) /* se_aes_0_key_sel */ 84 #define SEC_ENG_SE_AES_1_KEY_SEL_OFFSET (0x144) /* se_aes_1_key_sel */ 85 #define SEC_ENG_SE_AES_0_ENDIAN_OFFSET (0x148) /* se_aes_0_endian */ 86 #define SEC_ENG_SE_AES_0_SBOOT_OFFSET (0x14C) /* se_aes_0_sboot */ 87 #define SEC_ENG_SE_AES_0_LINK_OFFSET (0x150) /* se_aes_0_link */ 88 #define SEC_ENG_SE_AES_0_CTRL_PROT_OFFSET (0x1FC) /* se_aes_0_ctrl_prot */ 89 #define SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET (0x200) /* se_trng_0_ctrl_0 */ 90 #define SEC_ENG_SE_TRNG_0_STATUS_OFFSET (0x204) /* se_trng_0_status */ 91 #define SEC_ENG_SE_TRNG_0_DOUT_0_OFFSET (0x208) /* se_trng_0_dout_0 */ 92 #define SEC_ENG_SE_TRNG_0_DOUT_1_OFFSET (0x20C) /* se_trng_0_dout_1 */ 93 #define SEC_ENG_SE_TRNG_0_DOUT_2_OFFSET (0x210) /* se_trng_0_dout_2 */ 94 #define SEC_ENG_SE_TRNG_0_DOUT_3_OFFSET (0x214) /* se_trng_0_dout_3 */ 95 #define SEC_ENG_SE_TRNG_0_DOUT_4_OFFSET (0x218) /* se_trng_0_dout_4 */ 96 #define SEC_ENG_SE_TRNG_0_DOUT_5_OFFSET (0x21C) /* se_trng_0_dout_5 */ 97 #define SEC_ENG_SE_TRNG_0_DOUT_6_OFFSET (0x220) /* se_trng_0_dout_6 */ 98 #define SEC_ENG_SE_TRNG_0_DOUT_7_OFFSET (0x224) /* se_trng_0_dout_7 */ 99 #define SEC_ENG_SE_TRNG_0_TEST_OFFSET (0x228) /* se_trng_0_test */ 100 #define SEC_ENG_SE_TRNG_0_CTRL_1_OFFSET (0x22C) /* se_trng_0_ctrl_1 */ 101 #define SEC_ENG_SE_TRNG_0_CTRL_2_OFFSET (0x230) /* se_trng_0_ctrl_2 */ 102 #define SEC_ENG_SE_TRNG_0_CTRL_3_OFFSET (0x234) /* se_trng_0_ctrl_3 */ 103 #define SEC_ENG_SE_TRNG_0_TEST_OUT_0_OFFSET (0x240) /* se_trng_0_test_out_0 */ 104 #define SEC_ENG_SE_TRNG_0_TEST_OUT_1_OFFSET (0x244) /* se_trng_0_test_out_1 */ 105 #define SEC_ENG_SE_TRNG_0_TEST_OUT_2_OFFSET (0x248) /* se_trng_0_test_out_2 */ 106 #define SEC_ENG_SE_TRNG_0_TEST_OUT_3_OFFSET (0x24C) /* se_trng_0_test_out_3 */ 107 #define SEC_ENG_SE_TRNG_0_CTRL_PROT_OFFSET (0x2FC) /* se_trng_0_ctrl_prot */ 108 #define SEC_ENG_SE_PKA_0_CTRL_0_OFFSET (0x300) /* se_pka_0_ctrl_0 */ 109 #define SEC_ENG_SE_PKA_0_SEED_OFFSET (0x30C) /* se_pka_0_seed */ 110 #define SEC_ENG_SE_PKA_0_CTRL_1_OFFSET (0x310) /* se_pka_0_ctrl_1 */ 111 #define SEC_ENG_SE_PKA_0_RW_OFFSET (0x340) /* se_pka_0_rw */ 112 #define SEC_ENG_SE_PKA_0_RW_BURST_OFFSET (0x360) /* se_pka_0_rw_burst */ 113 #define SEC_ENG_SE_PKA_0_CTRL_PROT_OFFSET (0x3FC) /* se_pka_0_ctrl_prot */ 114 #define SEC_ENG_SE_CDET_0_CTRL_0_OFFSET (0x400) /* se_cdet_0_ctrl_0 */ 115 #define SEC_ENG_SE_CDET_0_CTRL_1_OFFSET (0x404) /* se_cdet_0_ctrl_1 */ 116 #define SEC_ENG_SE_CDET_0_CTRL_2_OFFSET (0x408) /* se_cdet_0_ctrl_2 */ 117 #define SEC_ENG_SE_CDET_0_CTRL_3_OFFSET (0x40C) /* se_cdet_0_ctrl_3 */ 118 #define SEC_ENG_SE_CDET_0_CTRL_PROT_OFFSET (0x4FC) /* se_cdet_0_ctrl_prot */ 119 #define SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET (0x500) /* se_gmac_0_ctrl_0 */ 120 #define SEC_ENG_SE_GMAC_0_LCA_OFFSET (0x504) /* se_gmac_0_lca */ 121 #define SEC_ENG_SE_GMAC_0_STATUS_OFFSET (0x508) /* se_gmac_0_status */ 122 #define SEC_ENG_SE_GMAC_0_CTRL_PROT_OFFSET (0x5FC) /* se_gmac_0_ctrl_prot */ 123 #define SEC_ENG_SE_CTRL_PROT_RD_OFFSET (0xF00) /* se_ctrl_prot_rd */ 124 #define SEC_ENG_SE_CTRL_RESERVED_0_OFFSET (0xF04) /* se_ctrl_reserved_0 */ 125 #define SEC_ENG_SE_CTRL_RESERVED_1_OFFSET (0xF08) /* se_ctrl_reserved_1 */ 126 #define SEC_ENG_SE_CTRL_RESERVED_2_OFFSET (0xF0C) /* se_ctrl_reserved_2 */ 127 128 /* Register Bitfield definitions *****************************************************/ 129 130 /* 0x0 : se_sha_0_ctrl */ 131 #define SEC_ENG_SE_SHA_0_BUSY (1 << 0U) 132 #define SEC_ENG_SE_SHA_0_TRIG_1T (1 << 1U) 133 #define SEC_ENG_SE_SHA_0_MODE_SHIFT (2U) 134 #define SEC_ENG_SE_SHA_0_MODE_MASK (0x7 << SEC_ENG_SE_SHA_0_MODE_SHIFT) 135 #define SEC_ENG_SE_SHA_0_EN (1 << 5U) 136 #define SEC_ENG_SE_SHA_0_HASH_SEL (1 << 6U) 137 #define SEC_ENG_SE_SHA_0_INT (1 << 8U) 138 #define SEC_ENG_SE_SHA_0_INT_CLR_1T (1 << 9U) 139 #define SEC_ENG_SE_SHA_0_INT_SET_1T (1 << 10U) 140 #define SEC_ENG_SE_SHA_0_INT_MASK (1 << 11U) 141 #define SEC_ENG_SE_SHA_0_MODE_EXT_SHIFT (12U) 142 #define SEC_ENG_SE_SHA_0_MODE_EXT_MASK (0x3 << SEC_ENG_SE_SHA_0_MODE_EXT_SHIFT) 143 #define SEC_ENG_SE_SHA_0_LINK_MODE (1 << 15U) 144 #define SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT (16U) 145 #define SEC_ENG_SE_SHA_0_MSG_LEN_MASK (0xffff << SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT) 146 147 /* 0x4 : se_sha_0_msa */ 148 #define SEC_ENG_SE_SHA_0_MSA_SHIFT (0U) 149 #define SEC_ENG_SE_SHA_0_MSA_MASK (0xffffffff << SEC_ENG_SE_SHA_0_MSA_SHIFT) 150 151 /* 0x8 : se_sha_0_status */ 152 #define SEC_ENG_SE_SHA_0_STATUS_SHIFT (0U) 153 #define SEC_ENG_SE_SHA_0_STATUS_MASK (0xffffffff << SEC_ENG_SE_SHA_0_STATUS_SHIFT) 154 155 /* 0xC : se_sha_0_endian */ 156 #define SEC_ENG_SE_SHA_0_DOUT_ENDIAN (1 << 0U) 157 158 /* 0x10 : se_sha_0_hash_l_0 */ 159 #define SEC_ENG_SE_SHA_0_HASH_L_0_SHIFT (0U) 160 #define SEC_ENG_SE_SHA_0_HASH_L_0_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_0_SHIFT) 161 162 /* 0x14 : se_sha_0_hash_l_1 */ 163 #define SEC_ENG_SE_SHA_0_HASH_L_1_SHIFT (0U) 164 #define SEC_ENG_SE_SHA_0_HASH_L_1_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_1_SHIFT) 165 166 /* 0x18 : se_sha_0_hash_l_2 */ 167 #define SEC_ENG_SE_SHA_0_HASH_L_2_SHIFT (0U) 168 #define SEC_ENG_SE_SHA_0_HASH_L_2_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_2_SHIFT) 169 170 /* 0x1C : se_sha_0_hash_l_3 */ 171 #define SEC_ENG_SE_SHA_0_HASH_L_3_SHIFT (0U) 172 #define SEC_ENG_SE_SHA_0_HASH_L_3_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_3_SHIFT) 173 174 /* 0x20 : se_sha_0_hash_l_4 */ 175 #define SEC_ENG_SE_SHA_0_HASH_L_4_SHIFT (0U) 176 #define SEC_ENG_SE_SHA_0_HASH_L_4_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_4_SHIFT) 177 178 /* 0x24 : se_sha_0_hash_l_5 */ 179 #define SEC_ENG_SE_SHA_0_HASH_L_5_SHIFT (0U) 180 #define SEC_ENG_SE_SHA_0_HASH_L_5_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_5_SHIFT) 181 182 /* 0x28 : se_sha_0_hash_l_6 */ 183 #define SEC_ENG_SE_SHA_0_HASH_L_6_SHIFT (0U) 184 #define SEC_ENG_SE_SHA_0_HASH_L_6_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_6_SHIFT) 185 186 /* 0x2C : se_sha_0_hash_l_7 */ 187 #define SEC_ENG_SE_SHA_0_HASH_L_7_SHIFT (0U) 188 #define SEC_ENG_SE_SHA_0_HASH_L_7_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_7_SHIFT) 189 190 /* 0x30 : se_sha_0_hash_h_0 */ 191 #define SEC_ENG_SE_SHA_0_HASH_H_0_SHIFT (0U) 192 #define SEC_ENG_SE_SHA_0_HASH_H_0_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_0_SHIFT) 193 194 /* 0x34 : se_sha_0_hash_h_1 */ 195 #define SEC_ENG_SE_SHA_0_HASH_H_1_SHIFT (0U) 196 #define SEC_ENG_SE_SHA_0_HASH_H_1_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_1_SHIFT) 197 198 /* 0x38 : se_sha_0_hash_h_2 */ 199 #define SEC_ENG_SE_SHA_0_HASH_H_2_SHIFT (0U) 200 #define SEC_ENG_SE_SHA_0_HASH_H_2_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_2_SHIFT) 201 202 /* 0x3C : se_sha_0_hash_h_3 */ 203 #define SEC_ENG_SE_SHA_0_HASH_H_3_SHIFT (0U) 204 #define SEC_ENG_SE_SHA_0_HASH_H_3_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_3_SHIFT) 205 206 /* 0x40 : se_sha_0_hash_h_4 */ 207 #define SEC_ENG_SE_SHA_0_HASH_H_4_SHIFT (0U) 208 #define SEC_ENG_SE_SHA_0_HASH_H_4_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_4_SHIFT) 209 210 /* 0x44 : se_sha_0_hash_h_5 */ 211 #define SEC_ENG_SE_SHA_0_HASH_H_5_SHIFT (0U) 212 #define SEC_ENG_SE_SHA_0_HASH_H_5_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_5_SHIFT) 213 214 /* 0x48 : se_sha_0_hash_h_6 */ 215 #define SEC_ENG_SE_SHA_0_HASH_H_6_SHIFT (0U) 216 #define SEC_ENG_SE_SHA_0_HASH_H_6_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_6_SHIFT) 217 218 /* 0x4C : se_sha_0_hash_h_7 */ 219 #define SEC_ENG_SE_SHA_0_HASH_H_7_SHIFT (0U) 220 #define SEC_ENG_SE_SHA_0_HASH_H_7_MASK (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_7_SHIFT) 221 222 /* 0x50 : se_sha_0_link */ 223 #define SEC_ENG_SE_SHA_0_LCA_SHIFT (0U) 224 #define SEC_ENG_SE_SHA_0_LCA_MASK (0xffffffff << SEC_ENG_SE_SHA_0_LCA_SHIFT) 225 226 /* 0xFC : se_sha_0_ctrl_prot */ 227 #define SEC_ENG_SE_SHA_ID0_EN (1 << 1U) 228 #define SEC_ENG_SE_SHA_ID1_EN (1 << 2U) 229 230 /* 0x100 : se_aes_0_ctrl */ 231 #define SEC_ENG_SE_AES_0_BUSY (1 << 0U) 232 #define SEC_ENG_SE_AES_0_TRIG_1T (1 << 1U) 233 #define SEC_ENG_SE_AES_0_EN (1 << 2U) 234 #define SEC_ENG_SE_AES_0_MODE_SHIFT (3U) 235 #define SEC_ENG_SE_AES_0_MODE_MASK (0x3 << SEC_ENG_SE_AES_0_MODE_SHIFT) 236 #define SEC_ENG_SE_AES_0_DEC_EN (1 << 5U) 237 #define SEC_ENG_SE_AES_0_DEC_KEY_SEL (1 << 6U) 238 #define SEC_ENG_SE_AES_0_HW_KEY_EN (1 << 7U) 239 #define SEC_ENG_SE_AES_0_INT (1 << 8U) 240 #define SEC_ENG_SE_AES_0_INT_CLR_1T (1 << 9U) 241 #define SEC_ENG_SE_AES_0_INT_SET_1T (1 << 10U) 242 #define SEC_ENG_SE_AES_0_INT_MASK (1 << 11U) 243 #define SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT (12U) 244 #define SEC_ENG_SE_AES_0_BLOCK_MODE_MASK (0x3 << SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT) 245 #define SEC_ENG_SE_AES_0_IV_SEL (1 << 14U) 246 #define SEC_ENG_SE_AES_0_LINK_MODE (1 << 15U) 247 #define SEC_ENG_SE_AES_0_MSG_LEN_SHIFT (16U) 248 #define SEC_ENG_SE_AES_0_MSG_LEN_MASK (0xffff << SEC_ENG_SE_AES_0_MSG_LEN_SHIFT) 249 250 /* 0x104 : se_aes_0_msa */ 251 #define SEC_ENG_SE_AES_0_MSA_SHIFT (0U) 252 #define SEC_ENG_SE_AES_0_MSA_MASK (0xffffffff << SEC_ENG_SE_AES_0_MSA_SHIFT) 253 254 /* 0x108 : se_aes_0_mda */ 255 #define SEC_ENG_SE_AES_0_MDA_SHIFT (0U) 256 #define SEC_ENG_SE_AES_0_MDA_MASK (0xffffffff << SEC_ENG_SE_AES_0_MDA_SHIFT) 257 258 /* 0x10C : se_aes_0_status */ 259 #define SEC_ENG_SE_AES_0_STATUS_SHIFT (0U) 260 #define SEC_ENG_SE_AES_0_STATUS_MASK (0xffffffff << SEC_ENG_SE_AES_0_STATUS_SHIFT) 261 262 /* 0x110 : se_aes_0_iv_0 */ 263 #define SEC_ENG_SE_AES_0_IV_0_SHIFT (0U) 264 #define SEC_ENG_SE_AES_0_IV_0_MASK (0xffffffff << SEC_ENG_SE_AES_0_IV_0_SHIFT) 265 266 /* 0x114 : se_aes_0_iv_1 */ 267 #define SEC_ENG_SE_AES_0_IV_1_SHIFT (0U) 268 #define SEC_ENG_SE_AES_0_IV_1_MASK (0xffffffff << SEC_ENG_SE_AES_0_IV_1_SHIFT) 269 270 /* 0x118 : se_aes_0_iv_2 */ 271 #define SEC_ENG_SE_AES_0_IV_2_SHIFT (0U) 272 #define SEC_ENG_SE_AES_0_IV_2_MASK (0xffffffff << SEC_ENG_SE_AES_0_IV_2_SHIFT) 273 274 /* 0x11C : se_aes_0_iv_3 */ 275 #define SEC_ENG_SE_AES_0_IV_3_SHIFT (0U) 276 #define SEC_ENG_SE_AES_0_IV_3_MASK (0xffffffff << SEC_ENG_SE_AES_0_IV_3_SHIFT) 277 278 /* 0x120 : se_aes_0_key_0 */ 279 #define SEC_ENG_SE_AES_0_KEY_0_SHIFT (0U) 280 #define SEC_ENG_SE_AES_0_KEY_0_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_0_SHIFT) 281 282 /* 0x124 : se_aes_0_key_1 */ 283 #define SEC_ENG_SE_AES_0_KEY_1_SHIFT (0U) 284 #define SEC_ENG_SE_AES_0_KEY_1_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_1_SHIFT) 285 286 /* 0x128 : se_aes_0_key_2 */ 287 #define SEC_ENG_SE_AES_0_KEY_2_SHIFT (0U) 288 #define SEC_ENG_SE_AES_0_KEY_2_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_2_SHIFT) 289 290 /* 0x12C : se_aes_0_key_3 */ 291 #define SEC_ENG_SE_AES_0_KEY_3_SHIFT (0U) 292 #define SEC_ENG_SE_AES_0_KEY_3_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_3_SHIFT) 293 294 /* 0x130 : se_aes_0_key_4 */ 295 #define SEC_ENG_SE_AES_0_KEY_4_SHIFT (0U) 296 #define SEC_ENG_SE_AES_0_KEY_4_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_4_SHIFT) 297 298 /* 0x134 : se_aes_0_key_5 */ 299 #define SEC_ENG_SE_AES_0_KEY_5_SHIFT (0U) 300 #define SEC_ENG_SE_AES_0_KEY_5_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_5_SHIFT) 301 302 /* 0x138 : se_aes_0_key_6 */ 303 #define SEC_ENG_SE_AES_0_KEY_6_SHIFT (0U) 304 #define SEC_ENG_SE_AES_0_KEY_6_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_6_SHIFT) 305 306 /* 0x13C : se_aes_0_key_7 */ 307 #define SEC_ENG_SE_AES_0_KEY_7_SHIFT (0U) 308 #define SEC_ENG_SE_AES_0_KEY_7_MASK (0xffffffff << SEC_ENG_SE_AES_0_KEY_7_SHIFT) 309 310 /* 0x140 : se_aes_0_key_sel */ 311 #define SEC_ENG_SE_AES_0_KEY_SEL_SHIFT (0U) 312 #define SEC_ENG_SE_AES_0_KEY_SEL_MASK (0x3 << SEC_ENG_SE_AES_0_KEY_SEL_SHIFT) 313 314 /* 0x144 : se_aes_1_key_sel */ 315 #define SEC_ENG_SE_AES_1_KEY_SEL_SHIFT (0U) 316 #define SEC_ENG_SE_AES_1_KEY_SEL_MASK (0x3 << SEC_ENG_SE_AES_1_KEY_SEL_SHIFT) 317 318 /* 0x148 : se_aes_0_endian */ 319 #define SEC_ENG_SE_AES_0_DOUT_ENDIAN (1 << 0U) 320 #define SEC_ENG_SE_AES_0_DIN_ENDIAN (1 << 1U) 321 #define SEC_ENG_SE_AES_0_KEY_ENDIAN (1 << 2U) 322 #define SEC_ENG_SE_AES_0_IV_ENDIAN (1 << 3U) 323 #define SEC_ENG_SE_AES_0_TWK_ENDIAN (1 << 4U) 324 #define SEC_ENG_SE_AES_0_CTR_LEN_SHIFT (30U) 325 #define SEC_ENG_SE_AES_0_CTR_LEN_MASK (0x3 << SEC_ENG_SE_AES_0_CTR_LEN_SHIFT) 326 327 /* 0x14C : se_aes_sboot */ 328 #define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL (1 << 0U) 329 #define SEC_ENG_SE_AES_0_XTS_MODE (1 << 15U) 330 #define SEC_ENG_SE_AES_0_UNI_LEN_SHIFT (16U) 331 #define SEC_ENG_SE_AES_0_UNI_LEN_MASK (0xffff << SEC_ENG_SE_AES_0_UNI_LEN_SHIFT) 332 333 /* 0x150 : se_aes_0_link */ 334 #define SEC_ENG_SE_AES_0_LCA_SHIFT (0U) 335 #define SEC_ENG_SE_AES_0_LCA_MASK (0xffffffff << SEC_ENG_SE_AES_0_LCA_SHIFT) 336 337 /* 0x1FC : se_aes_0_ctrl_prot */ 338 #define SEC_ENG_SE_AES_ID0_EN (1 << 1U) 339 #define SEC_ENG_SE_AES_ID1_EN (1 << 2U) 340 341 /* 0x200 : se_trng_0_ctrl_0 */ 342 #define SEC_ENG_SE_TRNG_0_BUSY (1 << 0U) 343 #define SEC_ENG_SE_TRNG_0_TRIG_1T (1 << 1U) 344 #define SEC_ENG_SE_TRNG_0_EN (1 << 2U) 345 #define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T (1 << 3U) 346 #define SEC_ENG_SE_TRNG_0_HT_ERROR (1 << 4U) 347 #define SEC_ENG_SE_TRNG_0_INT (1 << 8U) 348 #define SEC_ENG_SE_TRNG_0_INT_CLR_1T (1 << 9U) 349 #define SEC_ENG_SE_TRNG_0_INT_SET_1T (1 << 10U) 350 #define SEC_ENG_SE_TRNG_0_INT_MASK (1 << 11U) 351 #define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL (1 << 13U) 352 #define SEC_ENG_SE_TRNG_0_MANUAL_RESEED (1 << 14U) 353 #define SEC_ENG_SE_TRNG_0_MANUAL_EN (1 << 15U) 354 355 /* 0x204 : se_trng_0_status */ 356 #define SEC_ENG_SE_TRNG_0_STATUS_SHIFT (0U) 357 #define SEC_ENG_SE_TRNG_0_STATUS_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_STATUS_SHIFT) 358 359 /* 0x208 : se_trng_0_dout_0 */ 360 #define SEC_ENG_SE_TRNG_0_DOUT_0_SHIFT (0U) 361 #define SEC_ENG_SE_TRNG_0_DOUT_0_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_0_SHIFT) 362 363 /* 0x20C : se_trng_0_dout_1 */ 364 #define SEC_ENG_SE_TRNG_0_DOUT_1_SHIFT (0U) 365 #define SEC_ENG_SE_TRNG_0_DOUT_1_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_1_SHIFT) 366 367 /* 0x210 : se_trng_0_dout_2 */ 368 #define SEC_ENG_SE_TRNG_0_DOUT_2_SHIFT (0U) 369 #define SEC_ENG_SE_TRNG_0_DOUT_2_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_2_SHIFT) 370 371 /* 0x214 : se_trng_0_dout_3 */ 372 #define SEC_ENG_SE_TRNG_0_DOUT_3_SHIFT (0U) 373 #define SEC_ENG_SE_TRNG_0_DOUT_3_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_3_SHIFT) 374 375 /* 0x218 : se_trng_0_dout_4 */ 376 #define SEC_ENG_SE_TRNG_0_DOUT_4_SHIFT (0U) 377 #define SEC_ENG_SE_TRNG_0_DOUT_4_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_4_SHIFT) 378 379 /* 0x21C : se_trng_0_dout_5 */ 380 #define SEC_ENG_SE_TRNG_0_DOUT_5_SHIFT (0U) 381 #define SEC_ENG_SE_TRNG_0_DOUT_5_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_5_SHIFT) 382 383 /* 0x220 : se_trng_0_dout_6 */ 384 #define SEC_ENG_SE_TRNG_0_DOUT_6_SHIFT (0U) 385 #define SEC_ENG_SE_TRNG_0_DOUT_6_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_6_SHIFT) 386 387 /* 0x224 : se_trng_0_dout_7 */ 388 #define SEC_ENG_SE_TRNG_0_DOUT_7_SHIFT (0U) 389 #define SEC_ENG_SE_TRNG_0_DOUT_7_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_7_SHIFT) 390 391 /* 0x228 : se_trng_0_test */ 392 #define SEC_ENG_SE_TRNG_0_TEST_EN (1 << 0U) 393 #define SEC_ENG_SE_TRNG_0_CP_TEST_EN (1 << 1U) 394 #define SEC_ENG_SE_TRNG_0_CP_BYPASS (1 << 2U) 395 #define SEC_ENG_SE_TRNG_0_HT_DIS (1 << 3U) 396 #define SEC_ENG_SE_TRNG_0_HT_ALARM_N_SHIFT (4U) 397 #define SEC_ENG_SE_TRNG_0_HT_ALARM_N_MASK (0xff << SEC_ENG_SE_TRNG_0_HT_ALARM_N_SHIFT) 398 399 /* 0x22C : se_trng_0_ctrl_1 */ 400 #define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_SHIFT (0U) 401 #define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_SHIFT) 402 403 /* 0x230 : se_trng_0_ctrl_2 */ 404 #define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_SHIFT (0U) 405 #define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_MASK (0xffff << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_SHIFT) 406 407 /* 0x234 : se_trng_0_ctrl_3 */ 408 #define SEC_ENG_SE_TRNG_0_CP_RATIO_SHIFT (0U) 409 #define SEC_ENG_SE_TRNG_0_CP_RATIO_MASK (0xff << SEC_ENG_SE_TRNG_0_CP_RATIO_SHIFT) 410 #define SEC_ENG_SE_TRNG_0_HT_RCT_C_SHIFT (8U) 411 #define SEC_ENG_SE_TRNG_0_HT_RCT_C_MASK (0xff << SEC_ENG_SE_TRNG_0_HT_RCT_C_SHIFT) 412 #define SEC_ENG_SE_TRNG_0_HT_APT_C_SHIFT (16U) 413 #define SEC_ENG_SE_TRNG_0_HT_APT_C_MASK (0x3ff << SEC_ENG_SE_TRNG_0_HT_APT_C_SHIFT) 414 #define SEC_ENG_SE_TRNG_0_HT_OD_EN (1 << 26U) 415 #define SEC_ENG_SE_TRNG_0_ROSC_EN (1 << 31U) 416 417 /* 0x240 : se_trng_0_test_out_0 */ 418 #define SEC_ENG_SE_TRNG_0_TEST_OUT_0_SHIFT (0U) 419 #define SEC_ENG_SE_TRNG_0_TEST_OUT_0_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_TEST_OUT_0_SHIFT) 420 421 /* 0x244 : se_trng_0_test_out_1 */ 422 #define SEC_ENG_SE_TRNG_0_TEST_OUT_1_SHIFT (0U) 423 #define SEC_ENG_SE_TRNG_0_TEST_OUT_1_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_TEST_OUT_1_SHIFT) 424 425 /* 0x248 : se_trng_0_test_out_2 */ 426 #define SEC_ENG_SE_TRNG_0_TEST_OUT_2_SHIFT (0U) 427 #define SEC_ENG_SE_TRNG_0_TEST_OUT_2_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_TEST_OUT_2_SHIFT) 428 429 /* 0x24C : se_trng_0_test_out_3 */ 430 #define SEC_ENG_SE_TRNG_0_TEST_OUT_3_SHIFT (0U) 431 #define SEC_ENG_SE_TRNG_0_TEST_OUT_3_MASK (0xffffffff << SEC_ENG_SE_TRNG_0_TEST_OUT_3_SHIFT) 432 433 /* 0x2FC : se_trng_0_ctrl_prot */ 434 #define SEC_ENG_SE_TRNG_ID0_EN (1 << 1U) 435 #define SEC_ENG_SE_TRNG_ID1_EN (1 << 2U) 436 437 /* 0x300 : se_pka_0_ctrl_0 */ 438 #define SEC_ENG_SE_PKA_0_DONE (1 << 0U) 439 #define SEC_ENG_SE_PKA_0_DONE_CLR_1T (1 << 1U) 440 #define SEC_ENG_SE_PKA_0_BUSY (1 << 2U) 441 #define SEC_ENG_SE_PKA_0_EN (1 << 3U) 442 #define SEC_ENG_SE_PKA_0_PROT_MD_SHIFT (4U) 443 #define SEC_ENG_SE_PKA_0_PROT_MD_MASK (0xf << SEC_ENG_SE_PKA_0_PROT_MD_SHIFT) 444 #define SEC_ENG_SE_PKA_0_INT (1 << 8U) 445 #define SEC_ENG_SE_PKA_0_INT_CLR_1T (1 << 9U) 446 #define SEC_ENG_SE_PKA_0_INT_SET (1 << 10U) 447 #define SEC_ENG_SE_PKA_0_INT_MASK (1 << 11U) 448 #define SEC_ENG_SE_PKA_0_ENDIAN (1 << 12U) 449 #define SEC_ENG_SE_PKA_0_RAM_CLR_MD (1 << 13U) 450 #define SEC_ENG_SE_PKA_0_STATUS_CLR_1T (1 << 15U) 451 #define SEC_ENG_SE_PKA_0_STATUS_SHIFT (16U) 452 #define SEC_ENG_SE_PKA_0_STATUS_MASK (0xffff << SEC_ENG_SE_PKA_0_STATUS_SHIFT) 453 454 /* 0x30C : se_pka_0_seed */ 455 #define SEC_ENG_SE_PKA_0_SEED_SHIFT (0U) 456 #define SEC_ENG_SE_PKA_0_SEED_MASK (0xffffffff << SEC_ENG_SE_PKA_0_SEED_SHIFT) 457 458 /* 0x310 : se_pka_0_ctrl_1 */ 459 #define SEC_ENG_SE_PKA_0_HBURST_SHIFT (0U) 460 #define SEC_ENG_SE_PKA_0_HBURST_MASK (0x7 << SEC_ENG_SE_PKA_0_HBURST_SHIFT) 461 #define SEC_ENG_SE_PKA_0_HBYPASS (1 << 3U) 462 463 /* 0x340 : se_pka_0_rw */ 464 465 /* 0x360 : se_pka_0_rw_burst */ 466 467 /* 0x3FC : se_pka_0_ctrl_prot */ 468 #define SEC_ENG_SE_PKA_ID0_EN (1 << 1U) 469 #define SEC_ENG_SE_PKA_ID1_EN (1 << 2U) 470 471 /* 0x400 : se_cdet_0_ctrl_0 */ 472 #define SEC_ENG_SE_CDET_0_EN (1 << 0U) 473 #define SEC_ENG_SE_CDET_0_BUSY (1 << 1U) 474 #define SEC_ENG_SE_CDET_0_STATUS_SHIFT (3U) 475 #define SEC_ENG_SE_CDET_0_STATUS_MASK (0x1f << SEC_ENG_SE_CDET_0_STATUS_SHIFT) 476 #define SEC_ENG_SE_CDET_0_INT (1 << 8U) 477 #define SEC_ENG_SE_CDET_0_INT_CLR (1 << 9U) 478 #define SEC_ENG_SE_CDET_0_INT_SET (1 << 10U) 479 #define SEC_ENG_SE_CDET_0_INT_MASK (1 << 11U) 480 #define SEC_ENG_SE_CDET_0_MODE (1 << 12U) 481 482 /* 0x404 : se_cdet_0_ctrl_1 */ 483 #define SEC_ENG_SE_CDET_0_G_LOOP_MAX_SHIFT (0U) 484 #define SEC_ENG_SE_CDET_0_G_LOOP_MAX_MASK (0xffff << SEC_ENG_SE_CDET_0_G_LOOP_MAX_SHIFT) 485 #define SEC_ENG_SE_CDET_0_G_LOOP_MIN_SHIFT (16U) 486 #define SEC_ENG_SE_CDET_0_G_LOOP_MIN_MASK (0xffff << SEC_ENG_SE_CDET_0_G_LOOP_MIN_SHIFT) 487 488 /* 0x408 : se_cdet_0_ctrl_2 */ 489 #define SEC_ENG_SE_CDET_0_T_LOOP_N_SHIFT (0U) 490 #define SEC_ENG_SE_CDET_0_T_LOOP_N_MASK (0xffff << SEC_ENG_SE_CDET_0_T_LOOP_N_SHIFT) 491 #define SEC_ENG_SE_CDET_0_T_DLY_N_SHIFT (16U) 492 #define SEC_ENG_SE_CDET_0_T_DLY_N_MASK (0xff << SEC_ENG_SE_CDET_0_T_DLY_N_SHIFT) 493 #define SEC_ENG_SE_CDET_0_G_SLP_N_SHIFT (24U) 494 #define SEC_ENG_SE_CDET_0_G_SLP_N_MASK (0xff << SEC_ENG_SE_CDET_0_G_SLP_N_SHIFT) 495 496 /* 0x40C : se_cdet_0_ctrl_3 */ 497 #define SEC_ENG_SE_CDET_0_T_COUNT_SHIFT (0U) 498 #define SEC_ENG_SE_CDET_0_T_COUNT_MASK (0xffff << SEC_ENG_SE_CDET_0_T_COUNT_SHIFT) 499 #define SEC_ENG_SE_CDET_0_G_COUNT_SHIFT (16U) 500 #define SEC_ENG_SE_CDET_0_G_COUNT_MASK (0xffff << SEC_ENG_SE_CDET_0_G_COUNT_SHIFT) 501 502 /* 0x4FC : se_cdet_0_ctrl_prot */ 503 #define SEC_ENG_SE_CDET_PROT_EN (1 << 0U) 504 #define SEC_ENG_SE_CDET_ID0_EN (1 << 1U) 505 #define SEC_ENG_SE_CDET_ID1_EN (1 << 2U) 506 507 /* 0x500 : se_gmac_0_ctrl_0 */ 508 #define SEC_ENG_SE_GMAC_0_BUSY (1 << 0U) 509 #define SEC_ENG_SE_GMAC_0_TRIG_1T (1 << 1U) 510 #define SEC_ENG_SE_GMAC_0_EN (1 << 2U) 511 #define SEC_ENG_SE_GMAC_0_INT (1 << 8U) 512 #define SEC_ENG_SE_GMAC_0_INT_CLR_1T (1 << 9U) 513 #define SEC_ENG_SE_GMAC_0_INT_SET_1T (1 << 10U) 514 #define SEC_ENG_SE_GMAC_0_INT_MASK (1 << 11U) 515 #define SEC_ENG_SE_GMAC_0_T_ENDIAN (1 << 12U) 516 #define SEC_ENG_SE_GMAC_0_H_ENDIAN (1 << 13U) 517 #define SEC_ENG_SE_GMAC_0_X_ENDIAN (1 << 14U) 518 519 /* 0x504 : se_gmac_0_lca */ 520 #define SEC_ENG_SE_GMAC_0_LCA_SHIFT (0U) 521 #define SEC_ENG_SE_GMAC_0_LCA_MASK (0xffffffff << SEC_ENG_SE_GMAC_0_LCA_SHIFT) 522 523 /* 0x508 : se_gmac_0_status */ 524 #define SEC_ENG_SE_GMAC_0_STATUS_SHIFT (0U) 525 #define SEC_ENG_SE_GMAC_0_STATUS_MASK (0xffffffff << SEC_ENG_SE_GMAC_0_STATUS_SHIFT) 526 527 /* 0x5FC : se_gmac_0_ctrl_prot */ 528 #define SEC_ENG_SE_GMAC_ID0_EN (1 << 1U) 529 #define SEC_ENG_SE_GMAC_ID1_EN (1 << 2U) 530 531 /* 0xF00 : se_ctrl_prot_rd */ 532 #define SEC_ENG_SE_SHA_ID0_EN_RD (1 << 0U) 533 #define SEC_ENG_SE_SHA_ID1_EN_RD (1 << 1U) 534 #define SEC_ENG_SE_AES_ID0_EN_RD (1 << 2U) 535 #define SEC_ENG_SE_AES_ID1_EN_RD (1 << 3U) 536 #define SEC_ENG_SE_TRNG_ID0_EN_RD (1 << 4U) 537 #define SEC_ENG_SE_TRNG_ID1_EN_RD (1 << 5U) 538 #define SEC_ENG_SE_PKA_ID0_EN_RD (1 << 6U) 539 #define SEC_ENG_SE_PKA_ID1_EN_RD (1 << 7U) 540 #define SEC_ENG_SE_CDET_ID0_EN_RD (1 << 8U) 541 #define SEC_ENG_SE_CDET_ID1_EN_RD (1 << 9U) 542 #define SEC_ENG_SE_GMAC_ID0_EN_RD (1 << 10U) 543 #define SEC_ENG_SE_GMAC_ID1_EN_RD (1 << 11U) 544 #define SEC_ENG_SE_DBG_DIS (1 << 31U) 545 546 /* 0xF04 : se_ctrl_reserved_0 */ 547 #define SEC_ENG_SE_CTRL_RESERVED_0_SHIFT (0U) 548 #define SEC_ENG_SE_CTRL_RESERVED_0_MASK (0xffffffff << SEC_ENG_SE_CTRL_RESERVED_0_SHIFT) 549 550 /* 0xF08 : se_ctrl_reserved_1 */ 551 #define SEC_ENG_SE_CTRL_RESERVED_1_SHIFT (0U) 552 #define SEC_ENG_SE_CTRL_RESERVED_1_MASK (0xffffffff << SEC_ENG_SE_CTRL_RESERVED_1_SHIFT) 553 554 /* 0xF0C : se_ctrl_reserved_2 */ 555 #define SEC_ENG_SE_CTRL_RESERVED_2_SHIFT (0U) 556 #define SEC_ENG_SE_CTRL_RESERVED_2_MASK (0xffffffff << SEC_ENG_SE_CTRL_RESERVED_2_SHIFT) 557 558 #endif /* __HARDWARE_SEC_ENG_H__ */ 559