1 /** 2 * \file 3 * 4 * \brief Component description for SERCOM 5 * 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 /* 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 45 */ 46 47 #ifndef _SAMD20_SERCOM_COMPONENT_ 48 #define _SAMD20_SERCOM_COMPONENT_ 49 50 /* ========================================================================== */ 51 /** SOFTWARE API DEFINITION FOR SERCOM */ 52 /* ========================================================================== */ 53 /** \addtogroup SAMD20_SERCOM Serial Communication Interface */ 54 /*@{*/ 55 56 #define SERCOM_U2201 57 #define REV_SERCOM 0x102 58 59 /* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */ 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 61 typedef union { 62 struct { 63 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 64 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 65 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 66 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 67 uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ 68 uint32_t :8; /*!< bit: 8..15 Reserved */ 69 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ 70 uint32_t :3; /*!< bit: 17..19 Reserved */ 71 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ 72 uint32_t :6; /*!< bit: 22..27 Reserved */ 73 uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-out */ 74 uint32_t LOWTOUT:1; /*!< bit: 30 SCL Low Time-out */ 75 uint32_t :1; /*!< bit: 31 Reserved */ 76 } bit; /*!< Structure used for bit access */ 77 uint32_t reg; /*!< Type used for register access */ 78 } SERCOM_I2CM_CTRLA_Type; 79 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 80 81 #define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */ 82 #define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */ 83 84 #define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */ 85 #define SERCOM_I2CM_CTRLA_SWRST (0x1ul << SERCOM_I2CM_CTRLA_SWRST_Pos) 86 #define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */ 87 #define SERCOM_I2CM_CTRLA_ENABLE (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos) 88 #define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */ 89 #define SERCOM_I2CM_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos) 90 #define SERCOM_I2CM_CTRLA_MODE(value) ((SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))) 91 #define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */ 92 #define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */ 93 #define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */ 94 #define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */ 95 #define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */ 96 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */ 97 #define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 98 #define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 99 #define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 100 #define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 101 #define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 102 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 103 #define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */ 104 #define SERCOM_I2CM_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) 105 #define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */ 106 #define SERCOM_I2CM_CTRLA_PINOUT (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos) 107 #define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */ 108 #define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) 109 #define SERCOM_I2CM_CTRLA_SDAHOLD(value) ((SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))) 110 #define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-out */ 111 #define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos) 112 #define SERCOM_I2CM_CTRLA_INACTOUT(value) ((SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))) 113 #define SERCOM_I2CM_CTRLA_LOWTOUT_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Time-out */ 114 #define SERCOM_I2CM_CTRLA_LOWTOUT (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUT_Pos) 115 #define SERCOM_I2CM_CTRLA_MASK 0x7031009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */ 116 117 /* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */ 118 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 119 typedef union { 120 struct { 121 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 122 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 123 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 124 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 125 uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ 126 uint32_t :8; /*!< bit: 8..15 Reserved */ 127 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ 128 uint32_t :3; /*!< bit: 17..19 Reserved */ 129 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ 130 uint32_t :8; /*!< bit: 22..29 Reserved */ 131 uint32_t LOWTOUT:1; /*!< bit: 30 SCL Low Time-out */ 132 uint32_t :1; /*!< bit: 31 Reserved */ 133 } bit; /*!< Structure used for bit access */ 134 uint32_t reg; /*!< Type used for register access */ 135 } SERCOM_I2CS_CTRLA_Type; 136 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 137 138 #define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */ 139 #define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */ 140 141 #define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */ 142 #define SERCOM_I2CS_CTRLA_SWRST (0x1ul << SERCOM_I2CS_CTRLA_SWRST_Pos) 143 #define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */ 144 #define SERCOM_I2CS_CTRLA_ENABLE (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos) 145 #define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */ 146 #define SERCOM_I2CS_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos) 147 #define SERCOM_I2CS_CTRLA_MODE(value) ((SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))) 148 #define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */ 149 #define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */ 150 #define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */ 151 #define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */ 152 #define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */ 153 #define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */ 154 #define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 155 #define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 156 #define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 157 #define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 158 #define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 159 #define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 160 #define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run in Standby */ 161 #define SERCOM_I2CS_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) 162 #define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */ 163 #define SERCOM_I2CS_CTRLA_PINOUT (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos) 164 #define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */ 165 #define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) 166 #define SERCOM_I2CS_CTRLA_SDAHOLD(value) ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))) 167 #define SERCOM_I2CS_CTRLA_SDAHOLD_DIS_Val 0x0ul /**< \brief (SERCOM_I2CS_CTRLA) Disabled */ 168 #define SERCOM_I2CS_CTRLA_SDAHOLD_75_Val 0x1ul /**< \brief (SERCOM_I2CS_CTRLA) 50-100 ns hold time */ 169 #define SERCOM_I2CS_CTRLA_SDAHOLD_450_Val 0x2ul /**< \brief (SERCOM_I2CS_CTRLA) 300-600 ns hold time */ 170 #define SERCOM_I2CS_CTRLA_SDAHOLD_600_Val 0x3ul /**< \brief (SERCOM_I2CS_CTRLA) 400-800 ns hold time */ 171 #define SERCOM_I2CS_CTRLA_SDAHOLD_DIS (SERCOM_I2CS_CTRLA_SDAHOLD_DIS_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) 172 #define SERCOM_I2CS_CTRLA_SDAHOLD_75 (SERCOM_I2CS_CTRLA_SDAHOLD_75_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) 173 #define SERCOM_I2CS_CTRLA_SDAHOLD_450 (SERCOM_I2CS_CTRLA_SDAHOLD_450_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) 174 #define SERCOM_I2CS_CTRLA_SDAHOLD_600 (SERCOM_I2CS_CTRLA_SDAHOLD_600_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) 175 #define SERCOM_I2CS_CTRLA_LOWTOUT_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Time-out */ 176 #define SERCOM_I2CS_CTRLA_LOWTOUT (0x1ul << SERCOM_I2CS_CTRLA_LOWTOUT_Pos) 177 #define SERCOM_I2CS_CTRLA_MASK 0x4031009Ful /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */ 178 179 /* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */ 180 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 181 typedef union { 182 struct { 183 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 184 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 185 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 186 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 187 uint32_t RUNSTDBY:1; /*!< bit: 7 Run In Standby */ 188 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ 189 uint32_t :7; /*!< bit: 9..15 Reserved */ 190 uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */ 191 uint32_t :2; /*!< bit: 18..19 Reserved */ 192 uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */ 193 uint32_t :2; /*!< bit: 22..23 Reserved */ 194 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ 195 uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ 196 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ 197 uint32_t DORD:1; /*!< bit: 30 Data Order */ 198 uint32_t :1; /*!< bit: 31 Reserved */ 199 } bit; /*!< Structure used for bit access */ 200 uint32_t reg; /*!< Type used for register access */ 201 } SERCOM_SPI_CTRLA_Type; 202 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 203 204 #define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */ 205 #define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */ 206 207 #define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */ 208 #define SERCOM_SPI_CTRLA_SWRST (0x1ul << SERCOM_SPI_CTRLA_SWRST_Pos) 209 #define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */ 210 #define SERCOM_SPI_CTRLA_ENABLE (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos) 211 #define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */ 212 #define SERCOM_SPI_CTRLA_MODE_Msk (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos) 213 #define SERCOM_SPI_CTRLA_MODE(value) ((SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))) 214 #define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */ 215 #define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */ 216 #define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */ 217 #define SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */ 218 #define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */ 219 #define SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */ 220 #define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos) 221 #define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos) 222 #define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos) 223 #define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos) 224 #define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos) 225 #define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos) 226 #define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run In Standby */ 227 #define SERCOM_SPI_CTRLA_RUNSTDBY (0x1ul << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) 228 #define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */ 229 #define SERCOM_SPI_CTRLA_IBON (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos) 230 #define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */ 231 #define SERCOM_SPI_CTRLA_DOPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos) 232 #define SERCOM_SPI_CTRLA_DOPO(value) ((SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))) 233 #define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */ 234 #define SERCOM_SPI_CTRLA_DIPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos) 235 #define SERCOM_SPI_CTRLA_DIPO(value) ((SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))) 236 #define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */ 237 #define SERCOM_SPI_CTRLA_FORM_Msk (0xFul << SERCOM_SPI_CTRLA_FORM_Pos) 238 #define SERCOM_SPI_CTRLA_FORM(value) ((SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))) 239 #define SERCOM_SPI_CTRLA_FORM_SPI_Val 0x0ul /**< \brief (SERCOM_SPI_CTRLA) SPI frame */ 240 #define SERCOM_SPI_CTRLA_FORM_SPI_ADDR_Val 0x2ul /**< \brief (SERCOM_SPI_CTRLA) SPI frame with address */ 241 #define SERCOM_SPI_CTRLA_FORM_SPI (SERCOM_SPI_CTRLA_FORM_SPI_Val << SERCOM_SPI_CTRLA_FORM_Pos) 242 #define SERCOM_SPI_CTRLA_FORM_SPI_ADDR (SERCOM_SPI_CTRLA_FORM_SPI_ADDR_Val << SERCOM_SPI_CTRLA_FORM_Pos) 243 #define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */ 244 #define SERCOM_SPI_CTRLA_CPHA (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos) 245 #define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */ 246 #define SERCOM_SPI_CTRLA_CPOL (0x1ul << SERCOM_SPI_CTRLA_CPOL_Pos) 247 #define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */ 248 #define SERCOM_SPI_CTRLA_DORD (0x1ul << SERCOM_SPI_CTRLA_DORD_Pos) 249 #define SERCOM_SPI_CTRLA_MASK 0x7F33019Ful /**< \brief (SERCOM_SPI_CTRLA) MASK Register */ 250 251 /* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */ 252 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 253 typedef union { 254 struct { 255 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 256 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 257 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 258 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 259 uint32_t RUNSTDBY:1; /*!< bit: 7 Run In Standby */ 260 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ 261 uint32_t :7; /*!< bit: 9..15 Reserved */ 262 uint32_t TXPO:1; /*!< bit: 16 Transmit Data Pinout */ 263 uint32_t :3; /*!< bit: 17..19 Reserved */ 264 uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */ 265 uint32_t :2; /*!< bit: 22..23 Reserved */ 266 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ 267 uint32_t CMODE:1; /*!< bit: 28 Communication Mode */ 268 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ 269 uint32_t DORD:1; /*!< bit: 30 Data Order */ 270 uint32_t :1; /*!< bit: 31 Reserved */ 271 } bit; /*!< Structure used for bit access */ 272 uint32_t reg; /*!< Type used for register access */ 273 } SERCOM_USART_CTRLA_Type; 274 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 275 276 #define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */ 277 #define SERCOM_USART_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */ 278 279 #define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */ 280 #define SERCOM_USART_CTRLA_SWRST (0x1ul << SERCOM_USART_CTRLA_SWRST_Pos) 281 #define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */ 282 #define SERCOM_USART_CTRLA_ENABLE (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos) 283 #define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */ 284 #define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos) 285 #define SERCOM_USART_CTRLA_MODE(value) ((SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))) 286 #define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */ 287 #define SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */ 288 #define SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */ 289 #define SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */ 290 #define SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */ 291 #define SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */ 292 #define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos) 293 #define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos) 294 #define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos) 295 #define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos) 296 #define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos) 297 #define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos) 298 #define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run In Standby */ 299 #define SERCOM_USART_CTRLA_RUNSTDBY (0x1ul << SERCOM_USART_CTRLA_RUNSTDBY_Pos) 300 #define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */ 301 #define SERCOM_USART_CTRLA_IBON (0x1ul << SERCOM_USART_CTRLA_IBON_Pos) 302 #define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */ 303 #define SERCOM_USART_CTRLA_TXPO (0x1ul << SERCOM_USART_CTRLA_TXPO_Pos) 304 #define SERCOM_USART_CTRLA_TXPO_PAD0_Val 0x0ul /**< \brief (SERCOM_USART_CTRLA) TXD at PAD0, XCK at PAD1 */ 305 #define SERCOM_USART_CTRLA_TXPO_PAD2_Val 0x1ul /**< \brief (SERCOM_USART_CTRLA) TXD at PAD2, XCK at PAD3 */ 306 #define SERCOM_USART_CTRLA_TXPO_PAD0 (SERCOM_USART_CTRLA_TXPO_PAD0_Val << SERCOM_USART_CTRLA_TXPO_Pos) 307 #define SERCOM_USART_CTRLA_TXPO_PAD2 (SERCOM_USART_CTRLA_TXPO_PAD2_Val << SERCOM_USART_CTRLA_TXPO_Pos) 308 #define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */ 309 #define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos) 310 #define SERCOM_USART_CTRLA_RXPO(value) ((SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))) 311 #define SERCOM_USART_CTRLA_RXPO_PAD0_Val 0x0ul /**< \brief (SERCOM_USART_CTRLA) SERCOM_PAD0 */ 312 #define SERCOM_USART_CTRLA_RXPO_PAD1_Val 0x1ul /**< \brief (SERCOM_USART_CTRLA) SERCOM_PAD1 */ 313 #define SERCOM_USART_CTRLA_RXPO_PAD2_Val 0x2ul /**< \brief (SERCOM_USART_CTRLA) SERCOM_PAD2 */ 314 #define SERCOM_USART_CTRLA_RXPO_PAD3_Val 0x3ul /**< \brief (SERCOM_USART_CTRLA) SERCOM_PAD3 */ 315 #define SERCOM_USART_CTRLA_RXPO_PAD0 (SERCOM_USART_CTRLA_RXPO_PAD0_Val << SERCOM_USART_CTRLA_RXPO_Pos) 316 #define SERCOM_USART_CTRLA_RXPO_PAD1 (SERCOM_USART_CTRLA_RXPO_PAD1_Val << SERCOM_USART_CTRLA_RXPO_Pos) 317 #define SERCOM_USART_CTRLA_RXPO_PAD2 (SERCOM_USART_CTRLA_RXPO_PAD2_Val << SERCOM_USART_CTRLA_RXPO_Pos) 318 #define SERCOM_USART_CTRLA_RXPO_PAD3 (SERCOM_USART_CTRLA_RXPO_PAD3_Val << SERCOM_USART_CTRLA_RXPO_Pos) 319 #define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */ 320 #define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos) 321 #define SERCOM_USART_CTRLA_FORM(value) ((SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))) 322 #define SERCOM_USART_CTRLA_FORM_0_Val 0x0ul /**< \brief (SERCOM_USART_CTRLA) USART frame */ 323 #define SERCOM_USART_CTRLA_FORM_1_Val 0x1ul /**< \brief (SERCOM_USART_CTRLA) USART frame with parity */ 324 #define SERCOM_USART_CTRLA_FORM_0 (SERCOM_USART_CTRLA_FORM_0_Val << SERCOM_USART_CTRLA_FORM_Pos) 325 #define SERCOM_USART_CTRLA_FORM_1 (SERCOM_USART_CTRLA_FORM_1_Val << SERCOM_USART_CTRLA_FORM_Pos) 326 #define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */ 327 #define SERCOM_USART_CTRLA_CMODE (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos) 328 #define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */ 329 #define SERCOM_USART_CTRLA_CPOL (0x1ul << SERCOM_USART_CTRLA_CPOL_Pos) 330 #define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */ 331 #define SERCOM_USART_CTRLA_DORD (0x1ul << SERCOM_USART_CTRLA_DORD_Pos) 332 #define SERCOM_USART_CTRLA_MASK 0x7F31019Ful /**< \brief (SERCOM_USART_CTRLA) MASK Register */ 333 334 /* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */ 335 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 336 typedef union { 337 struct { 338 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 339 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ 340 uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */ 341 uint32_t :6; /*!< bit: 10..15 Reserved */ 342 uint32_t CMD:2; /*!< bit: 16..17 Command */ 343 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ 344 uint32_t :13; /*!< bit: 19..31 Reserved */ 345 } bit; /*!< Structure used for bit access */ 346 uint32_t reg; /*!< Type used for register access */ 347 } SERCOM_I2CM_CTRLB_Type; 348 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 349 350 #define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */ 351 #define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */ 352 353 #define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */ 354 #define SERCOM_I2CM_CTRLB_SMEN (0x1ul << SERCOM_I2CM_CTRLB_SMEN_Pos) 355 #define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */ 356 #define SERCOM_I2CM_CTRLB_QCEN (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos) 357 #define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */ 358 #define SERCOM_I2CM_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos) 359 #define SERCOM_I2CM_CTRLB_CMD(value) ((SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))) 360 #define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */ 361 #define SERCOM_I2CM_CTRLB_ACKACT (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos) 362 #define SERCOM_I2CM_CTRLB_MASK 0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */ 363 364 /* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */ 365 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 366 typedef union { 367 struct { 368 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 369 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ 370 uint32_t :5; /*!< bit: 9..13 Reserved */ 371 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ 372 uint32_t CMD:2; /*!< bit: 16..17 Command */ 373 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ 374 uint32_t :13; /*!< bit: 19..31 Reserved */ 375 } bit; /*!< Structure used for bit access */ 376 uint32_t reg; /*!< Type used for register access */ 377 } SERCOM_I2CS_CTRLB_Type; 378 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 379 380 #define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */ 381 #define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */ 382 383 #define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */ 384 #define SERCOM_I2CS_CTRLB_SMEN (0x1ul << SERCOM_I2CS_CTRLB_SMEN_Pos) 385 #define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */ 386 #define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos) 387 #define SERCOM_I2CS_CTRLB_AMODE(value) ((SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))) 388 #define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */ 389 #define SERCOM_I2CS_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos) 390 #define SERCOM_I2CS_CTRLB_CMD(value) ((SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))) 391 #define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */ 392 #define SERCOM_I2CS_CTRLB_ACKACT (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos) 393 #define SERCOM_I2CS_CTRLB_MASK 0x0007C100ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */ 394 395 /* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */ 396 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 397 typedef union { 398 struct { 399 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ 400 uint32_t :3; /*!< bit: 3.. 5 Reserved */ 401 uint32_t PLOADEN:1; /*!< bit: 6 Slave Data Preload Enable */ 402 uint32_t :7; /*!< bit: 7..13 Reserved */ 403 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ 404 uint32_t :1; /*!< bit: 16 Reserved */ 405 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ 406 uint32_t :14; /*!< bit: 18..31 Reserved */ 407 } bit; /*!< Structure used for bit access */ 408 uint32_t reg; /*!< Type used for register access */ 409 } SERCOM_SPI_CTRLB_Type; 410 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 411 412 #define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */ 413 #define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */ 414 415 #define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */ 416 #define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos) 417 #define SERCOM_SPI_CTRLB_CHSIZE(value) ((SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))) 418 #define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Slave Data Preload Enable */ 419 #define SERCOM_SPI_CTRLB_PLOADEN (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos) 420 #define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */ 421 #define SERCOM_SPI_CTRLB_AMODE_Msk (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos) 422 #define SERCOM_SPI_CTRLB_AMODE(value) ((SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))) 423 #define SERCOM_SPI_CTRLB_AMODE_MASK_Val 0x0ul /**< \brief (SERCOM_SPI_CTRLB) ADDRMASK is used as a mask to the ADDR register. */ 424 #define SERCOM_SPI_CTRLB_AMODE_2ADDR_Val 0x1ul /**< \brief (SERCOM_SPI_CTRLB) The slave responds to the 2 unique addresses in ADDR and ADDRMASK. */ 425 #define SERCOM_SPI_CTRLB_AMODE_RANGE_Val 0x2ul /**< \brief (SERCOM_SPI_CTRLB) The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit. */ 426 #define SERCOM_SPI_CTRLB_AMODE_MASK (SERCOM_SPI_CTRLB_AMODE_MASK_Val << SERCOM_SPI_CTRLB_AMODE_Pos) 427 #define SERCOM_SPI_CTRLB_AMODE_2ADDR (SERCOM_SPI_CTRLB_AMODE_2ADDR_Val << SERCOM_SPI_CTRLB_AMODE_Pos) 428 #define SERCOM_SPI_CTRLB_AMODE_RANGE (SERCOM_SPI_CTRLB_AMODE_RANGE_Val << SERCOM_SPI_CTRLB_AMODE_Pos) 429 #define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */ 430 #define SERCOM_SPI_CTRLB_RXEN (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos) 431 #define SERCOM_SPI_CTRLB_MASK 0x0002C047ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */ 432 433 /* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */ 434 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 435 typedef union { 436 struct { 437 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ 438 uint32_t :3; /*!< bit: 3.. 5 Reserved */ 439 uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */ 440 uint32_t :2; /*!< bit: 7.. 8 Reserved */ 441 uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */ 442 uint32_t :3; /*!< bit: 10..12 Reserved */ 443 uint32_t PMODE:1; /*!< bit: 13 Parity Mode */ 444 uint32_t :2; /*!< bit: 14..15 Reserved */ 445 uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */ 446 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ 447 uint32_t :14; /*!< bit: 18..31 Reserved */ 448 } bit; /*!< Structure used for bit access */ 449 uint32_t reg; /*!< Type used for register access */ 450 } SERCOM_USART_CTRLB_Type; 451 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 452 453 #define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */ 454 #define SERCOM_USART_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */ 455 456 #define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */ 457 #define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos) 458 #define SERCOM_USART_CTRLB_CHSIZE(value) ((SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))) 459 #define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */ 460 #define SERCOM_USART_CTRLB_SBMODE (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos) 461 #define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */ 462 #define SERCOM_USART_CTRLB_SFDE (0x1ul << SERCOM_USART_CTRLB_SFDE_Pos) 463 #define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */ 464 #define SERCOM_USART_CTRLB_PMODE (0x1ul << SERCOM_USART_CTRLB_PMODE_Pos) 465 #define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */ 466 #define SERCOM_USART_CTRLB_TXEN (0x1ul << SERCOM_USART_CTRLB_TXEN_Pos) 467 #define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */ 468 #define SERCOM_USART_CTRLB_RXEN (0x1ul << SERCOM_USART_CTRLB_RXEN_Pos) 469 #define SERCOM_USART_CTRLB_MASK 0x00032247ul /**< \brief (SERCOM_USART_CTRLB) MASK Register */ 470 471 /* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x08) (R/W 8) I2CM I2CM Debug Control -------- */ 472 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 473 typedef union { 474 struct { 475 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Stop Mode */ 476 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 477 } bit; /*!< Structure used for bit access */ 478 uint8_t reg; /*!< Type used for register access */ 479 } SERCOM_I2CM_DBGCTRL_Type; 480 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 481 482 #define SERCOM_I2CM_DBGCTRL_OFFSET 0x08 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */ 483 #define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */ 484 485 #define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Stop Mode */ 486 #define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1ul << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos) 487 #define SERCOM_I2CM_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */ 488 489 /* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x08) (R/W 8) SPI SPI Debug Control -------- */ 490 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 491 typedef union { 492 struct { 493 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Stop Mode */ 494 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 495 } bit; /*!< Structure used for bit access */ 496 uint8_t reg; /*!< Type used for register access */ 497 } SERCOM_SPI_DBGCTRL_Type; 498 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 499 500 #define SERCOM_SPI_DBGCTRL_OFFSET 0x08 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */ 501 #define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */ 502 503 #define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Stop Mode */ 504 #define SERCOM_SPI_DBGCTRL_DBGSTOP (0x1ul << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos) 505 #define SERCOM_SPI_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */ 506 507 /* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x08) (R/W 8) USART USART Debug Control -------- */ 508 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 509 typedef union { 510 struct { 511 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Stop Mode */ 512 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 513 } bit; /*!< Structure used for bit access */ 514 uint8_t reg; /*!< Type used for register access */ 515 } SERCOM_USART_DBGCTRL_Type; 516 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 517 518 #define SERCOM_USART_DBGCTRL_OFFSET 0x08 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */ 519 #define SERCOM_USART_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */ 520 521 #define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Stop Mode */ 522 #define SERCOM_USART_DBGCTRL_DBGSTOP (0x1ul << SERCOM_USART_DBGCTRL_DBGSTOP_Pos) 523 #define SERCOM_USART_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */ 524 525 /* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0A) (R/W 16) I2CM I2CM Baud Rate -------- */ 526 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 527 typedef union { 528 struct { 529 uint16_t BAUD:8; /*!< bit: 0.. 7 Master Baud Rate */ 530 uint16_t BAUDLOW:8; /*!< bit: 8..15 Master Baud Rate Low */ 531 } bit; /*!< Structure used for bit access */ 532 uint16_t reg; /*!< Type used for register access */ 533 } SERCOM_I2CM_BAUD_Type; 534 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 535 536 #define SERCOM_I2CM_BAUD_OFFSET 0x0A /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */ 537 #define SERCOM_I2CM_BAUD_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */ 538 539 #define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Master Baud Rate */ 540 #define SERCOM_I2CM_BAUD_BAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos) 541 #define SERCOM_I2CM_BAUD_BAUD(value) ((SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))) 542 #define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Master Baud Rate Low */ 543 #define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos) 544 #define SERCOM_I2CM_BAUD_BAUDLOW(value) ((SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))) 545 #define SERCOM_I2CM_BAUD_MASK 0xFFFFul /**< \brief (SERCOM_I2CM_BAUD) MASK Register */ 546 547 /* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0A) (R/W 8) SPI SPI Baud Rate -------- */ 548 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 549 typedef union { 550 struct { 551 uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Register */ 552 } bit; /*!< Structure used for bit access */ 553 uint8_t reg; /*!< Type used for register access */ 554 } SERCOM_SPI_BAUD_Type; 555 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 556 557 #define SERCOM_SPI_BAUD_OFFSET 0x0A /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */ 558 #define SERCOM_SPI_BAUD_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */ 559 560 #define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Register */ 561 #define SERCOM_SPI_BAUD_BAUD_Msk (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos) 562 #define SERCOM_SPI_BAUD_BAUD(value) ((SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))) 563 #define SERCOM_SPI_BAUD_MASK 0xFFul /**< \brief (SERCOM_SPI_BAUD) MASK Register */ 564 565 /* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0A) (R/W 16) USART USART Baud -------- */ 566 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 567 typedef union { 568 struct { 569 uint16_t BAUD:16; /*!< bit: 0..15 Baud Value */ 570 } bit; /*!< Structure used for bit access */ 571 uint16_t reg; /*!< Type used for register access */ 572 } SERCOM_USART_BAUD_Type; 573 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 574 575 #define SERCOM_USART_BAUD_OFFSET 0x0A /**< \brief (SERCOM_USART_BAUD offset) USART Baud */ 576 #define SERCOM_USART_BAUD_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud */ 577 578 #define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Value */ 579 #define SERCOM_USART_BAUD_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos) 580 #define SERCOM_USART_BAUD_BAUD(value) ((SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))) 581 #define SERCOM_USART_BAUD_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD) MASK Register */ 582 583 /* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x0C) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */ 584 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 585 typedef union { 586 struct { 587 uint8_t MB:1; /*!< bit: 0 Master on Bus Interrupt Enable */ 588 uint8_t SB:1; /*!< bit: 1 Slave on Bus Interrupt Enable */ 589 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 590 } bit; /*!< Structure used for bit access */ 591 uint8_t reg; /*!< Type used for register access */ 592 } SERCOM_I2CM_INTENCLR_Type; 593 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 594 595 #define SERCOM_I2CM_INTENCLR_OFFSET 0x0C /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */ 596 #define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */ 597 598 #define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master on Bus Interrupt Enable */ 599 #define SERCOM_I2CM_INTENCLR_MB (0x1ul << SERCOM_I2CM_INTENCLR_MB_Pos) 600 #define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave on Bus Interrupt Enable */ 601 #define SERCOM_I2CM_INTENCLR_SB (0x1ul << SERCOM_I2CM_INTENCLR_SB_Pos) 602 #define SERCOM_I2CM_INTENCLR_MASK 0x03ul /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */ 603 604 /* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x0C) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */ 605 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 606 typedef union { 607 struct { 608 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ 609 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ 610 uint8_t DRDY:1; /*!< bit: 2 Data Ready Interrupt Enable */ 611 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 612 } bit; /*!< Structure used for bit access */ 613 uint8_t reg; /*!< Type used for register access */ 614 } SERCOM_I2CS_INTENCLR_Type; 615 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 616 617 #define SERCOM_I2CS_INTENCLR_OFFSET 0x0C /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */ 618 #define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */ 619 620 #define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Enable */ 621 #define SERCOM_I2CS_INTENCLR_PREC (0x1ul << SERCOM_I2CS_INTENCLR_PREC_Pos) 622 #define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Enable */ 623 #define SERCOM_I2CS_INTENCLR_AMATCH (0x1ul << SERCOM_I2CS_INTENCLR_AMATCH_Pos) 624 #define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Ready Interrupt Enable */ 625 #define SERCOM_I2CS_INTENCLR_DRDY (0x1ul << SERCOM_I2CS_INTENCLR_DRDY_Pos) 626 #define SERCOM_I2CS_INTENCLR_MASK 0x07ul /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */ 627 628 /* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Interrupt Enable Clear -------- */ 629 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 630 typedef union { 631 struct { 632 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ 633 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ 634 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ 635 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 636 } bit; /*!< Structure used for bit access */ 637 uint8_t reg; /*!< Type used for register access */ 638 } SERCOM_SPI_INTENCLR_Type; 639 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 640 641 #define SERCOM_SPI_INTENCLR_OFFSET 0x0C /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */ 642 #define SERCOM_SPI_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */ 643 644 #define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Enable */ 645 #define SERCOM_SPI_INTENCLR_DRE (0x1ul << SERCOM_SPI_INTENCLR_DRE_Pos) 646 #define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Enable */ 647 #define SERCOM_SPI_INTENCLR_TXC (0x1ul << SERCOM_SPI_INTENCLR_TXC_Pos) 648 #define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Enable */ 649 #define SERCOM_SPI_INTENCLR_RXC (0x1ul << SERCOM_SPI_INTENCLR_RXC_Pos) 650 #define SERCOM_SPI_INTENCLR_MASK 0x07ul /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */ 651 652 /* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x0C) (R/W 8) USART USART Interrupt Enable Clear -------- */ 653 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 654 typedef union { 655 struct { 656 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ 657 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ 658 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ 659 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */ 660 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 661 } bit; /*!< Structure used for bit access */ 662 uint8_t reg; /*!< Type used for register access */ 663 } SERCOM_USART_INTENCLR_Type; 664 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 665 666 #define SERCOM_USART_INTENCLR_OFFSET 0x0C /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */ 667 #define SERCOM_USART_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */ 668 669 #define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Enable */ 670 #define SERCOM_USART_INTENCLR_DRE (0x1ul << SERCOM_USART_INTENCLR_DRE_Pos) 671 #define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Enable */ 672 #define SERCOM_USART_INTENCLR_TXC (0x1ul << SERCOM_USART_INTENCLR_TXC_Pos) 673 #define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Enable */ 674 #define SERCOM_USART_INTENCLR_RXC (0x1ul << SERCOM_USART_INTENCLR_RXC_Pos) 675 #define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */ 676 #define SERCOM_USART_INTENCLR_RXS (0x1ul << SERCOM_USART_INTENCLR_RXS_Pos) 677 #define SERCOM_USART_INTENCLR_MASK 0x0Ful /**< \brief (SERCOM_USART_INTENCLR) MASK Register */ 678 679 /* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x0D) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */ 680 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 681 typedef union { 682 struct { 683 uint8_t MB:1; /*!< bit: 0 Master on Bus Interrupt Enable */ 684 uint8_t SB:1; /*!< bit: 1 Slave on Bus Interrupt Enable */ 685 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 686 } bit; /*!< Structure used for bit access */ 687 uint8_t reg; /*!< Type used for register access */ 688 } SERCOM_I2CM_INTENSET_Type; 689 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 690 691 #define SERCOM_I2CM_INTENSET_OFFSET 0x0D /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */ 692 #define SERCOM_I2CM_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */ 693 694 #define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master on Bus Interrupt Enable */ 695 #define SERCOM_I2CM_INTENSET_MB (0x1ul << SERCOM_I2CM_INTENSET_MB_Pos) 696 #define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave on Bus Interrupt Enable */ 697 #define SERCOM_I2CM_INTENSET_SB (0x1ul << SERCOM_I2CM_INTENSET_SB_Pos) 698 #define SERCOM_I2CM_INTENSET_MASK 0x03ul /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */ 699 700 /* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x0D) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */ 701 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 702 typedef union { 703 struct { 704 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ 705 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ 706 uint8_t DRDY:1; /*!< bit: 2 Data Ready Interrupt Enable */ 707 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 708 } bit; /*!< Structure used for bit access */ 709 uint8_t reg; /*!< Type used for register access */ 710 } SERCOM_I2CS_INTENSET_Type; 711 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 712 713 #define SERCOM_I2CS_INTENSET_OFFSET 0x0D /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */ 714 #define SERCOM_I2CS_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */ 715 716 #define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */ 717 #define SERCOM_I2CS_INTENSET_PREC (0x1ul << SERCOM_I2CS_INTENSET_PREC_Pos) 718 #define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */ 719 #define SERCOM_I2CS_INTENSET_AMATCH (0x1ul << SERCOM_I2CS_INTENSET_AMATCH_Pos) 720 #define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Ready Interrupt Enable */ 721 #define SERCOM_I2CS_INTENSET_DRDY (0x1ul << SERCOM_I2CS_INTENSET_DRDY_Pos) 722 #define SERCOM_I2CS_INTENSET_MASK 0x07ul /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */ 723 724 /* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x0D) (R/W 8) SPI SPI Interrupt Enable Set -------- */ 725 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 726 typedef union { 727 struct { 728 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ 729 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ 730 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ 731 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 732 } bit; /*!< Structure used for bit access */ 733 uint8_t reg; /*!< Type used for register access */ 734 } SERCOM_SPI_INTENSET_Type; 735 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 736 737 #define SERCOM_SPI_INTENSET_OFFSET 0x0D /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */ 738 #define SERCOM_SPI_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */ 739 740 #define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */ 741 #define SERCOM_SPI_INTENSET_DRE (0x1ul << SERCOM_SPI_INTENSET_DRE_Pos) 742 #define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */ 743 #define SERCOM_SPI_INTENSET_TXC (0x1ul << SERCOM_SPI_INTENSET_TXC_Pos) 744 #define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */ 745 #define SERCOM_SPI_INTENSET_RXC (0x1ul << SERCOM_SPI_INTENSET_RXC_Pos) 746 #define SERCOM_SPI_INTENSET_MASK 0x07ul /**< \brief (SERCOM_SPI_INTENSET) MASK Register */ 747 748 /* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x0D) (R/W 8) USART USART Interrupt Enable Set -------- */ 749 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 750 typedef union { 751 struct { 752 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ 753 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ 754 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ 755 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */ 756 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 757 } bit; /*!< Structure used for bit access */ 758 uint8_t reg; /*!< Type used for register access */ 759 } SERCOM_USART_INTENSET_Type; 760 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 761 762 #define SERCOM_USART_INTENSET_OFFSET 0x0D /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */ 763 #define SERCOM_USART_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */ 764 765 #define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */ 766 #define SERCOM_USART_INTENSET_DRE (0x1ul << SERCOM_USART_INTENSET_DRE_Pos) 767 #define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */ 768 #define SERCOM_USART_INTENSET_TXC (0x1ul << SERCOM_USART_INTENSET_TXC_Pos) 769 #define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */ 770 #define SERCOM_USART_INTENSET_RXC (0x1ul << SERCOM_USART_INTENSET_RXC_Pos) 771 #define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */ 772 #define SERCOM_USART_INTENSET_RXS (0x1ul << SERCOM_USART_INTENSET_RXS_Pos) 773 #define SERCOM_USART_INTENSET_MASK 0x0Ful /**< \brief (SERCOM_USART_INTENSET) MASK Register */ 774 775 /* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x0E) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */ 776 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 777 typedef union { 778 struct { 779 uint8_t MB:1; /*!< bit: 0 Master on Bus */ 780 uint8_t SB:1; /*!< bit: 1 Slave on Bus */ 781 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 782 } bit; /*!< Structure used for bit access */ 783 uint8_t reg; /*!< Type used for register access */ 784 } SERCOM_I2CM_INTFLAG_Type; 785 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 786 787 #define SERCOM_I2CM_INTFLAG_OFFSET 0x0E /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */ 788 #define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */ 789 790 #define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master on Bus */ 791 #define SERCOM_I2CM_INTFLAG_MB (0x1ul << SERCOM_I2CM_INTFLAG_MB_Pos) 792 #define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave on Bus */ 793 #define SERCOM_I2CM_INTFLAG_SB (0x1ul << SERCOM_I2CM_INTFLAG_SB_Pos) 794 #define SERCOM_I2CM_INTFLAG_MASK 0x03ul /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */ 795 796 /* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x0E) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */ 797 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 798 typedef union { 799 struct { 800 uint8_t PREC:1; /*!< bit: 0 Stop Received */ 801 uint8_t AMATCH:1; /*!< bit: 1 Address Match */ 802 uint8_t DRDY:1; /*!< bit: 2 Data Ready */ 803 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 804 } bit; /*!< Structure used for bit access */ 805 uint8_t reg; /*!< Type used for register access */ 806 } SERCOM_I2CS_INTFLAG_Type; 807 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 808 809 #define SERCOM_I2CS_INTFLAG_OFFSET 0x0E /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */ 810 #define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */ 811 812 #define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received */ 813 #define SERCOM_I2CS_INTFLAG_PREC (0x1ul << SERCOM_I2CS_INTFLAG_PREC_Pos) 814 #define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match */ 815 #define SERCOM_I2CS_INTFLAG_AMATCH (0x1ul << SERCOM_I2CS_INTFLAG_AMATCH_Pos) 816 #define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Ready */ 817 #define SERCOM_I2CS_INTFLAG_DRDY (0x1ul << SERCOM_I2CS_INTFLAG_DRDY_Pos) 818 #define SERCOM_I2CS_INTFLAG_MASK 0x07ul /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */ 819 820 /* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x0E) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */ 821 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 822 typedef union { 823 struct { 824 uint8_t DRE:1; /*!< bit: 0 Data Register Empty */ 825 uint8_t TXC:1; /*!< bit: 1 Transmit Complete */ 826 uint8_t RXC:1; /*!< bit: 2 Receive Complete */ 827 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 828 } bit; /*!< Structure used for bit access */ 829 uint8_t reg; /*!< Type used for register access */ 830 } SERCOM_SPI_INTFLAG_Type; 831 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 832 833 #define SERCOM_SPI_INTFLAG_OFFSET 0x0E /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */ 834 #define SERCOM_SPI_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */ 835 836 #define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty */ 837 #define SERCOM_SPI_INTFLAG_DRE (0x1ul << SERCOM_SPI_INTFLAG_DRE_Pos) 838 #define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete */ 839 #define SERCOM_SPI_INTFLAG_TXC (0x1ul << SERCOM_SPI_INTFLAG_TXC_Pos) 840 #define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete */ 841 #define SERCOM_SPI_INTFLAG_RXC (0x1ul << SERCOM_SPI_INTFLAG_RXC_Pos) 842 #define SERCOM_SPI_INTFLAG_MASK 0x07ul /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */ 843 844 /* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x0E) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */ 845 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 846 typedef union { 847 struct { 848 uint8_t DRE:1; /*!< bit: 0 Data Register Empty */ 849 uint8_t TXC:1; /*!< bit: 1 Transmit Complete */ 850 uint8_t RXC:1; /*!< bit: 2 Receive Complete */ 851 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */ 852 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 853 } bit; /*!< Structure used for bit access */ 854 uint8_t reg; /*!< Type used for register access */ 855 } SERCOM_USART_INTFLAG_Type; 856 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 857 858 #define SERCOM_USART_INTFLAG_OFFSET 0x0E /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */ 859 #define SERCOM_USART_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */ 860 861 #define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty */ 862 #define SERCOM_USART_INTFLAG_DRE (0x1ul << SERCOM_USART_INTFLAG_DRE_Pos) 863 #define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete */ 864 #define SERCOM_USART_INTFLAG_TXC (0x1ul << SERCOM_USART_INTFLAG_TXC_Pos) 865 #define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete */ 866 #define SERCOM_USART_INTFLAG_RXC (0x1ul << SERCOM_USART_INTFLAG_RXC_Pos) 867 #define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */ 868 #define SERCOM_USART_INTFLAG_RXS (0x1ul << SERCOM_USART_INTFLAG_RXS_Pos) 869 #define SERCOM_USART_INTFLAG_MASK 0x0Ful /**< \brief (SERCOM_USART_INTFLAG) MASK Register */ 870 871 /* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x10) (R/W 16) I2CM I2CM Status -------- */ 872 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 873 typedef union { 874 struct { 875 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ 876 uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */ 877 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ 878 uint16_t :1; /*!< bit: 3 Reserved */ 879 uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */ 880 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Time-out */ 881 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ 882 uint16_t :7; /*!< bit: 8..14 Reserved */ 883 uint16_t SYNCBUSY:1; /*!< bit: 15 Synchronization Busy */ 884 } bit; /*!< Structure used for bit access */ 885 uint16_t reg; /*!< Type used for register access */ 886 } SERCOM_I2CM_STATUS_Type; 887 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 888 889 #define SERCOM_I2CM_STATUS_OFFSET 0x10 /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */ 890 #define SERCOM_I2CM_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */ 891 892 #define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */ 893 #define SERCOM_I2CM_STATUS_BUSERR (0x1ul << SERCOM_I2CM_STATUS_BUSERR_Pos) 894 #define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */ 895 #define SERCOM_I2CM_STATUS_ARBLOST (0x1ul << SERCOM_I2CM_STATUS_ARBLOST_Pos) 896 #define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */ 897 #define SERCOM_I2CM_STATUS_RXNACK (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos) 898 #define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */ 899 #define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos) 900 #define SERCOM_I2CM_STATUS_BUSSTATE(value) ((SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))) 901 #define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Time-out */ 902 #define SERCOM_I2CM_STATUS_LOWTOUT (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos) 903 #define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */ 904 #define SERCOM_I2CM_STATUS_CLKHOLD (0x1ul << SERCOM_I2CM_STATUS_CLKHOLD_Pos) 905 #define SERCOM_I2CM_STATUS_SYNCBUSY_Pos 15 /**< \brief (SERCOM_I2CM_STATUS) Synchronization Busy */ 906 #define SERCOM_I2CM_STATUS_SYNCBUSY (0x1ul << SERCOM_I2CM_STATUS_SYNCBUSY_Pos) 907 #define SERCOM_I2CM_STATUS_MASK 0x80F7ul /**< \brief (SERCOM_I2CM_STATUS) MASK Register */ 908 909 /* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x10) (R/W 16) I2CS I2CS Status -------- */ 910 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 911 typedef union { 912 struct { 913 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ 914 uint16_t COLL:1; /*!< bit: 1 Transmit Collision */ 915 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ 916 uint16_t DIR:1; /*!< bit: 3 Read / Write Direction */ 917 uint16_t SR:1; /*!< bit: 4 Repeated Start */ 918 uint16_t :1; /*!< bit: 5 Reserved */ 919 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Time-out */ 920 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ 921 uint16_t :7; /*!< bit: 8..14 Reserved */ 922 uint16_t SYNCBUSY:1; /*!< bit: 15 Synchronization Busy */ 923 } bit; /*!< Structure used for bit access */ 924 uint16_t reg; /*!< Type used for register access */ 925 } SERCOM_I2CS_STATUS_Type; 926 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 927 928 #define SERCOM_I2CS_STATUS_OFFSET 0x10 /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */ 929 #define SERCOM_I2CS_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */ 930 931 #define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */ 932 #define SERCOM_I2CS_STATUS_BUSERR (0x1ul << SERCOM_I2CS_STATUS_BUSERR_Pos) 933 #define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */ 934 #define SERCOM_I2CS_STATUS_COLL (0x1ul << SERCOM_I2CS_STATUS_COLL_Pos) 935 #define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */ 936 #define SERCOM_I2CS_STATUS_RXNACK (0x1ul << SERCOM_I2CS_STATUS_RXNACK_Pos) 937 #define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read / Write Direction */ 938 #define SERCOM_I2CS_STATUS_DIR (0x1ul << SERCOM_I2CS_STATUS_DIR_Pos) 939 #define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */ 940 #define SERCOM_I2CS_STATUS_SR (0x1ul << SERCOM_I2CS_STATUS_SR_Pos) 941 #define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Time-out */ 942 #define SERCOM_I2CS_STATUS_LOWTOUT (0x1ul << SERCOM_I2CS_STATUS_LOWTOUT_Pos) 943 #define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */ 944 #define SERCOM_I2CS_STATUS_CLKHOLD (0x1ul << SERCOM_I2CS_STATUS_CLKHOLD_Pos) 945 #define SERCOM_I2CS_STATUS_SYNCBUSY_Pos 15 /**< \brief (SERCOM_I2CS_STATUS) Synchronization Busy */ 946 #define SERCOM_I2CS_STATUS_SYNCBUSY (0x1ul << SERCOM_I2CS_STATUS_SYNCBUSY_Pos) 947 #define SERCOM_I2CS_STATUS_MASK 0x80DFul /**< \brief (SERCOM_I2CS_STATUS) MASK Register */ 948 949 /* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x10) (R/W 16) SPI SPI Status -------- */ 950 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 951 typedef union { 952 struct { 953 uint16_t :2; /*!< bit: 0.. 1 Reserved */ 954 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ 955 uint16_t :12; /*!< bit: 3..14 Reserved */ 956 uint16_t SYNCBUSY:1; /*!< bit: 15 Synchronization Busy */ 957 } bit; /*!< Structure used for bit access */ 958 uint16_t reg; /*!< Type used for register access */ 959 } SERCOM_SPI_STATUS_Type; 960 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 961 962 #define SERCOM_SPI_STATUS_OFFSET 0x10 /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */ 963 #define SERCOM_SPI_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */ 964 965 #define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */ 966 #define SERCOM_SPI_STATUS_BUFOVF (0x1ul << SERCOM_SPI_STATUS_BUFOVF_Pos) 967 #define SERCOM_SPI_STATUS_SYNCBUSY_Pos 15 /**< \brief (SERCOM_SPI_STATUS) Synchronization Busy */ 968 #define SERCOM_SPI_STATUS_SYNCBUSY (0x1ul << SERCOM_SPI_STATUS_SYNCBUSY_Pos) 969 #define SERCOM_SPI_STATUS_MASK 0x8004ul /**< \brief (SERCOM_SPI_STATUS) MASK Register */ 970 971 /* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x10) (R/W 16) USART USART Status -------- */ 972 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 973 typedef union { 974 struct { 975 uint16_t PERR:1; /*!< bit: 0 Parity Error */ 976 uint16_t FERR:1; /*!< bit: 1 Frame Error */ 977 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ 978 uint16_t :12; /*!< bit: 3..14 Reserved */ 979 uint16_t SYNCBUSY:1; /*!< bit: 15 Synchronization Busy */ 980 } bit; /*!< Structure used for bit access */ 981 uint16_t reg; /*!< Type used for register access */ 982 } SERCOM_USART_STATUS_Type; 983 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 984 985 #define SERCOM_USART_STATUS_OFFSET 0x10 /**< \brief (SERCOM_USART_STATUS offset) USART Status */ 986 #define SERCOM_USART_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */ 987 988 #define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */ 989 #define SERCOM_USART_STATUS_PERR (0x1ul << SERCOM_USART_STATUS_PERR_Pos) 990 #define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */ 991 #define SERCOM_USART_STATUS_FERR (0x1ul << SERCOM_USART_STATUS_FERR_Pos) 992 #define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */ 993 #define SERCOM_USART_STATUS_BUFOVF (0x1ul << SERCOM_USART_STATUS_BUFOVF_Pos) 994 #define SERCOM_USART_STATUS_SYNCBUSY_Pos 15 /**< \brief (SERCOM_USART_STATUS) Synchronization Busy */ 995 #define SERCOM_USART_STATUS_SYNCBUSY (0x1ul << SERCOM_USART_STATUS_SYNCBUSY_Pos) 996 #define SERCOM_USART_STATUS_MASK 0x8007ul /**< \brief (SERCOM_USART_STATUS) MASK Register */ 997 998 /* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Address -------- */ 999 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1000 typedef union { 1001 struct { 1002 uint8_t ADDR:8; /*!< bit: 0.. 7 Address */ 1003 } bit; /*!< Structure used for bit access */ 1004 uint8_t reg; /*!< Type used for register access */ 1005 } SERCOM_I2CM_ADDR_Type; 1006 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1007 1008 #define SERCOM_I2CM_ADDR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */ 1009 #define SERCOM_I2CM_ADDR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */ 1010 1011 #define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address */ 1012 #define SERCOM_I2CM_ADDR_ADDR_Msk (0xFFul << SERCOM_I2CM_ADDR_ADDR_Pos) 1013 #define SERCOM_I2CM_ADDR_ADDR(value) ((SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))) 1014 #define SERCOM_I2CM_ADDR_MASK 0xFFul /**< \brief (SERCOM_I2CM_ADDR) MASK Register */ 1015 1016 /* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x14) (R/W 32) I2CS I2CS Address -------- */ 1017 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1018 typedef union { 1019 struct { 1020 uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */ 1021 uint32_t ADDR:7; /*!< bit: 1.. 7 Address */ 1022 uint32_t :9; /*!< bit: 8..16 Reserved */ 1023 uint32_t ADDRMASK:7; /*!< bit: 17..23 Address Mask */ 1024 uint32_t :8; /*!< bit: 24..31 Reserved */ 1025 } bit; /*!< Structure used for bit access */ 1026 uint32_t reg; /*!< Type used for register access */ 1027 } SERCOM_I2CS_ADDR_Type; 1028 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1029 1030 #define SERCOM_I2CS_ADDR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */ 1031 #define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */ 1032 1033 #define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */ 1034 #define SERCOM_I2CS_ADDR_GENCEN (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos) 1035 #define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address */ 1036 #define SERCOM_I2CS_ADDR_ADDR_Msk (0x7Ful << SERCOM_I2CS_ADDR_ADDR_Pos) 1037 #define SERCOM_I2CS_ADDR_ADDR(value) ((SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))) 1038 #define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */ 1039 #define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x7Ful << SERCOM_I2CS_ADDR_ADDRMASK_Pos) 1040 #define SERCOM_I2CS_ADDR_ADDRMASK(value) ((SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))) 1041 #define SERCOM_I2CS_ADDR_MASK 0x00FE00FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */ 1042 1043 /* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x14) (R/W 32) SPI SPI Address -------- */ 1044 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1045 typedef union { 1046 struct { 1047 uint32_t ADDR:8; /*!< bit: 0.. 7 Address */ 1048 uint32_t :8; /*!< bit: 8..15 Reserved */ 1049 uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */ 1050 uint32_t :8; /*!< bit: 24..31 Reserved */ 1051 } bit; /*!< Structure used for bit access */ 1052 uint32_t reg; /*!< Type used for register access */ 1053 } SERCOM_SPI_ADDR_Type; 1054 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1055 1056 #define SERCOM_SPI_ADDR_OFFSET 0x14 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */ 1057 #define SERCOM_SPI_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */ 1058 1059 #define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address */ 1060 #define SERCOM_SPI_ADDR_ADDR_Msk (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos) 1061 #define SERCOM_SPI_ADDR_ADDR(value) ((SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))) 1062 #define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */ 1063 #define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos) 1064 #define SERCOM_SPI_ADDR_ADDRMASK(value) ((SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))) 1065 #define SERCOM_SPI_ADDR_MASK 0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */ 1066 1067 /* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Data -------- */ 1068 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1069 typedef union { 1070 struct { 1071 uint8_t DATA:8; /*!< bit: 0.. 7 Data */ 1072 } bit; /*!< Structure used for bit access */ 1073 uint8_t reg; /*!< Type used for register access */ 1074 } SERCOM_I2CM_DATA_Type; 1075 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1076 1077 #define SERCOM_I2CM_DATA_OFFSET 0x18 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */ 1078 #define SERCOM_I2CM_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */ 1079 1080 #define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data */ 1081 #define SERCOM_I2CM_DATA_DATA_Msk (0xFFul << SERCOM_I2CM_DATA_DATA_Pos) 1082 #define SERCOM_I2CM_DATA_DATA(value) ((SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))) 1083 #define SERCOM_I2CM_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CM_DATA) MASK Register */ 1084 1085 /* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Data -------- */ 1086 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1087 typedef union { 1088 struct { 1089 uint8_t DATA:8; /*!< bit: 0.. 7 Data */ 1090 } bit; /*!< Structure used for bit access */ 1091 uint8_t reg; /*!< Type used for register access */ 1092 } SERCOM_I2CS_DATA_Type; 1093 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1094 1095 #define SERCOM_I2CS_DATA_OFFSET 0x18 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */ 1096 #define SERCOM_I2CS_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */ 1097 1098 #define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data */ 1099 #define SERCOM_I2CS_DATA_DATA_Msk (0xFFul << SERCOM_I2CS_DATA_DATA_Pos) 1100 #define SERCOM_I2CS_DATA_DATA(value) ((SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))) 1101 #define SERCOM_I2CS_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CS_DATA) MASK Register */ 1102 1103 /* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x18) (R/W 16) SPI SPI Data -------- */ 1104 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1105 typedef union { 1106 struct { 1107 uint16_t DATA:9; /*!< bit: 0.. 8 Data */ 1108 uint16_t :7; /*!< bit: 9..15 Reserved */ 1109 } bit; /*!< Structure used for bit access */ 1110 uint16_t reg; /*!< Type used for register access */ 1111 } SERCOM_SPI_DATA_Type; 1112 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1113 1114 #define SERCOM_SPI_DATA_OFFSET 0x18 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */ 1115 #define SERCOM_SPI_DATA_RESETVALUE 0x0000ul /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */ 1116 1117 #define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data */ 1118 #define SERCOM_SPI_DATA_DATA_Msk (0x1FFul << SERCOM_SPI_DATA_DATA_Pos) 1119 #define SERCOM_SPI_DATA_DATA(value) ((SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))) 1120 #define SERCOM_SPI_DATA_MASK 0x01FFul /**< \brief (SERCOM_SPI_DATA) MASK Register */ 1121 1122 /* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x18) (R/W 16) USART USART Data -------- */ 1123 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1124 typedef union { 1125 struct { 1126 uint16_t DATA:9; /*!< bit: 0.. 8 Data */ 1127 uint16_t :7; /*!< bit: 9..15 Reserved */ 1128 } bit; /*!< Structure used for bit access */ 1129 uint16_t reg; /*!< Type used for register access */ 1130 } SERCOM_USART_DATA_Type; 1131 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1132 1133 #define SERCOM_USART_DATA_OFFSET 0x18 /**< \brief (SERCOM_USART_DATA offset) USART Data */ 1134 #define SERCOM_USART_DATA_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_DATA reset_value) USART Data */ 1135 1136 #define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data */ 1137 #define SERCOM_USART_DATA_DATA_Msk (0x1FFul << SERCOM_USART_DATA_DATA_Pos) 1138 #define SERCOM_USART_DATA_DATA(value) ((SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))) 1139 #define SERCOM_USART_DATA_MASK 0x01FFul /**< \brief (SERCOM_USART_DATA) MASK Register */ 1140 1141 /** \brief SERCOM_I2CM hardware registers */ 1142 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1143 typedef struct { /* I2C Master Mode */ 1144 __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ 1145 __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ 1146 __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) I2CM Debug Control */ 1147 RoReg8 Reserved1[0x1]; 1148 __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0A (R/W 16) I2CM Baud Rate */ 1149 __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) I2CM Interrupt Enable Clear */ 1150 __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) I2CM Interrupt Enable Set */ 1151 __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) I2CM Interrupt Flag Status and Clear */ 1152 RoReg8 Reserved2[0x1]; 1153 __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/W 16) I2CM Status */ 1154 RoReg8 Reserved3[0x2]; 1155 __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x14 (R/W 8) I2CM Address */ 1156 RoReg8 Reserved4[0x3]; 1157 __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x18 (R/W 8) I2CM Data */ 1158 } SercomI2cm; 1159 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1160 1161 /** \brief SERCOM_I2CS hardware registers */ 1162 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1163 typedef struct { /* I2C Slave Mode */ 1164 __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ 1165 __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ 1166 RoReg8 Reserved1[0x4]; 1167 __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) I2CS Interrupt Enable Clear */ 1168 __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) I2CS Interrupt Enable Set */ 1169 __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) I2CS Interrupt Flag Status and Clear */ 1170 RoReg8 Reserved2[0x1]; 1171 __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/W 16) I2CS Status */ 1172 RoReg8 Reserved3[0x2]; 1173 __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x14 (R/W 32) I2CS Address */ 1174 __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x18 (R/W 8) I2CS Data */ 1175 } SercomI2cs; 1176 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1177 1178 /** \brief SERCOM_SPI hardware registers */ 1179 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1180 typedef struct { /* SPI Mode */ 1181 __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ 1182 __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ 1183 __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) SPI Debug Control */ 1184 RoReg8 Reserved1[0x1]; 1185 __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0A (R/W 8) SPI Baud Rate */ 1186 RoReg8 Reserved2[0x1]; 1187 __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) SPI Interrupt Enable Clear */ 1188 __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) SPI Interrupt Enable Set */ 1189 __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) SPI Interrupt Flag Status and Clear */ 1190 RoReg8 Reserved3[0x1]; 1191 __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/W 16) SPI Status */ 1192 RoReg8 Reserved4[0x2]; 1193 __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x14 (R/W 32) SPI Address */ 1194 __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x18 (R/W 16) SPI Data */ 1195 } SercomSpi; 1196 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1197 1198 /** \brief SERCOM_USART hardware registers */ 1199 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1200 typedef struct { /* USART Mode */ 1201 __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ 1202 __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ 1203 __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) USART Debug Control */ 1204 RoReg8 Reserved1[0x1]; 1205 __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0A (R/W 16) USART Baud */ 1206 __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) USART Interrupt Enable Clear */ 1207 __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) USART Interrupt Enable Set */ 1208 __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) USART Interrupt Flag Status and Clear */ 1209 RoReg8 Reserved2[0x1]; 1210 __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/W 16) USART Status */ 1211 RoReg8 Reserved3[0x6]; 1212 __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x18 (R/W 16) USART Data */ 1213 } SercomUsart; 1214 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1215 1216 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1217 typedef union { 1218 SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */ 1219 SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */ 1220 SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */ 1221 SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */ 1222 } Sercom; 1223 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1224 1225 /*@}*/ 1226 1227 #endif /* _SAMD20_SERCOM_COMPONENT_ */ 1228