1 /* 2 * Copyright (c) 2021-2024 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_LOBS_H 10 #define HPM_LOBS_H 11 12 typedef struct { 13 __RW uint32_t CTRL; /* 0x0: Control Register */ 14 __R uint8_t RESERVED0[8]; /* 0x4 - 0xB: Reserved */ 15 __RW uint32_t STREAMCTRL; /* 0xC: Stream Control Register */ 16 __RW uint32_t PTACTION; /* 0x10: Pre-trigger Action Register */ 17 __RW uint32_t STARTADDR; /* 0x14: Start Address Register */ 18 __RW uint32_t ENDADDR; /* 0x18: End Address Register */ 19 __R uint8_t RESERVED1[4]; /* 0x1C - 0x1F: Reserved */ 20 __R uint32_t CTSR; /* 0x20: Current Trigger State Register */ 21 __R uint32_t CCVR; /* 0x24: Current Counter Value Register */ 22 __R uint32_t CAVR; /* 0x28: Current Action Value Register */ 23 __R uint8_t RESERVED2[4]; /* 0x2C - 0x2F: Reserved */ 24 __R uint32_t FIFOSTATE; /* 0x30: Fifo State Register */ 25 __RW uint32_t FINALADDR; /* 0x34: Final Address Register */ 26 __R uint8_t RESERVED3[24]; /* 0x38 - 0x4F: Reserved */ 27 __RW uint32_t GRPSELA; /* 0x50: Group Select Register */ 28 __RW uint32_t GRPENA; /* 0x54: Group Enable Register */ 29 __RW uint32_t SIGSELA1; /* 0x58: Signal Select1 Register */ 30 __R uint8_t RESERVED4[4]; /* 0x5C - 0x5F: Reserved */ 31 __RW uint32_t SIGSELA2; /* 0x60: Signal Select2 Register */ 32 __R uint8_t RESERVED5[52]; /* 0x64 - 0x97: Reserved */ 33 __RW uint32_t SIGENA; /* 0x98: Signal Enable Register */ 34 __R uint8_t RESERVED6[100]; /* 0x9C - 0xFF: Reserved */ 35 struct { 36 __RW uint32_t SIGSEL; /* 0x100: Signal Select Register */ 37 __RW uint32_t TRIGCTRL; /* 0x104: Trigger Control Register */ 38 __RW uint32_t NEXTSTATE; /* 0x108: Next State Register */ 39 __RW uint32_t ACTION; /* 0x10C: Action Register */ 40 __R uint8_t RESERVED0[16]; /* 0x110 - 0x11F: Reserved */ 41 __RW uint32_t COUNTCOMP; /* 0x120: Counter Compare Register */ 42 __R uint8_t RESERVED1[12]; /* 0x124 - 0x12F: Reserved */ 43 __RW uint32_t EXTMASK; /* 0x130: External Mask Register */ 44 __RW uint32_t EXTCOMP; /* 0x134: External Compare Register */ 45 __R uint8_t RESERVED2[8]; /* 0x138 - 0x13F: Reserved */ 46 __RW uint32_t SIGMASK; /* 0x140: Signal Mask Register */ 47 __RW uint32_t COMPEN; /* 0x144: Compare Enable register */ 48 __R uint8_t RESERVED3[56]; /* 0x148 - 0x17F: Reserved */ 49 __RW uint32_t SIGCOMP0; /* 0x180: Signal Compare Register0 */ 50 __RW uint32_t SIGCOMP1; /* 0x184: Signal Compare Register1 */ 51 __RW uint32_t SIGCOMP2; /* 0x188: Signal Compare Register2 */ 52 __RW uint32_t SIGCOMP3; /* 0x18C: Signal Compare Register3 */ 53 __R uint8_t RESERVED4[112]; /* 0x190 - 0x1FF: Reserved */ 54 } STATE[5]; 55 __R uint8_t RESERVED7[2480]; /* 0x600 - 0xFAF: Reserved */ 56 __RW uint32_t LAR; /* 0xFB0: Lock Access Register */ 57 } LOBS_Type; 58 59 60 /* Bitfield definition for register: CTRL */ 61 /* 62 * RUN (RW) 63 * 64 * Run control. 65 * 0 LOBS disabled. Register programming permitted. 66 * 1 LOBS enabled 67 */ 68 #define LOBS_CTRL_RUN_MASK (0x1U) 69 #define LOBS_CTRL_RUN_SHIFT (0U) 70 #define LOBS_CTRL_RUN_SET(x) (((uint32_t)(x) << LOBS_CTRL_RUN_SHIFT) & LOBS_CTRL_RUN_MASK) 71 #define LOBS_CTRL_RUN_GET(x) (((uint32_t)(x) & LOBS_CTRL_RUN_MASK) >> LOBS_CTRL_RUN_SHIFT) 72 73 /* Bitfield definition for register: STREAMCTRL */ 74 /* 75 * SEL (RW) 76 * 77 * Signal Group Select 78 * 0 128bit from one group 79 * 1 from 2 groups, 4bit in each group 80 */ 81 #define LOBS_STREAMCTRL_SEL_MASK (0x100U) 82 #define LOBS_STREAMCTRL_SEL_SHIFT (8U) 83 #define LOBS_STREAMCTRL_SEL_SET(x) (((uint32_t)(x) << LOBS_STREAMCTRL_SEL_SHIFT) & LOBS_STREAMCTRL_SEL_MASK) 84 #define LOBS_STREAMCTRL_SEL_GET(x) (((uint32_t)(x) & LOBS_STREAMCTRL_SEL_MASK) >> LOBS_STREAMCTRL_SEL_SHIFT) 85 86 /* 87 * FULL_CLEAR (RW) 88 * 89 * FIFO Overflow Clear 90 */ 91 #define LOBS_STREAMCTRL_FULL_CLEAR_MASK (0x80U) 92 #define LOBS_STREAMCTRL_FULL_CLEAR_SHIFT (7U) 93 #define LOBS_STREAMCTRL_FULL_CLEAR_SET(x) (((uint32_t)(x) << LOBS_STREAMCTRL_FULL_CLEAR_SHIFT) & LOBS_STREAMCTRL_FULL_CLEAR_MASK) 94 #define LOBS_STREAMCTRL_FULL_CLEAR_GET(x) (((uint32_t)(x) & LOBS_STREAMCTRL_FULL_CLEAR_MASK) >> LOBS_STREAMCTRL_FULL_CLEAR_SHIFT) 95 96 /* 97 * SAMPLE (RW) 98 * 99 * Sample Rate 100 * 4 take one every 5 101 * 5 take one every 6 102 * 6 take one every 7 103 */ 104 #define LOBS_STREAMCTRL_SAMPLE_MASK (0x78U) 105 #define LOBS_STREAMCTRL_SAMPLE_SHIFT (3U) 106 #define LOBS_STREAMCTRL_SAMPLE_SET(x) (((uint32_t)(x) << LOBS_STREAMCTRL_SAMPLE_SHIFT) & LOBS_STREAMCTRL_SAMPLE_MASK) 107 #define LOBS_STREAMCTRL_SAMPLE_GET(x) (((uint32_t)(x) & LOBS_STREAMCTRL_SAMPLE_MASK) >> LOBS_STREAMCTRL_SAMPLE_SHIFT) 108 109 /* 110 * BURST (RW) 111 * 112 * Burst Cfg 113 * 3b011 Incr4 114 * 3b101 Incr8 115 * 3b111 Incr16 116 */ 117 #define LOBS_STREAMCTRL_BURST_MASK (0x7U) 118 #define LOBS_STREAMCTRL_BURST_SHIFT (0U) 119 #define LOBS_STREAMCTRL_BURST_SET(x) (((uint32_t)(x) << LOBS_STREAMCTRL_BURST_SHIFT) & LOBS_STREAMCTRL_BURST_MASK) 120 #define LOBS_STREAMCTRL_BURST_GET(x) (((uint32_t)(x) & LOBS_STREAMCTRL_BURST_MASK) >> LOBS_STREAMCTRL_BURST_SHIFT) 121 122 /* Bitfield definition for register: PTACTION */ 123 /* 124 * TRACE (RW) 125 * 126 * Enables trace 127 */ 128 #define LOBS_PTACTION_TRACE_MASK (0x8U) 129 #define LOBS_PTACTION_TRACE_SHIFT (3U) 130 #define LOBS_PTACTION_TRACE_SET(x) (((uint32_t)(x) << LOBS_PTACTION_TRACE_SHIFT) & LOBS_PTACTION_TRACE_MASK) 131 #define LOBS_PTACTION_TRACE_GET(x) (((uint32_t)(x) & LOBS_PTACTION_TRACE_MASK) >> LOBS_PTACTION_TRACE_SHIFT) 132 133 /* Bitfield definition for register: STARTADDR */ 134 /* 135 * ADDR (RW) 136 * 137 * Start address 138 */ 139 #define LOBS_STARTADDR_ADDR_MASK (0xFFFFFFFFUL) 140 #define LOBS_STARTADDR_ADDR_SHIFT (0U) 141 #define LOBS_STARTADDR_ADDR_SET(x) (((uint32_t)(x) << LOBS_STARTADDR_ADDR_SHIFT) & LOBS_STARTADDR_ADDR_MASK) 142 #define LOBS_STARTADDR_ADDR_GET(x) (((uint32_t)(x) & LOBS_STARTADDR_ADDR_MASK) >> LOBS_STARTADDR_ADDR_SHIFT) 143 144 /* Bitfield definition for register: ENDADDR */ 145 /* 146 * ADDR (RW) 147 * 148 * End address 149 */ 150 #define LOBS_ENDADDR_ADDR_MASK (0xFFFFFFFFUL) 151 #define LOBS_ENDADDR_ADDR_SHIFT (0U) 152 #define LOBS_ENDADDR_ADDR_SET(x) (((uint32_t)(x) << LOBS_ENDADDR_ADDR_SHIFT) & LOBS_ENDADDR_ADDR_MASK) 153 #define LOBS_ENDADDR_ADDR_GET(x) (((uint32_t)(x) & LOBS_ENDADDR_ADDR_MASK) >> LOBS_ENDADDR_ADDR_SHIFT) 154 155 /* Bitfield definition for register: CTSR */ 156 /* 157 * FINALSTATE (RO) 158 * 159 * 0 LOBS is still tracing. 160 * 1 Indicates that the LOBS has stopped advancing Trigger States and stopped trace. 161 * FINALSTATE can be set by TRIGCTRL.COUNTBRK reaching the final loop count, or by programming NEXTSTATEto zero 162 */ 163 #define LOBS_CTSR_FINALSTATE_MASK (0x80000000UL) 164 #define LOBS_CTSR_FINALSTATE_SHIFT (31U) 165 #define LOBS_CTSR_FINALSTATE_GET(x) (((uint32_t)(x) & LOBS_CTSR_FINALSTATE_MASK) >> LOBS_CTSR_FINALSTATE_SHIFT) 166 167 /* 168 * CTSR (RO) 169 * 170 * Reads current Trigger State. This is a one-hot encoded field. 171 * When CTRL.RUN: 172 * 0 RAZ. 173 * 1 Returns current Trigger State. 174 * If FINALSTATE is 1, then the CTSR field gives the Trigger State when FINALSTATE became 1 175 */ 176 #define LOBS_CTSR_CTSR_MASK (0x1FU) 177 #define LOBS_CTSR_CTSR_SHIFT (0U) 178 #define LOBS_CTSR_CTSR_GET(x) (((uint32_t)(x) & LOBS_CTSR_CTSR_MASK) >> LOBS_CTSR_CTSR_SHIFT) 179 180 /* Bitfield definition for register: CCVR */ 181 /* 182 * CCVR (RO) 183 * 184 * Returns the counter value when the CTSR was last read. If the CTSR has never been read, then the value in the CCVR is undefined 185 */ 186 #define LOBS_CCVR_CCVR_MASK (0xFFFFFFFFUL) 187 #define LOBS_CCVR_CCVR_SHIFT (0U) 188 #define LOBS_CCVR_CCVR_GET(x) (((uint32_t)(x) & LOBS_CCVR_CCVR_MASK) >> LOBS_CCVR_CCVR_SHIFT) 189 190 /* Bitfield definition for register: CAVR */ 191 /* 192 * TRACE (RO) 193 * 194 * Trace active. 195 * 0b0 Trace is not active. 196 * 0b1 Trace is active. 197 */ 198 #define LOBS_CAVR_TRACE_MASK (0x8U) 199 #define LOBS_CAVR_TRACE_SHIFT (3U) 200 #define LOBS_CAVR_TRACE_GET(x) (((uint32_t)(x) & LOBS_CAVR_TRACE_MASK) >> LOBS_CAVR_TRACE_SHIFT) 201 202 /* Bitfield definition for register: FIFOSTATE */ 203 /* 204 * FULL (RO) 205 * 206 * FIFO full 207 */ 208 #define LOBS_FIFOSTATE_FULL_MASK (0x2U) 209 #define LOBS_FIFOSTATE_FULL_SHIFT (1U) 210 #define LOBS_FIFOSTATE_FULL_GET(x) (((uint32_t)(x) & LOBS_FIFOSTATE_FULL_MASK) >> LOBS_FIFOSTATE_FULL_SHIFT) 211 212 /* 213 * EMPTY (RO) 214 * 215 * FIFO empty 216 */ 217 #define LOBS_FIFOSTATE_EMPTY_MASK (0x1U) 218 #define LOBS_FIFOSTATE_EMPTY_SHIFT (0U) 219 #define LOBS_FIFOSTATE_EMPTY_GET(x) (((uint32_t)(x) & LOBS_FIFOSTATE_EMPTY_MASK) >> LOBS_FIFOSTATE_EMPTY_SHIFT) 220 221 /* Bitfield definition for register: FINALADDR */ 222 /* 223 * ADDR (RW) 224 * 225 * Final address 226 */ 227 #define LOBS_FINALADDR_ADDR_MASK (0xFFFFFFFFUL) 228 #define LOBS_FINALADDR_ADDR_SHIFT (0U) 229 #define LOBS_FINALADDR_ADDR_SET(x) (((uint32_t)(x) << LOBS_FINALADDR_ADDR_SHIFT) & LOBS_FINALADDR_ADDR_MASK) 230 #define LOBS_FINALADDR_ADDR_GET(x) (((uint32_t)(x) & LOBS_FINALADDR_ADDR_MASK) >> LOBS_FINALADDR_ADDR_SHIFT) 231 232 /* Bitfield definition for register: GRPSELA */ 233 /* 234 * NUM2 (RW) 235 * 236 * Select sample group number2 237 */ 238 #define LOBS_GRPSELA_NUM2_MASK (0xF0U) 239 #define LOBS_GRPSELA_NUM2_SHIFT (4U) 240 #define LOBS_GRPSELA_NUM2_SET(x) (((uint32_t)(x) << LOBS_GRPSELA_NUM2_SHIFT) & LOBS_GRPSELA_NUM2_MASK) 241 #define LOBS_GRPSELA_NUM2_GET(x) (((uint32_t)(x) & LOBS_GRPSELA_NUM2_MASK) >> LOBS_GRPSELA_NUM2_SHIFT) 242 243 /* 244 * NUM1 (RW) 245 * 246 * Select sample group number1 247 */ 248 #define LOBS_GRPSELA_NUM1_MASK (0xFU) 249 #define LOBS_GRPSELA_NUM1_SHIFT (0U) 250 #define LOBS_GRPSELA_NUM1_SET(x) (((uint32_t)(x) << LOBS_GRPSELA_NUM1_SHIFT) & LOBS_GRPSELA_NUM1_MASK) 251 #define LOBS_GRPSELA_NUM1_GET(x) (((uint32_t)(x) & LOBS_GRPSELA_NUM1_MASK) >> LOBS_GRPSELA_NUM1_SHIFT) 252 253 /* Bitfield definition for register: GRPENA */ 254 /* 255 * EN2 (RW) 256 * 257 * Enable sample group number2 258 */ 259 #define LOBS_GRPENA_EN2_MASK (0x2U) 260 #define LOBS_GRPENA_EN2_SHIFT (1U) 261 #define LOBS_GRPENA_EN2_SET(x) (((uint32_t)(x) << LOBS_GRPENA_EN2_SHIFT) & LOBS_GRPENA_EN2_MASK) 262 #define LOBS_GRPENA_EN2_GET(x) (((uint32_t)(x) & LOBS_GRPENA_EN2_MASK) >> LOBS_GRPENA_EN2_SHIFT) 263 264 /* 265 * EN1 (RW) 266 * 267 * Enable sample group number1 268 */ 269 #define LOBS_GRPENA_EN1_MASK (0x1U) 270 #define LOBS_GRPENA_EN1_SHIFT (0U) 271 #define LOBS_GRPENA_EN1_SET(x) (((uint32_t)(x) << LOBS_GRPENA_EN1_SHIFT) & LOBS_GRPENA_EN1_MASK) 272 #define LOBS_GRPENA_EN1_GET(x) (((uint32_t)(x) & LOBS_GRPENA_EN1_MASK) >> LOBS_GRPENA_EN1_SHIFT) 273 274 /* Bitfield definition for register: SIGSELA1 */ 275 /* 276 * NUM4 (RW) 277 * 278 * Select sample signal bit number4 in first group 279 */ 280 #define LOBS_SIGSELA1_NUM4_MASK (0xFF000000UL) 281 #define LOBS_SIGSELA1_NUM4_SHIFT (24U) 282 #define LOBS_SIGSELA1_NUM4_SET(x) (((uint32_t)(x) << LOBS_SIGSELA1_NUM4_SHIFT) & LOBS_SIGSELA1_NUM4_MASK) 283 #define LOBS_SIGSELA1_NUM4_GET(x) (((uint32_t)(x) & LOBS_SIGSELA1_NUM4_MASK) >> LOBS_SIGSELA1_NUM4_SHIFT) 284 285 /* 286 * NUM3 (RW) 287 * 288 * Select sample signal bit number3 in first group 289 */ 290 #define LOBS_SIGSELA1_NUM3_MASK (0xFF0000UL) 291 #define LOBS_SIGSELA1_NUM3_SHIFT (16U) 292 #define LOBS_SIGSELA1_NUM3_SET(x) (((uint32_t)(x) << LOBS_SIGSELA1_NUM3_SHIFT) & LOBS_SIGSELA1_NUM3_MASK) 293 #define LOBS_SIGSELA1_NUM3_GET(x) (((uint32_t)(x) & LOBS_SIGSELA1_NUM3_MASK) >> LOBS_SIGSELA1_NUM3_SHIFT) 294 295 /* 296 * NUM2 (RW) 297 * 298 * Select sample signal bit number2 in first group 299 */ 300 #define LOBS_SIGSELA1_NUM2_MASK (0xFF00U) 301 #define LOBS_SIGSELA1_NUM2_SHIFT (8U) 302 #define LOBS_SIGSELA1_NUM2_SET(x) (((uint32_t)(x) << LOBS_SIGSELA1_NUM2_SHIFT) & LOBS_SIGSELA1_NUM2_MASK) 303 #define LOBS_SIGSELA1_NUM2_GET(x) (((uint32_t)(x) & LOBS_SIGSELA1_NUM2_MASK) >> LOBS_SIGSELA1_NUM2_SHIFT) 304 305 /* 306 * NUM1 (RW) 307 * 308 * Select sample signal bit number1 in first group 309 */ 310 #define LOBS_SIGSELA1_NUM1_MASK (0xFFU) 311 #define LOBS_SIGSELA1_NUM1_SHIFT (0U) 312 #define LOBS_SIGSELA1_NUM1_SET(x) (((uint32_t)(x) << LOBS_SIGSELA1_NUM1_SHIFT) & LOBS_SIGSELA1_NUM1_MASK) 313 #define LOBS_SIGSELA1_NUM1_GET(x) (((uint32_t)(x) & LOBS_SIGSELA1_NUM1_MASK) >> LOBS_SIGSELA1_NUM1_SHIFT) 314 315 /* Bitfield definition for register: SIGSELA2 */ 316 /* 317 * NUM4 (RW) 318 * 319 * Select sample signal bit number4 in second group 320 */ 321 #define LOBS_SIGSELA2_NUM4_MASK (0xFF000000UL) 322 #define LOBS_SIGSELA2_NUM4_SHIFT (24U) 323 #define LOBS_SIGSELA2_NUM4_SET(x) (((uint32_t)(x) << LOBS_SIGSELA2_NUM4_SHIFT) & LOBS_SIGSELA2_NUM4_MASK) 324 #define LOBS_SIGSELA2_NUM4_GET(x) (((uint32_t)(x) & LOBS_SIGSELA2_NUM4_MASK) >> LOBS_SIGSELA2_NUM4_SHIFT) 325 326 /* 327 * NUM3 (RW) 328 * 329 * Select sample signal bit number3 in second group 330 */ 331 #define LOBS_SIGSELA2_NUM3_MASK (0xFF0000UL) 332 #define LOBS_SIGSELA2_NUM3_SHIFT (16U) 333 #define LOBS_SIGSELA2_NUM3_SET(x) (((uint32_t)(x) << LOBS_SIGSELA2_NUM3_SHIFT) & LOBS_SIGSELA2_NUM3_MASK) 334 #define LOBS_SIGSELA2_NUM3_GET(x) (((uint32_t)(x) & LOBS_SIGSELA2_NUM3_MASK) >> LOBS_SIGSELA2_NUM3_SHIFT) 335 336 /* 337 * NUM2 (RW) 338 * 339 * Select sample signal bit number2 in second group 340 */ 341 #define LOBS_SIGSELA2_NUM2_MASK (0xFF00U) 342 #define LOBS_SIGSELA2_NUM2_SHIFT (8U) 343 #define LOBS_SIGSELA2_NUM2_SET(x) (((uint32_t)(x) << LOBS_SIGSELA2_NUM2_SHIFT) & LOBS_SIGSELA2_NUM2_MASK) 344 #define LOBS_SIGSELA2_NUM2_GET(x) (((uint32_t)(x) & LOBS_SIGSELA2_NUM2_MASK) >> LOBS_SIGSELA2_NUM2_SHIFT) 345 346 /* 347 * NUM1 (RW) 348 * 349 * Select sample signal bit number1 in second group 350 */ 351 #define LOBS_SIGSELA2_NUM1_MASK (0xFFU) 352 #define LOBS_SIGSELA2_NUM1_SHIFT (0U) 353 #define LOBS_SIGSELA2_NUM1_SET(x) (((uint32_t)(x) << LOBS_SIGSELA2_NUM1_SHIFT) & LOBS_SIGSELA2_NUM1_MASK) 354 #define LOBS_SIGSELA2_NUM1_GET(x) (((uint32_t)(x) & LOBS_SIGSELA2_NUM1_MASK) >> LOBS_SIGSELA2_NUM1_SHIFT) 355 356 /* Bitfield definition for register: SIGENA */ 357 /* 358 * EN2 (RW) 359 * 360 * Enable sample signal number2 361 */ 362 #define LOBS_SIGENA_EN2_MASK (0xF0U) 363 #define LOBS_SIGENA_EN2_SHIFT (4U) 364 #define LOBS_SIGENA_EN2_SET(x) (((uint32_t)(x) << LOBS_SIGENA_EN2_SHIFT) & LOBS_SIGENA_EN2_MASK) 365 #define LOBS_SIGENA_EN2_GET(x) (((uint32_t)(x) & LOBS_SIGENA_EN2_MASK) >> LOBS_SIGENA_EN2_SHIFT) 366 367 /* 368 * EN1 (RW) 369 * 370 * Enable sample signal number1 371 */ 372 #define LOBS_SIGENA_EN1_MASK (0xFU) 373 #define LOBS_SIGENA_EN1_SHIFT (0U) 374 #define LOBS_SIGENA_EN1_SET(x) (((uint32_t)(x) << LOBS_SIGENA_EN1_SHIFT) & LOBS_SIGENA_EN1_MASK) 375 #define LOBS_SIGENA_EN1_GET(x) (((uint32_t)(x) & LOBS_SIGENA_EN1_MASK) >> LOBS_SIGENA_EN1_SHIFT) 376 377 /* Bitfield definition for register of struct array STATE: SIGSEL */ 378 /* 379 * EN (RW) 380 * 381 * Selects Signal Group. 382 * 0x1 Selects Signal Group 0. 383 * 0x2 Selects Signal Group 1. 384 * 0x4 Selects Signal Group 2. 385 * 0x8 Selects Signal Group 3. 386 * 0x10 Selects Signal Group 4. 387 * 0x20 Selects Signal Group 5. 388 * 0x40 Selects Signal Group 6. 389 * 0x80 Selects Signal Group 7. 390 * 0x100 Selects Signal Group 8. 391 * 0x200 Selects Signal Group 9. 392 * 0x400 Selects Signal Group 10. 393 * 0x800 Selects Signal Group 11. 394 */ 395 #define LOBS_STATE_SIGSEL_EN_MASK (0xFFFU) 396 #define LOBS_STATE_SIGSEL_EN_SHIFT (0U) 397 #define LOBS_STATE_SIGSEL_EN_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGSEL_EN_SHIFT) & LOBS_STATE_SIGSEL_EN_MASK) 398 #define LOBS_STATE_SIGSEL_EN_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGSEL_EN_MASK) >> LOBS_STATE_SIGSEL_EN_SHIFT) 399 400 /* Bitfield definition for register of struct array STATE: TRIGCTRL */ 401 /* 402 * TRACE (RW) 403 * 404 * Trace capture control. 405 * 0b10 Trace is captured every ELACLK cycle. 406 * others Reserved. 407 */ 408 #define LOBS_STATE_TRIGCTRL_TRACE_MASK (0xC0U) 409 #define LOBS_STATE_TRIGCTRL_TRACE_SHIFT (6U) 410 #define LOBS_STATE_TRIGCTRL_TRACE_SET(x) (((uint32_t)(x) << LOBS_STATE_TRIGCTRL_TRACE_SHIFT) & LOBS_STATE_TRIGCTRL_TRACE_MASK) 411 #define LOBS_STATE_TRIGCTRL_TRACE_GET(x) (((uint32_t)(x) & LOBS_STATE_TRIGCTRL_TRACE_MASK) >> LOBS_STATE_TRIGCTRL_TRACE_SHIFT) 412 413 /* 414 * COMPSEL (RW) 415 * 416 * Comparison mode. Acts as both a counter enable and a select for the comparison mode. 417 * 0b0 Disable counters and select Trigger Signal Comparison mode. 418 * 0b1 Enable counters and select Trigger Counter Comparison mode. 419 */ 420 #define LOBS_STATE_TRIGCTRL_COMPSEL_MASK (0x8U) 421 #define LOBS_STATE_TRIGCTRL_COMPSEL_SHIFT (3U) 422 #define LOBS_STATE_TRIGCTRL_COMPSEL_SET(x) (((uint32_t)(x) << LOBS_STATE_TRIGCTRL_COMPSEL_SHIFT) & LOBS_STATE_TRIGCTRL_COMPSEL_MASK) 423 #define LOBS_STATE_TRIGCTRL_COMPSEL_GET(x) (((uint32_t)(x) & LOBS_STATE_TRIGCTRL_COMPSEL_MASK) >> LOBS_STATE_TRIGCTRL_COMPSEL_SHIFT) 424 425 /* 426 * COMP (RW) 427 * 428 * Trigger Signal Comparison type select. 429 * 0b000 Trigger Signal Comparisons disabled. The enabled counters count clocks immediately after the Trigger State has been entered and generate a programmable Output Action and transition to the next Trigger State when the Counter Compare Register count is reached, that is when a Trigger Counter Comparison match occurs. 430 * 0b001 Compare type is equal (==). 431 * 0b010 Compare type is greater than (>). 432 * 0b011 Compare type is greater than or equal (>=). 433 * 0b101 Compare type is not equal (!=). 434 * 0b110 Compare type is less than (<). 435 * 0b111 Compare type is less than or equal (<=). 436 */ 437 #define LOBS_STATE_TRIGCTRL_COMP_MASK (0x7U) 438 #define LOBS_STATE_TRIGCTRL_COMP_SHIFT (0U) 439 #define LOBS_STATE_TRIGCTRL_COMP_SET(x) (((uint32_t)(x) << LOBS_STATE_TRIGCTRL_COMP_SHIFT) & LOBS_STATE_TRIGCTRL_COMP_MASK) 440 #define LOBS_STATE_TRIGCTRL_COMP_GET(x) (((uint32_t)(x) & LOBS_STATE_TRIGCTRL_COMP_MASK) >> LOBS_STATE_TRIGCTRL_COMP_SHIFT) 441 442 /* Bitfield definition for register of struct array STATE: NEXTSTATE */ 443 /* 444 * NEXTSTATE (RW) 445 * 446 * Selects the next state to move to after the Trigger Condition has been met in the current state. 447 * 0x0 Do not change state. This is the final Trigger State. 448 * 0x1 Selects Trigger State 0. 449 * 0x2 Selects Trigger State 1. 450 * 0x4 Selects Trigger State 2. 451 * 0x8 Selects Trigger State 3. 452 * 0x10 Selects Trigger State 4. 453 */ 454 #define LOBS_STATE_NEXTSTATE_NEXTSTATE_MASK (0x1FU) 455 #define LOBS_STATE_NEXTSTATE_NEXTSTATE_SHIFT (0U) 456 #define LOBS_STATE_NEXTSTATE_NEXTSTATE_SET(x) (((uint32_t)(x) << LOBS_STATE_NEXTSTATE_NEXTSTATE_SHIFT) & LOBS_STATE_NEXTSTATE_NEXTSTATE_MASK) 457 #define LOBS_STATE_NEXTSTATE_NEXTSTATE_GET(x) (((uint32_t)(x) & LOBS_STATE_NEXTSTATE_NEXTSTATE_MASK) >> LOBS_STATE_NEXTSTATE_NEXTSTATE_SHIFT) 458 459 /* Bitfield definition for register of struct array STATE: ACTION */ 460 /* 461 * TRACE (RW) 462 * 463 * Trace active. 464 * 0b0 Trace disable. 465 * 0b1 Trace enable. 466 */ 467 #define LOBS_STATE_ACTION_TRACE_MASK (0x8U) 468 #define LOBS_STATE_ACTION_TRACE_SHIFT (3U) 469 #define LOBS_STATE_ACTION_TRACE_SET(x) (((uint32_t)(x) << LOBS_STATE_ACTION_TRACE_SHIFT) & LOBS_STATE_ACTION_TRACE_MASK) 470 #define LOBS_STATE_ACTION_TRACE_GET(x) (((uint32_t)(x) & LOBS_STATE_ACTION_TRACE_MASK) >> LOBS_STATE_ACTION_TRACE_SHIFT) 471 472 /* Bitfield definition for register of struct array STATE: COUNTCOMP */ 473 /* 474 * VALUE (RW) 475 * 476 * A value that, when reached in the associated up-counter for this Trigger State, causes a Trigger Counter Comparison match to occur. 477 */ 478 #define LOBS_STATE_COUNTCOMP_VALUE_MASK (0xFFFFFFFFUL) 479 #define LOBS_STATE_COUNTCOMP_VALUE_SHIFT (0U) 480 #define LOBS_STATE_COUNTCOMP_VALUE_SET(x) (((uint32_t)(x) << LOBS_STATE_COUNTCOMP_VALUE_SHIFT) & LOBS_STATE_COUNTCOMP_VALUE_MASK) 481 #define LOBS_STATE_COUNTCOMP_VALUE_GET(x) (((uint32_t)(x) & LOBS_STATE_COUNTCOMP_VALUE_MASK) >> LOBS_STATE_COUNTCOMP_VALUE_SHIFT) 482 483 /* Bitfield definition for register of struct array STATE: EXTMASK */ 484 /* 485 * VALUE (RW) 486 * 487 * External Mask 488 */ 489 #define LOBS_STATE_EXTMASK_VALUE_MASK (0xFFFFFFFFUL) 490 #define LOBS_STATE_EXTMASK_VALUE_SHIFT (0U) 491 #define LOBS_STATE_EXTMASK_VALUE_SET(x) (((uint32_t)(x) << LOBS_STATE_EXTMASK_VALUE_SHIFT) & LOBS_STATE_EXTMASK_VALUE_MASK) 492 #define LOBS_STATE_EXTMASK_VALUE_GET(x) (((uint32_t)(x) & LOBS_STATE_EXTMASK_VALUE_MASK) >> LOBS_STATE_EXTMASK_VALUE_SHIFT) 493 494 /* Bitfield definition for register of struct array STATE: EXTCOMP */ 495 /* 496 * VALUE (RW) 497 * 498 * External Compare 499 */ 500 #define LOBS_STATE_EXTCOMP_VALUE_MASK (0xFFFFFFFFUL) 501 #define LOBS_STATE_EXTCOMP_VALUE_SHIFT (0U) 502 #define LOBS_STATE_EXTCOMP_VALUE_SET(x) (((uint32_t)(x) << LOBS_STATE_EXTCOMP_VALUE_SHIFT) & LOBS_STATE_EXTCOMP_VALUE_MASK) 503 #define LOBS_STATE_EXTCOMP_VALUE_GET(x) (((uint32_t)(x) & LOBS_STATE_EXTCOMP_VALUE_MASK) >> LOBS_STATE_EXTCOMP_VALUE_SHIFT) 504 505 /* Bitfield definition for register of struct array STATE: SIGMASK */ 506 /* 507 * NUM3 (RW) 508 * 509 * Select compare signal number3 510 */ 511 #define LOBS_STATE_SIGMASK_NUM3_MASK (0xFF000000UL) 512 #define LOBS_STATE_SIGMASK_NUM3_SHIFT (24U) 513 #define LOBS_STATE_SIGMASK_NUM3_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGMASK_NUM3_SHIFT) & LOBS_STATE_SIGMASK_NUM3_MASK) 514 #define LOBS_STATE_SIGMASK_NUM3_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGMASK_NUM3_MASK) >> LOBS_STATE_SIGMASK_NUM3_SHIFT) 515 516 /* 517 * NUM2 (RW) 518 * 519 * Select compare signal number2 520 */ 521 #define LOBS_STATE_SIGMASK_NUM2_MASK (0xFF0000UL) 522 #define LOBS_STATE_SIGMASK_NUM2_SHIFT (16U) 523 #define LOBS_STATE_SIGMASK_NUM2_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGMASK_NUM2_SHIFT) & LOBS_STATE_SIGMASK_NUM2_MASK) 524 #define LOBS_STATE_SIGMASK_NUM2_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGMASK_NUM2_MASK) >> LOBS_STATE_SIGMASK_NUM2_SHIFT) 525 526 /* 527 * NUM1 (RW) 528 * 529 * Select compare signal number1 530 */ 531 #define LOBS_STATE_SIGMASK_NUM1_MASK (0xFF00U) 532 #define LOBS_STATE_SIGMASK_NUM1_SHIFT (8U) 533 #define LOBS_STATE_SIGMASK_NUM1_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGMASK_NUM1_SHIFT) & LOBS_STATE_SIGMASK_NUM1_MASK) 534 #define LOBS_STATE_SIGMASK_NUM1_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGMASK_NUM1_MASK) >> LOBS_STATE_SIGMASK_NUM1_SHIFT) 535 536 /* 537 * NUM0 (RW) 538 * 539 * Select compare signal number0 540 */ 541 #define LOBS_STATE_SIGMASK_NUM0_MASK (0xFFU) 542 #define LOBS_STATE_SIGMASK_NUM0_SHIFT (0U) 543 #define LOBS_STATE_SIGMASK_NUM0_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGMASK_NUM0_SHIFT) & LOBS_STATE_SIGMASK_NUM0_MASK) 544 #define LOBS_STATE_SIGMASK_NUM0_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGMASK_NUM0_MASK) >> LOBS_STATE_SIGMASK_NUM0_SHIFT) 545 546 /* Bitfield definition for register of struct array STATE: COMPEN */ 547 /* 548 * EN (RW) 549 * 550 * Select compare signal number0-3 551 */ 552 #define LOBS_STATE_COMPEN_EN_MASK (0xFU) 553 #define LOBS_STATE_COMPEN_EN_SHIFT (0U) 554 #define LOBS_STATE_COMPEN_EN_SET(x) (((uint32_t)(x) << LOBS_STATE_COMPEN_EN_SHIFT) & LOBS_STATE_COMPEN_EN_MASK) 555 #define LOBS_STATE_COMPEN_EN_GET(x) (((uint32_t)(x) & LOBS_STATE_COMPEN_EN_MASK) >> LOBS_STATE_COMPEN_EN_SHIFT) 556 557 /* Bitfield definition for register of struct array STATE: SIGCOMP0 */ 558 /* 559 * VALUE0 (RW) 560 * 561 * Compare golden value for Signal Group signals[31:0]. 562 */ 563 #define LOBS_STATE_SIGCOMP0_VALUE0_MASK (0xFFFFFFFFUL) 564 #define LOBS_STATE_SIGCOMP0_VALUE0_SHIFT (0U) 565 #define LOBS_STATE_SIGCOMP0_VALUE0_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGCOMP0_VALUE0_SHIFT) & LOBS_STATE_SIGCOMP0_VALUE0_MASK) 566 #define LOBS_STATE_SIGCOMP0_VALUE0_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGCOMP0_VALUE0_MASK) >> LOBS_STATE_SIGCOMP0_VALUE0_SHIFT) 567 568 /* Bitfield definition for register of struct array STATE: SIGCOMP1 */ 569 /* 570 * VALUE1 (RW) 571 * 572 * Compare golden value for Signal Group signals[63:32]. 573 */ 574 #define LOBS_STATE_SIGCOMP1_VALUE1_MASK (0xFFFFFFFFUL) 575 #define LOBS_STATE_SIGCOMP1_VALUE1_SHIFT (0U) 576 #define LOBS_STATE_SIGCOMP1_VALUE1_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGCOMP1_VALUE1_SHIFT) & LOBS_STATE_SIGCOMP1_VALUE1_MASK) 577 #define LOBS_STATE_SIGCOMP1_VALUE1_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGCOMP1_VALUE1_MASK) >> LOBS_STATE_SIGCOMP1_VALUE1_SHIFT) 578 579 /* Bitfield definition for register of struct array STATE: SIGCOMP2 */ 580 /* 581 * VALUE2 (RW) 582 * 583 * Compare golden value for Signal Group signals[95:64]. 584 */ 585 #define LOBS_STATE_SIGCOMP2_VALUE2_MASK (0xFFFFFFFFUL) 586 #define LOBS_STATE_SIGCOMP2_VALUE2_SHIFT (0U) 587 #define LOBS_STATE_SIGCOMP2_VALUE2_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGCOMP2_VALUE2_SHIFT) & LOBS_STATE_SIGCOMP2_VALUE2_MASK) 588 #define LOBS_STATE_SIGCOMP2_VALUE2_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGCOMP2_VALUE2_MASK) >> LOBS_STATE_SIGCOMP2_VALUE2_SHIFT) 589 590 /* Bitfield definition for register of struct array STATE: SIGCOMP3 */ 591 /* 592 * VALUE3 (RW) 593 * 594 * Compare golden value for Signal Group signals[127:96]. 595 */ 596 #define LOBS_STATE_SIGCOMP3_VALUE3_MASK (0xFFFFFFFFUL) 597 #define LOBS_STATE_SIGCOMP3_VALUE3_SHIFT (0U) 598 #define LOBS_STATE_SIGCOMP3_VALUE3_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGCOMP3_VALUE3_SHIFT) & LOBS_STATE_SIGCOMP3_VALUE3_MASK) 599 #define LOBS_STATE_SIGCOMP3_VALUE3_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGCOMP3_VALUE3_MASK) >> LOBS_STATE_SIGCOMP3_VALUE3_SHIFT) 600 601 /* Bitfield definition for register: LAR */ 602 /* 603 * VALUE (RW) 604 * 605 * Lock Access Value 606 */ 607 #define LOBS_LAR_VALUE_MASK (0xFFFFFFFFUL) 608 #define LOBS_LAR_VALUE_SHIFT (0U) 609 #define LOBS_LAR_VALUE_SET(x) (((uint32_t)(x) << LOBS_LAR_VALUE_SHIFT) & LOBS_LAR_VALUE_MASK) 610 #define LOBS_LAR_VALUE_GET(x) (((uint32_t)(x) & LOBS_LAR_VALUE_MASK) >> LOBS_LAR_VALUE_SHIFT) 611 612 613 614 /* STATE register group index macro definition */ 615 #define LOBS_STATE_0 (0UL) 616 #define LOBS_STATE_1 (1UL) 617 #define LOBS_STATE_2 (2UL) 618 #define LOBS_STATE_3 (3UL) 619 #define LOBS_STATE_4 (4UL) 620 621 622 #endif /* HPM_LOBS_H */ 623