1 /****************************************************************************** 2 * @file core_pulp_cluster.h 3 * @brief CMSIS PULP Core Cluster Peripheral Access Layer Header File 4 * @version V0.0.1 5 * @date 04. April 2020 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2017 GreenWaves Technologies SAS. All rights reserved. 9 * Copyright (c) 2020 ETH Zurich 10 * 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the License); you may 14 * not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 */ 25 #ifndef __CLUSTER_PULP_H_GENERIC__ 26 #define __CLUSTER_PULP_H_GENERIC__ 27 28 #ifdef FEATURE_CLUSTER 29 30 #include "core_pulp.h" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /******************************************************************************* 37 * CMSIS definitions 38 ******************************************************************************/ 39 #define CLUSTER_ID 0 /**< CLuster ID */ 40 #define CLUSTER_CORES_NUM 8 /**< CLuster cores number */ 41 42 #define CLUSTER_HW_MUTEX_NUM 1 43 /** SoC events statically reserved by the runtime*/ 44 #define FC_CLUSTER_SW_NOTIF_EVENT 0 /**< Used to notify FC*/ 45 #define CLUSTER_CLUSTER_SW_NOTIF_EVENT 1 /**< Used to notify CLUSTER*/ 46 47 /** 48 \ingroup CMSIS_core_register 49 \defgroup CMSIS_core_base Core Definitions 50 \brief Definitions for base addresses, unions, and structures. 51 @{ 52 */ 53 /** 54 \brief Structure type to access the System Control Block (SCB). 55 */ 56 typedef struct 57 { 58 __OM uint32_t EOC; /*!< Offset: 0x000 (R/W ) CPUID Base Register */ 59 __IOM uint32_t _reserved0; /*!< Offset: 0x004 (R/W) reserved Register */ 60 __IOM uint32_t FETCH_EN; /*!< Offset: 0x008 (R/W) Interrupt Control and State Register */ 61 __IOM uint32_t _reserved1; /*!< Offset: 0x00C (R/W) reserved Register */ 62 __OM uint32_t EVENT; /*!< Offset: 0x010 (W) Event out Register */ 63 __IOM uint32_t _reserved2[3]; /*!< Offset: 0x014 (R/W) reserved Register */ 64 __OM uint32_t CLUSTER_CG; /*!< Offset: 0x020 (R/W) Event out Register */ 65 __IOM uint32_t _reserved3[7]; /*!< Offset: 0x024 (R/W) reserved Registers */ 66 __IOM uint32_t BOOT_ADDR[8]; /*!< Offset: 0x040 (R/W) Vector Table Offset Register */ 67 } SCB_Type; 68 69 /* SCB Registers Definitions */ 70 #define SCB_EOC_Pos 0U /*!< SCB EOC Position */ 71 #define SCB_EOC_Msk (1UL /* << SCB_EOC_Pos*/) /*!< SCB EOC Mask */ 72 73 #define SCB_FETCH_EN_Pos 0U /*!< SCB FETCH_EN Position */ 74 #define SCB_FETCH_EN_Msk (1UL /* << SCB_FETCH_EN_Pos*/) /*!< SCB FETCH_EN Mask */ 75 /*@} end of group CMSIS_FC_CTRL */ 76 77 /** 78 \ingroup CMSIS_core_register 79 \defgroup CMSIS_SCBC System Control Block for Icache (SCBC) 80 \brief Type definitions for the System Control Block Registers 81 @{ 82 */ 83 84 typedef struct 85 { 86 __IOM uint32_t ICACHE_ENABLE; /*!< Offset: 0x00 (R/W ) Cluster Icache Enable Register */ 87 __IOM uint32_t ICACHE_FLUSH; /*!< Offset: 0x04 (R/W) Cluster Icache Flush Register */ 88 __IOM uint32_t ICACHE_LX_SEL_FLUSH; /*!< Offset: 0x08 (R/W) Cluster Icache Level-X Flush Register or FC Flush Selected Address Register*/ 89 __IOM uint32_t ICACHE_SEL_FLUSH_STATUS; /*!< Offset: 0x0C (R/W) Cluster Icache Flush Selected Address Register or FC ICACHE status */ 90 __IOM uint32_t ICACHE_CNTS_CLEAR; /*!< Offset: 0x10 (R/W) Cluster Icache is private Icache */ 91 __IOM uint32_t ICACHE_CNTS_ENABLE; /*!< Offset: 0x10 (R/W) Cluster Icache is private Icache */ 92 } SCBC_Type; 93 94 /* SCBC Registers Definitions */ 95 #define SCBC_ENABLE_Pos 0U /*!< SCBC_ENABLE Position */ 96 #define SCBC_ENABLE_Msk (1UL /* << SCBC_ENABLE_Pos*/) /*!< SCBC_ENABLE Mask */ 97 98 #define SCBC_STATUS_Pos 0U /*!< SCBC_STATUS Position */ 99 #define SCBC_STATUS_Msk (1UL /* << SCBC_STATUS_Pos*/) /*!< SCBC_STATUS Mask */ 100 101 /*@} end of group CMSIS_SCBC */ 102 103 /** 104 \ingroup CMSIS_core_register 105 \defgroup CMSIS_EU_CORE_DEMUX Event Unit Core 106 \brief Type definitions for the event unit core Registers 107 @{ 108 */ 109 /** 110 \brief Structure type to access the EU_CORE_DEMUX. 111 */ 112 113 typedef struct { 114 __IOM uint32_t MASK; /**< EU_DEMUX mask register, offset: 0x00 */ 115 __IOM uint32_t MASK_AND; /**< EU_DEMUX mask and register, offset: 0x04 */ 116 __IOM uint32_t MASK_OR; /**< EU_DEMUX mask or register, offset: 0x08 */ 117 __IOM uint32_t MASK_IRQ; /**< EU_DEMUX mask irq register, offset: 0x0C */ 118 __IOM uint32_t MASK_IRQ_AND; /**< EU_DEMUX mask irq and register, offset: 0x10 */ 119 __IOM uint32_t MASK_IRQ_OR; /**< EU_DEMUX mask irq or register, offset: 0x14 */ 120 __IOM uint32_t STATUS; /**< EU_DEMUX Status register, offset: 0x18 */ 121 __IOM uint32_t BUFFER; /**< EU_DEMUX buffer register, offset: 0x1C */ 122 __IOM uint32_t BUFFER_MASKED; /**< EU_DEMUX buffer masked register, offset: 0x20 */ 123 __IOM uint32_t BUFFER_IRQ_MASKED; /**< EU_DEMUX buffer irq masked register, offset: 0x24 */ 124 __IOM uint32_t BUFFER_CLEAR; /**< EU_DEMUX buffer clear register, offset: 0x28 */ 125 __IOM uint32_t SW_EVENTS_MASK; /**< EU_DEMUX software event mask register, offset: 0x2C */ 126 __IOM uint32_t SW_EVENTS_MASK_AND; /**< EU_DEMUX software event mask and register, offset: 0x30 */ 127 __IOM uint32_t SW_EVENTS_MASK_OR; /**< EU_DEMUX software event mask or register, offset: 0x34 */ 128 __IOM uint32_t EVENT_WAIT; /**< EU_DEMUX event wait register, offset: 0x38 */ 129 __IOM uint32_t EVENT_WAIT_CLEAR; /**< EU_DEMUX event wait clear register, offset: 0x3C */ 130 __IOM uint32_t MASK_SEC_IRQ; /**< EU_DEMUX mask sec irq register, offset: 0x40 */ 131 132 } EU_CORE_DEMUX_Type; 133 134 /*@} end of group CMSIS_EU_CORE_DEMUX */ 135 136 /** 137 \ingroup CMSIS_core_register 138 \defgroup CMSIS_EU_SEC_DEMUX Event Unit Security 139 \brief Type definitions for the event unit security Registers 140 @{ 141 */ 142 /** 143 \brief Structure type to access the EU_SEC_DEMUX. 144 */ 145 typedef struct { 146 __IOM uint32_t MASK; /**< EU_SEC_DEMUX mask register, offset: 0x00 */ 147 __IOM uint32_t MASK_AND; /**< EU_SEC_DEMUX mask and register, offset: 0x04 */ 148 __IOM uint32_t MASK_OR; /**< EU_SEC_DEMUX mask or register, offset: 0x08 */ 149 } EU_SEC_DEMUX_Type; 150 151 #define EU_SEC_ELEM_NUM 8 152 153 /*@} end of group CMSIS_EU_DEMUX */ 154 155 /** 156 \ingroup CMSIS_core_register 157 \defgroup CMSIS_EU_LOOP_DEMUX Event Unit Loop 158 \brief Type definitions for the event unit Loop Registers 159 @{ 160 */ 161 /** 162 \brief Structure type to access the EU_LOOP_DEMUX. 163 */ 164 typedef struct { 165 __IOM uint32_t STATE; /**< EU_LOOP_DEMUX state register, offset: 0x00 */ 166 __IOM uint32_t START; /**< EU_LOOP_DEMUX start register, offset: 0x04 */ 167 __IOM uint32_t END; /**< EU_LOOP_DEMUX end register, offset: 0x08 */ 168 __IOM uint32_t INCR; /**< EU_LOOP_DEMUX increment register, offset: 0x0C */ 169 __IOM uint32_t CHUNK; /**< EU_LOOP_DEMUX chunk register, offset: 0x10 */ 170 __IOM uint32_t EPOCH; /**< EU_LOOP_DEMUX epoch register, offset: 0x14 */ 171 __IOM uint32_t SINGLE; /**< EU_LOOP_DEMUX single register, offset: 0x18 */ 172 } EU_LOOP_DEMUX_Type; 173 174 #define EU_LOOP_DEMUX_DONE_ 0x0 175 #define EU_LOOP_DEMUX_LOCKED_ 0x1 176 #define EU_LOOP_DEMUX_SKIP_ 0x2 177 178 /*@} end of group CMSIS_EU_SW_EVENTS_DEMUX */ 179 180 /** 181 \ingroup CMSIS_core_register 182 \defgroup CMSIS_EU_SW_EVENTS_DEMUX Event Unit Loop 183 \brief Type definitions for the event unit Loop Registers 184 @{ 185 */ 186 /** 187 \brief Structure type to access the EU_SW_EVENTS_DEMUX. 188 */ 189 typedef struct { 190 __IOM uint32_t TRIGGER_SET[8]; /**< EU_SW_EVENTS_DEMUX trigger set register, offset: 0x00 */ 191 __IOM uint32_t _reserved0[8]; /*!< Offset: 0x20 (R/W) Empty Registers */ 192 __IOM uint32_t TRIGGER_WAIT[8]; /**< EU_SW_EVENTS_DEMUX trigger wait register, offset: 0x40 */ 193 __IOM uint32_t _reserved1[8]; /*!< Offset: 0x60 (R/W) Empty Registers */ 194 __IOM uint32_t TRIGGER_CLR[8]; /**< EU_SW_EVENTS_DEMUX trigger clear register, offset: 0x80 */ 195 } EU_SW_EVENTS_DEMUX_Type; 196 197 /*@} end of group CMSIS_EU_SW_EVENTS_DEMUX */ 198 199 /** 200 \ingroup CMSIS_core_register 201 \defgroup CMSIS_EU_DISPATCH_DEMUX Event Unit Dispatch 202 \brief Type definitions for the event unit Dispatch Registers 203 @{ 204 */ 205 typedef struct { 206 __IOM uint32_t FIFO_ACCESS; /**< EU_DISPATCH_DEMUX fifo access register, offset: 0x00 */ 207 __IOM uint32_t TEAM_CONFIG; /**< EU_DISPATCH_DEMUX team config register, offset: 0x04 */ 208 } EU_DISPATCH_DEMUX_Type; 209 210 #define EU_DISPATCH_DEMUX_ELEM_NUM 8 211 212 /*@} end of group CMSIS_EU_DISPATCH_DEMUX */ 213 214 /** 215 \ingroup CMSIS_core_register 216 \defgroup CMSIS_EU_MUTEX_DEMUX Event Unit Hardware Mutex 217 \brief Type definitions for the event unit Dispatch Registers 218 @{ 219 */ 220 typedef struct { 221 __IOM uint32_t MUTEX[1]; /**< EU_MUTEX_DEMUX mutex register, offset: 0x00 */ 222 } EU_MUTEX_DEMUX_Type; 223 224 #define EU_MUTEX_DEMUX_ELEM_NUM 1 225 226 /*@} end of group CMSIS_EU_MUTEX_DEMUX */ 227 228 /** 229 \ingroup CMSIS_core_register 230 \defgroup CMSIS_EU_BARRIER_DEMUX Event Unit Barrier 231 \brief Type definitions for the event unit Barrier Registers 232 @{ 233 */ 234 typedef struct { 235 __IOM uint32_t TRIGGER_MASK; /**< EU_BARRIER_DEMUX triger mask register, offset: 0x00 */ 236 __IOM uint32_t STATUS; /**< EU_BARRIER_DEMUX status register, offset: 0x04 */ 237 __IOM uint32_t STATUS_SUMMRY; /**< EU_BARRIER_DEMUX status summary register, offset: 0x08 */ 238 __IOM uint32_t TARGET_MASK; /**< EU_BARRIER_DEMUX target mask register, offset: 0x0C */ 239 __IOM uint32_t TRIGGER; /**< EU_BARRIER_DEMUX trigger register, offset: 0x10 */ 240 __IOM uint32_t TRIGGER_SET; /**< EU_BARRIER_DEMUX trigger set register, offset: 0x14 */ 241 __IOM uint32_t TRIGGER_WAIT; /**< EU_BARRIER_DEMUX trigger wait register, offset: 0x18 */ 242 __IOM uint32_t TRIGGER_WAIT_CLEAR; /**< EU_BARRIER_DEMUX trigger clear register, offset: 0x1C */ 243 244 } EU_BARRIER_DEMUX_Type; 245 /* We have only one HW Barrier */ 246 247 /*@} end of group CMSIS_EU_BARRIER_DEMUX */ 248 249 /** 250 \ingroup CMSIS_core_register 251 \defgroup CMSIS_EU_SOC_EVENTS Event Unit Barrier 252 \brief Type definitions for the event unit Barrier Registers 253 @{ 254 */ 255 typedef struct { 256 __IM uint32_t CURRENT_EVENT; /**< EU_SOC_EVENTS current event register, offset: 0x00 */ 257 258 } EU_SOC_EVENTS_Type; 259 /* We have only one HW Barrier */ 260 261 #define EU_CURRENT_VALID_BIT_MASK (0x80000000U) 262 #define EU_CURRENT_VALID_BIT_SHIFT (31U) 263 #define EU_CURRENT_VALID_BIT(x) (((uint32_t)(((uint32_t)(x)) << EU_CURRENT_VALID_BIT_SHIFT)) & EU_CURRENT_VALID_BIT_MASK) 264 265 #define EU_CURRENT_SOC_EVENT_MASK 0xFF 266 267 /*@} end of group CMSIS_EU_SOC_EVENTS */ 268 269 /** 270 \ingroup CMSIS_core_register 271 \defgroup CMSIS_core_base Core Definitions 272 \brief Definitions for base addresses, unions, and structures. 273 @{ 274 */ 275 /** 276 \brief Structure type to access the direct memory access (DMAMCHAN). 277 */ 278 typedef struct 279 { 280 __IOM uint32_t CMD; /*!< Offset: 0x00 (R/W ) DMAMCHAN Command Base Register */ 281 __IOM uint32_t STATUS; /*!< Offset: 0x04 (R/W) DMAMCHAN Channle Status Register */ 282 } DMAMCHAN_Type; 283 284 /* DMAMCHAN Registers Definitions */ 285 #define DMAMCHAN_CMD_TID_Pos 0U /*!< DMAMCHAN TID Position */ 286 #define DMAMCHAN_CMD_TID_Msk (0xFUL /* << DMAMCHAN_CMD_TID_Pos*/) /*!< DMAMCHAN TID Mask */ 287 288 #define DMAMCHAN_CMD_BLE_Pos 21U /*!< DMAMCHAN Broadcast Lines Enable Position */ 289 #define DMAMCHAN_CMD_BLE_Msk (1UL << DMAMCHAN_CMD_BLE_Pos) /*!< DMAMCHAN CMD Broadcast Lines Enable Mask */ 290 291 #define DMAMCHAN_CMD_ILE_Pos 20U /*!< DMAMCHAN Intrrupt Line EnableID Position */ 292 #define DMAMCHAN_CMD_ILE_Msk (1UL << DMAMCHAN_CMD_ILE_Pos) /*!< DMAMCHAN Intrrupt Line Enable Mask */ 293 294 #define DMAMCHAN_CMD_ELE_Pos 19U /*!< DMAMCHAN CMD Event Line Enable Position */ 295 #define DMAMCHAN_CMD_ELE_Msk (1UL << DMAMCHAN_CMD_ELE_Pos) /*!< DMAMCHAN CMD Event Line Enable Mask */ 296 297 #define DMAMCHAN_CMD_2D_Pos 18U /*!< DMAMCHAN CMD 2D transfer Position */ 298 #define DMAMCHAN_CMD_2D_Msk (1UL << DMAMCHAN_CMD_2D_Pos) /*!< DMAMCHAN CMD 2D transfer Mask */ 299 300 #define DMAMCHAN_CMD_INC_Pos 17U /*!< DMAMCHAN CMD Increment Position */ 301 #define DMAMCHAN_CMD_INC_Msk (1UL << DMAMCHAN_CMD_INC_Pos) /*!< DMAMCHAN CMD Increment Mask */ 302 303 #define DMAMCHAN_CMD_TYP_Pos 16U /*!< DMAMCHAN CMD Type Position */ 304 #define DMAMCHAN_CMD_TYP_Msk (1UL << DMAMCHAN_CMD_TYP_Pos) /*!< DMAMCHAN CMD Type Mask */ 305 306 #define DMAMCHAN_CMD_LEN_Pos 0U /*!< DMAMCHAN CMD Length Position */ 307 #define DMAMCHAN_CMD_LEN_Msk (0xFFUL /*<< DMAMCHAN_EOC_Pos*/) /*!< DMAMCHAN CMD Length Mask */ 308 309 #define DMAMCHAN_CMD_2D_STRIDE_Pos 16U /*!< DMAMCHAN CMD 2D STRIDE Position */ 310 #define DMAMCHAN_CMD_2D_STRIDE_Msk (0xFFUL << DMAMCHAN_CMD_2D_STRIDE_Pos) /*!< DMAMCHAN CMD 2D STRIDE Mask */ 311 312 #define DMAMCHAN_CMD_2D_COUNT_Pos 0U /*!< DMAMCHAN CMD 2D COUNT Position */ 313 #define DMAMCHAN_CMD_2D_COUNT_Msk (0xFFUL /* << DMAMCHAN_CMD_2D_COUNT_Pos*/) /*!< DMAMCHAN CMD 2D COUNT Mask */ 314 315 /*@} end of group CMSIS_DMAMCHAN */ 316 317 /** 318 \ingroup CMSIS_core_register 319 \defgroup CMSIS_core_base Core Definitions 320 \brief Definitions for base addresses, unions, and structures. 321 @{ 322 */ 323 /** 324 \brief Structure type to access the direct memory access compressor (DMAMCHAN). 325 */ 326 typedef struct 327 { 328 /*!< Offset: 0x00 (W ) Compressor TCDM Address Register */ 329 __O uint32_t TCDM_ADDRESS; 330 /*!< Offset: 0x04 (W ) Compressor L2 Address Register */ 331 __O uint32_t L2_ADDRESS; 332 /*!< Offset: 0x08 (W ) Compressor configuration Register */ 333 __O uint32_t CONFIG; 334 // 0xC 335 __IOM uint32_t PAD0; 336 /*!< Offset: 0x10 (W ) Compressor LUT patterns Register */ 337 __O uint32_t LUT; 338 /*!< Offset: 0x14 (W ) Compressor compression special value Register */ 339 __O uint32_t SPECIAL; 340 /*!< Offset: 0x18 (R ) Compressor readen bits Register */ 341 __I uint32_t BIT_READ; 342 /*!< Offset: 0x1C (W ) Compressor transfer direction Register */ 343 __O uint32_t DIRECTION; 344 } DMAMCHAN_COMPRESSOR_Type; 345 346 typedef struct { 347 __O uint32_t TCDM_ADDR; 348 __O uint32_t L2_ADDR; 349 __O uint32_t CONF_REG; 350 __I uint32_t STAT_REG; 351 __O uint32_t LUT_REG; 352 __O uint32_t SYMBOL_REG; 353 __O uint32_t BIT_READ_REG; 354 __O uint32_t MODE_REG; 355 __O uint32_t SW_RST_REG; 356 __O uint32_t CLKEN_REG; 357 __O uint32_t TRIGGER_REG; 358 __IOM uint32_t PAD0; 359 __O uint32_t L2_COUNT_REG; 360 __O uint32_t L2_STRIDE_REG; 361 __O uint32_t TCDM_COUNT_REG; 362 __O uint32_t TCDM_STRIDE_REG; 363 } decompressor_t; 364 365 /** 366 \ingroup CMSIS_core_register 367 \defgroup CMSIS_CLUSTER_EU_CORES Cluster Event Unit Cores 368 \brief Type definitions for the event unit core Registers 369 @{ 370 */ 371 /** 372 \brief Structure type to access the CLUSTER_EU_CORES. 373 */ 374 375 typedef struct { 376 EU_CORE_DEMUX_Type CORES[CLUSTER_CORES_NUM]; /*!< Offset: 0x000 (R/W) Cluster Event Unit cores */ 377 378 } CLUSTER_EU_CORES_Type; 379 380 /*@} end of group CMSIS_CLUSTER_EU_CORE */ 381 382 #define CLUSTER_DISPATCH_IS_ENTRY_MASK (0x1U) 383 #define CLUSTER_DISPATCH_IS_ENTRY_SHIFT (0U) 384 #define CLUSTER_DISPATCH_IS_ENTRY(x) (((uint32_t)(((uint32_t)(x)) /* << CLUSTER_DISPATCH_IS_ENTRY_SHIFT */)) & CLUSTER_DISPATCH_IS_ENTRY_MASK) 385 386 #define CLUSTER_DISPATCH_ENTRY_ADDR_MASK (0x7FFFFFFEU) 387 #define CLUSTER_DISPATCH_ENTRY_ADDR_SHIFT (1U) 388 #define CLUSTER_DISPATCH_ADDR_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << CLUSTER_DISPATCH_ENTRY_ADDR_SHIFT)) & CLUSTER_DISPATCH_ENTRY_ADDR_MASK) 389 390 #define CLUSTER_DISPATCH_ENTRY_MASK (0x7FFFFFFFU) 391 #define CLUSTER_DISPATCH_ENTRY_SHIFT (0U) 392 #define CLUSTER_DISPATCH_ENTRY(x) (((uint32_t)(((uint32_t)(x)) /*<< CLUSTER_DISPATCH_ENTRY_SHIFT*/)) & CLUSTER_DISPATCH_ENTRY_MASK) 393 #define READ_CLUSTER_DISPATCH_ENTRY(x) (((uint32_t)(((uint32_t)(x)) & CLUSTER_DISPATCH_ENTRY_MASK)) /*>> CLUSTER_DISPATCH_ENTRY_SHIFT*/) 394 395 #define CLUSTER_DISPATCH_IS_JOB_MASK (0x80000000U) 396 #define CLUSTER_DISPATCH_IS_JOB_SHIFT (31U) 397 #define CLUSTER_DISPATCH_IS_JOB(x) (((uint32_t)(((uint32_t)(x)) << CLUSTER_DISPATCH_IS_JOB_SHIFT)) & CLUSTER_DISPATCH_IS_JOB_MASK) 398 399 /* Memory map */ 400 401 #define CLUSTER_BASE (ARCHI_CLUSTER_GLOBAL_ADDR(0)) /*!< CLUSTER Base Address */ 402 403 #define CLUSTER_SCB_BASE (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0)) /*!< CLUSTER System Control Block Base Address */ 404 #define CLUSTER_SCBC_BASE (ARCHI_ICACHE_CTRL_ADDR) /*!< CLUSTER System Control Block Cache Base Address */ 405 #define CLUSTER_SysTick_BASE (ARCHI_CLUSTER_TIMER_ADDR) /*!< CLUSTER SysTick Base Address */ 406 407 #define CLUSTER_EU_BARRIER_BASE (ARCHI_EU_ADDR + 0x400UL) /*!< CLUSTER Event Unit HW Barrier Base Address */ 408 #define CLUSTER_EU_SW_EVENTS_BASE (ARCHI_EU_ADDR + 0x600UL) /*!< CLUSTER Event Unit SW Events Base Address */ 409 #define CLUSTER_EU_SOC_EVENTS_BASE (ARCHI_EU_ADDR + 0x700UL) /*!< CLUSTER Event Unit SOC Events Base Address */ 410 #define CLUSTER_EU_EXT_EVENTS_BASE (ARCHI_EU_ADDR + 0x780UL) /*!< CLUSTER Event Unit EXT Events Base Address */ 411 412 #define CLUSTER_EU_CORE_DEMUX_BASE (ARCHI_DEMUX_PERIPHERALS_ADDR) /*!< CLUSTER Event Unit Core Demux Base Address */ 413 #define CLUSTER_EU_SEC_DEMUX_BASE (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x040UL) /*!< CLUSTER Event Unit Security Demux Base Address */ 414 #define CLUSTER_EU_LOOP_DEMUX_BASE (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x060UL) /*!< CLUSTER Event Unit Loop Demux Base Address */ 415 #define CLUSTER_EU_DISPATCH_DEMUX_BASE (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x080UL) /*!< CLUSTER Event Unit Dispatch Demux Base Address */ 416 #define CLUSTER_EU_MUTEX_DEMUX_BASE (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x0C0UL) /*!< CLUSTER Event Unit Mutex Demux Base Address */ 417 #define CLUSTER_EU_SW_EVENTS_DEMUX_BASE (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x100UL) /*!< CLUSTER Event Unit SW Events Demux Base Address */ 418 #define CLUSTER_EU_BARRIER_DEMUX_BASE (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x200UL) /*!< CLUSTER Event Unit Barrier Demux Base Address */ 419 420 /* Cluster Core Structrue definitions */ 421 #define CLUSTER_EU_SW_EVENTS ((EU_SW_EVENTS_DEMUX_Type *) CLUSTER_EU_SW_EVENTS_BASE) /*!< EU_SW_EVENTS_DEMUX configuration struct */ 422 #define EU_CORES ((CLUSTER_EU_CORES_Type *) ARCHI_EU_ADDR) /*!< CLUSTER_EU_CORES configuration struct */ 423 #define SCB ((SCB_Type *) CLUSTER_SCB_BASE ) /*!< CLUSTER SCB configuration struct */ 424 #define CLUSTER_SCBC ((SCBC_Type *) CLUSTER_SCBC_BASE ) /*!< CLUSTER SCBC configuration struct */ 425 426 #define CLUSTER_SysTick ((SysTick_Type *) CLUSTER_SysTick_BASE ) /*!< SysTick configuration struct */ 427 #define CLUSTER_TIMERL ((TimerL_Type *) CLUSTER_SysTick_BASE ) /*!< SysTick configuration struct */ 428 #define CLUSTER_TIMERH ((TimerH_Type *) CLUSTER_SysTick_BASE ) /*!< SysTick configuration struct */ 429 430 #ifdef __cplusplus 431 } 432 #endif 433 434 #endif 435 436 #endif /* __CLUSTER_PULP_H_GENERIC */ 437