1 /** 2 ***************************************************************************** 3 * @file cmem7_spi.h 4 * 5 * @brief CMEM7 SPI header file 6 * 7 * 8 * @version V1.0 9 * @date 3. September 2013 10 * 11 * @note 12 * 13 ***************************************************************************** 14 * @attention 15 * 16 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 17 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 18 * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 19 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 20 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 21 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 22 * 23 * <h2><center>© COPYRIGHT 2013 Capital-micro </center></h2> 24 ***************************************************************************** 25 */ 26 27 #ifndef __CMEM7_SPI_H 28 #define __CMEM7_SPI_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* Includes ------------------------------------------------------------------*/ 35 #include "cmem7.h" 36 #include "cmem7_conf.h" 37 38 39 #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI0) || \ 40 ((PERIPH) == SPI1)) 41 42 43 /** @defgroup SPI_MODE 44 * @{ 45 */ 46 #define SPI_MODE_CPOL_0_CPHA_0 0 /*!< CPOL : Idle clock level is low level. 47 CPHA : Capture data at the first edge */ 48 #define SPI_MODE_CPOL_0_CPHA_1 1 /*!< CPOL : Idle clock level is low level. 49 CPHA : Capture data at the second edge */ 50 #define SPI_MODE_CPOL_1_CPHA_0 2 /*!< CPOL : Idle clock level is high level. 51 CPHA : Capture data at the first edge */ 52 #define SPI_MODE_CPOL_1_CPHA_1 3 /*!< CPOL : Idle clock level is high level. 53 CPHA : Capture data at the first edge */ 54 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_CPOL_0_CPHA_0) || \ 55 ((MODE) == SPI_MODE_CPOL_0_CPHA_1) || \ 56 ((MODE) == SPI_MODE_CPOL_1_CPHA_0) || \ 57 ((MODE) == SPI_MODE_CPOL_1_CPHA_1)) 58 /** 59 * @} 60 */ 61 62 /** @defgroup SPI_INT 63 * @{ 64 */ 65 #define SPI_INT_RX_FIFO_UNDERFLOW 0x00000001 66 #define SPI_INT_RX_FIFO_OVERFLOW 0x00000002 67 #define SPI_INT_RX_FIFO_ALMOST_FULL 0x00000004 68 #define SPI_INT_TX_FIFO_UNDERFLOW 0x00000008 69 #define SPI_INT_TX_FIFO_OVERFLOW 0x00000010 70 #define SPI_INT_TX_FIFO_ALMOST_FULL 0x00000020 71 #define SPI_INT_DONE 0x00000040 72 #define SPI_INT_ALL 0x0000007F 73 74 #define IS_SPI_INT(INT) (((INT) != 0) && (((INT) & ~SPI_INT_ALL) == 0)) 75 /** 76 * @} 77 */ 78 79 /** 80 * @brief SPI initialization structure 81 */ 82 typedef struct 83 { 84 uint8_t SPI_Mode; /*!< indicates SPI's CPOL and CPHA, ref as @ref SPI_MODE */ 85 BOOL SPI_RxEn; /*!< indicates if SPI receiver is enabled or not */ 86 uint8_t SPI_BitLength; /*!< bit length while transmitting and receiving */ 87 uint8_t SPI_Gap; /*!< cycle number between continuous data frame */ 88 uint8_t SPI_ClockDividor; /*!< SPI clock dividor, 1 / ((1 + DIV) * 2) */ 89 } SPI_InitTypeDef; 90 /** 91 * @} 92 */ 93 94 /** 95 * @brief SPI initialization 96 * @note This function should be called at first before any other interfaces. 97 * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1 98 * @param[in] init A pointer to structure SPI_InitTypeDef 99 * @retval None 100 */ 101 void SPI_Init(SPI0_Type* SPIx, SPI_InitTypeDef *init); 102 103 /** 104 * @brief Enable or disable SPI. 105 * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1 106 * @param[in] Enable The bit indicates if the specific SPI is enable or not 107 * @retval None 108 */ 109 void SPI_Enable(SPI0_Type* SPIx, BOOL enable); 110 111 /** 112 * @brief Enable or disable SPI interrupt. 113 * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1 114 * @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int 115 * @param[in] Enable The bit indicates if specific interrupts are enable or not 116 * @retval None 117 */ 118 void SPI_EnableInt(SPI0_Type* SPIx, uint32_t Int, BOOL enable); 119 120 /** 121 * @brief Check specific interrupts are set or not 122 * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1 123 * @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int 124 * @retval BOOL The bit indicates if specific interrupts are set or not 125 */ 126 BOOL SPI_GetIntStatus(SPI0_Type* SPIx, uint32_t Int); 127 128 /** 129 * @brief Clear specific interrupts 130 * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1 131 * @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int 132 * @retval None 133 */ 134 void SPI_ClearInt(SPI0_Type* SPIx, uint32_t Int); 135 136 /** 137 * @brief Read data from SPI FIFO 138 * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1 139 * @param[in] size Expected data size to be read 140 * @param[out] data A user-allocated buffer to fetch data to be read 141 * @retval uint8_t Actual read data size 142 */ 143 uint8_t SPI_ReadFifo(SPI0_Type* SPIx, uint8_t size, uint32_t* data); 144 145 /** 146 * @brief Write data to SPI FIFO 147 * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1 148 * @param[in] size Expected data size to be written 149 * @param[in] data A pointer to the data to be written 150 * @retval uint8_t Actual written data size 151 */ 152 uint8_t SPI_WriteFifo(SPI0_Type* SPIx, uint8_t Size, uint32_t* data); 153 154 /** 155 * @brief send a SPI transcation request 156 * @param[in] SPIx SPI peripheral, which is SPI0 or SPI1 157 * @param[in] size Expected data size to be written and read 158 * @retval BOOL The bit indicates if the request is sent 159 */ 160 BOOL SPI_Transcation(SPI0_Type* SPIx, uint8_t size); 161 162 #ifdef __cplusplus 163 } 164 #endif 165 166 #endif /*__CMEM7_SPI_H */ 167 168