1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file hal_spi.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SPI 5 /// FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 #ifndef __HAL_SPI_H 21 #define __HAL_SPI_H 22 23 // Files includes 24 #include "types.h" 25 #include "reg_spi.h" 26 27 //////////////////////////////////////////////////////////////////////////////// 28 /// @addtogroup MM32_Hardware_Abstract_Layer 29 /// @{ 30 31 //////////////////////////////////////////////////////////////////////////////// 32 /// @defgroup SPI_HAL 33 /// @brief SPI HAL modules 34 /// @{ 35 36 //////////////////////////////////////////////////////////////////////////////// 37 /// @defgroup SPI_Exported_Types 38 /// @{ 39 40 //////////////////////////////////////////////////////////////////////////////// 41 /// @brief SPI mode enum definition 42 //////////////////////////////////////////////////////////////////////////////// 43 typedef enum { 44 SPI_Mode_Slave = 0x0000, ///< SPI slave mode 45 SPI_Mode_Master = SPI_GCR_MODE ///< SPI master mode 46 } SPI_Mode_TypeDef; 47 48 //////////////////////////////////////////////////////////////////////////////// 49 /// @brief SPI data size enum definition 50 //////////////////////////////////////////////////////////////////////////////// 51 typedef enum { 52 SPI_DataSize_8b = 0x0000, ///< 8 bits valid data 53 SPI_DataSize_32b = SPI_GCR_DWSEL ///< 32 bits valid data 54 } SPI_DataSize_TypeDef; 55 56 //////////////////////////////////////////////////////////////////////////////// 57 /// @brief SPI clock polarity enum definition 58 //////////////////////////////////////////////////////////////////////////////// 59 typedef enum { 60 SPI_CPOL_Low = 0x0000, ///< The clock is low in idle state. 61 SPI_CPOL_High = SPI_CCR_CPOL ///< The clock is high in idle state. 62 } SPI_CPOL_TypeDef; 63 64 //////////////////////////////////////////////////////////////////////////////// 65 /// @brief SPI clock phase enum definition 66 //////////////////////////////////////////////////////////////////////////////// 67 typedef enum { 68 SPI_CPHA_2Edge = 0x0000, ///< Data sampling starts from the second clock edge. 69 SPI_CPHA_1Edge = SPI_CCR_CPHA ///< Data sampling starts from the first clock edge. 70 } SPI_CPHA_TypeDef; 71 72 //////////////////////////////////////////////////////////////////////////////// 73 /// @brief SPI nss control mode enum definition 74 //////////////////////////////////////////////////////////////////////////////// 75 typedef enum { 76 SPI_NSS_Soft = 0x0000, 77 SPI_NSS_Hard = SPI_GCR_NSS 78 } SPI_NSS_TypeDef; 79 80 //////////////////////////////////////////////////////////////////////////////// 81 /// @brief SPI baud rate prescaler enum definition 82 //////////////////////////////////////////////////////////////////////////////// 83 typedef enum { 84 SPI_BaudRatePrescaler_2 = 0x0002, ///< SCK clock devide by 2 85 SPI_BaudRatePrescaler_4 = 0x0004, ///< SCK clock devide by 4 86 SPI_BaudRatePrescaler_8 = 0x0008, ///< SCK clock devide by 7 87 SPI_BaudRatePrescaler_16 = 0x0010, ///< SCK clock devide by 16 88 SPI_BaudRatePrescaler_32 = 0x0020, ///< SCK clock devide by 32 89 SPI_BaudRatePrescaler_64 = 0x0040, ///< SCK clock devide by 64 90 SPI_BaudRatePrescaler_128 = 0x0080, ///< SCK clock devide by 128 91 SPI_BaudRatePrescaler_256 = 0x0100 ///< SCK clock devide by 256 92 } SPI_BaudRatePrescaler_TypeDef; 93 94 //////////////////////////////////////////////////////////////////////////////// 95 /// @brief SPI first bit enum definition 96 //////////////////////////////////////////////////////////////////////////////// 97 typedef enum { 98 SPI_FirstBit_MSB = 0x0000, ///< Data transfers start from MSB 99 SPI_FirstBit_LSB = SPI_CCR_LSBFE ///< Data transfers start from LSB 100 } SPI_FirstBit_TypeDef; 101 102 //////////////////////////////////////////////////////////////////////////////// 103 /// @brief SPI FIFO trigger level enum definition 104 //////////////////////////////////////////////////////////////////////////////// 105 typedef enum { 106 SPI_RXTLF = SPI_GCR_RXTLF_Half, ///< RX FIFO trigger level 107 SPI_TXTLF = SPI_GCR_TXTLF_Half ///< TX FIFO trigger level 108 } SPI_TLF_TypeDef; 109 110 //////////////////////////////////////////////////////////////////////////////// 111 /// @brief SPI bit derection enum definition 112 //////////////////////////////////////////////////////////////////////////////// 113 typedef enum { 114 SPI_Direction_Rx, ///< Receive enable 115 SPI_Direction_Tx, ///< Transmit enable 116 SPI_Disable_Rx, ///< Receive disable 117 SPI_Disable_Tx ///< Transmit disable 118 } SPI_Direction_TypeDef; 119 120 //////////////////////////////////////////////////////////////////////////////// 121 /// @brief SPI flag enum definition 122 //////////////////////////////////////////////////////////////////////////////// 123 typedef enum { 124 SPI_FLAG_RXAVL = SPI_SR_RXAVL, ///< Receive 1 byte available data flag 125 SPI_FLAG_TXEPT = SPI_SR_TXEPT, ///< Transmitter empty flag 126 SPI_FLAG_TXFULL = SPI_SR_TXFULL, ///< Transmitter FIFO full status flag 127 SPI_FLAG_RXAVL_4BYTE = SPI_SR_RXAVL_4BYTE ///< Receive 4 bytes available data flag 128 } SPI_FLAG_TypeDef; 129 130 //////////////////////////////////////////////////////////////////////////////// 131 /// @brief SPI slave mode data edge adjust enum definition 132 //////////////////////////////////////////////////////////////////////////////// 133 typedef enum { 134 SPI_SlaveAdjust_LOW, ///< SPI slave mode data edge adjust in low speed mode 135 SPI_SlaveAdjust_FAST ///< SPI slave mode data edge adjust in fast speed mode 136 } SPI_SlaveAdjust_TypeDef; 137 138 //////////////////////////////////////////////////////////////////////////////// 139 /// @brief SPI data edge adjust enum definition 140 //////////////////////////////////////////////////////////////////////////////// 141 typedef enum { 142 SPI_DataEdgeAdjust_LOW, ///< SPI data edge adjust in low speed mode 143 SPI_DataEdgeAdjust_FAST ///< SPI data edge adjust in fast speed mode 144 } SPI_DataEdgeAdjust_TypeDef; 145 146 //////////////////////////////////////////////////////////////////////////////// 147 /// @brief SPI interruput enum definition 148 //////////////////////////////////////////////////////////////////////////////// 149 typedef enum { 150 SPI_IT_TXEPT = 0x40, ///< Transmitter empty interrupt 151 SPI_IT_RXFULL = 0x20, ///< RX FIFO full interrupt 152 SPI_IT_RXMATCH = 0x10, ///< Receive data match the RXDNR number interrut 153 SPI_IT_RXOERR = 0x08, ///< Receive overrun error interrupt 154 SPI_IT_UNDERRUN = 0x04, ///< Underrun interrupt 155 SPI_IT_RX = 0x02, ///< Receive available data interrupt 156 SPI_IT_TX = 0x01 ///< Transmit FIFO available interrupt 157 } SPI_IT_TypeDef; 158 159 160 typedef enum { 161 I2S_Standard_Phillips = 0x0000, 162 I2S_Standard_MSB = 0x0010, 163 I2S_Standard_LSB = 0x0020, 164 I2S_Standard_PCMShort = 0x0030, 165 I2S_Standard_PCMLong = 0x00B0, 166 } SPI_I2S_STANDARD_TypeDef; 167 168 169 typedef enum { 170 I2S_DataFormat_16b = 0x0000, 171 I2S_DataFormat_16bextended = 0x0001, 172 I2S_DataFormat_24b = 0x0003, 173 I2S_DataFormat_32b = 0x0005, 174 } SPI_I2S_DATAFORMAT_TypeDef; 175 typedef enum { 176 I2S_AudioFreq_192k = (192000), 177 I2S_AudioFreq_96k = (96000), 178 I2S_AudioFreq_48k = (48000), 179 I2S_AudioFreq_44k = (44100), 180 I2S_AudioFreq_32k = (32000), 181 I2S_AudioFreq_24k = (24000), 182 I2S_AudioFreq_22k = (22050), 183 I2S_AudioFreq_16k = (16000), 184 I2S_AudioFreq_11k = (11025), 185 I2S_AudioFreq_12k = (12000), 186 I2S_AudioFreq_8k = (8000), 187 I2S_AudioFreq_4k = (4000), 188 I2S_AudioFreq_Default = (2), 189 } SPI_I2S_AUDIO_FREQ_TypeDef; 190 typedef enum { 191 I2S_Mode_SlaveTx = 0x0000, 192 I2S_Mode_SlaveRx = 0x0100, 193 I2S_Mode_MasterTx = 0x0200, 194 I2S_Mode_MasterRx = 0x0300, 195 } SPI_I2S_TRANS_MODE_TypeDef; 196 197 typedef enum { 198 I2S_MCLKOutput_Enable = 0x0800, 199 I2S_MCLKOutput_Disable = 0x0000, 200 } SPI_I2S_MCLK_OUTPUT_TypeDef; 201 202 typedef enum { 203 I2S_CPOL_Low = 0x0000, ///< The clock is low in idle state. 204 I2S_CPOL_High = SPI_CCR_CPOL ///< The clock is high in idle state. 205 } SPI_I2S_CPOL_TypeDef; 206 207 208 209 //////////////////////////////////////////////////////////////////////////////// 210 /// @brief SPI Init structure definition 211 //////////////////////////////////////////////////////////////////////////////// 212 typedef struct { 213 SPI_Mode_TypeDef SPI_Mode; ///< Specifies the SPI operating mode 214 SPI_DataSize_TypeDef SPI_DataSize; ///< Specifies the SPI available data size 215 u8 SPI_DataWidth; ///< SPI data length 216 SPI_CPOL_TypeDef SPI_CPOL; ///< Specifies the serial clock steady state 217 SPI_CPHA_TypeDef SPI_CPHA; ///< Specifies the clock active edge for the bit capture 218 SPI_NSS_TypeDef SPI_NSS; ///< Specifies whether the NSS signal is managed by hardware or by software 219 SPI_BaudRatePrescaler_TypeDef SPI_BaudRatePrescaler; ///< Specifies the Baud Rate prescaler value which will be 220 ///< used to configure the transmit and receive SCK clock 221 SPI_FirstBit_TypeDef SPI_FirstBit; ///< Specifies whether data transfers start from MSB or LSB bit 222 // u16 SPI_length; 223 } SPI_InitTypeDef; 224 //////////////////////////////////////////////////////////////////////////////// 225 /// @brief I2S Init structure definition 226 //////////////////////////////////////////////////////////////////////////////// 227 typedef struct { 228 SPI_I2S_TRANS_MODE_TypeDef I2S_Mode; ///< Specifies the I2S operating mode. 229 SPI_I2S_STANDARD_TypeDef I2S_Standard; ///< Specifies the standard used for the I2S communication. 230 SPI_I2S_DATAFORMAT_TypeDef I2S_DataFormat; ///< Specifies the data format for the I2S communication. 231 SPI_I2S_MCLK_OUTPUT_TypeDef I2S_MCLKOutput; ///< Specifies whether the I2S MCLK output is enabled or not. 232 SPI_I2S_AUDIO_FREQ_TypeDef I2S_AudioFreq; ///< Specifies the frequency selected for the I2S communication. 233 SPI_I2S_CPOL_TypeDef I2S_CPOL; ///< Specifies the idle state of the I2S clock. 234 } I2S_InitTypeDef; 235 /// @} 236 237 //////////////////////////////////////////////////////////////////////////////// 238 /// @defgroup SPI_Exported_Constants 239 /// @{ 240 241 //////////////////////////////////////////////////////////////////////////////// 242 /// @defgroup SPI_Register_Mask 243 /// @{ 244 245 #define GCR_Mask ((u32)0x0FFF) 246 #define CCR_Mask ((u32)0x003F) 247 #define BRR_Mask ((u32)0xFFFF) 248 #define ECR_Mask ((u32)0x001F) 249 250 /// @} 251 252 253 // SPI_7bit_8bit data width 254 #define SPI_DataWidth_1b ((u16)0x0001) 255 #define SPI_DataWidth_2b ((u16)0x0002) 256 #define SPI_DataWidth_3b ((u16)0x0003) 257 #define SPI_DataWidth_4b ((u16)0x0004) 258 #define SPI_DataWidth_5b ((u16)0x0005) 259 #define SPI_DataWidth_6b ((u16)0x0006) 260 #define SPI_DataWidth_7b ((u16)0x0007) 261 #define SPI_DataWidth_8b ((u16)0x0008) 262 #define SPI_DataWidth_9b ((u16)0x0009) 263 #define SPI_DataWidth_10b ((u16)0x000a) 264 #define SPI_DataWidth_11b ((u16)0x000b) 265 #define SPI_DataWidth_12b ((u16)0x000c) 266 #define SPI_DataWidth_13b ((u16)0x000d) 267 #define SPI_DataWidth_14b ((u16)0x000e) 268 #define SPI_DataWidth_15b ((u16)0x000f) 269 #define SPI_DataWidth_16b ((u16)0x0010) 270 #define SPI_DataWidth_17b ((u16)0x0011) 271 #define SPI_DataWidth_18b ((u16)0x0012) 272 #define SPI_DataWidth_19b ((u16)0x0013) 273 #define SPI_DataWidth_20b ((u16)0x0014) 274 #define SPI_DataWidth_21b ((u16)0x0015) 275 #define SPI_DataWidth_22b ((u16)0x0016) 276 #define SPI_DataWidth_23b ((u16)0x0017) 277 #define SPI_DataWidth_24b ((u16)0x0018) 278 #define SPI_DataWidth_25b ((u16)0x0019) 279 #define SPI_DataWidth_26b ((u16)0x001a) 280 #define SPI_DataWidth_27b ((u16)0x001b) 281 #define SPI_DataWidth_28b ((u16)0x001c) 282 #define SPI_DataWidth_29b ((u16)0x001d) 283 #define SPI_DataWidth_30b ((u16)0x001e) 284 #define SPI_DataWidth_31b ((u16)0x001f) 285 #define SPI_DataWidth_32b ((u16)0x0000) 286 287 288 289 /// @} 290 291 //////////////////////////////////////////////////////////////////////////////// 292 /// @defgroup SPI_Exported_Variables 293 /// @{ 294 295 #ifdef _HAL_SPI_C_ 296 #define GLOBAL 297 #else 298 #define GLOBAL extern 299 #endif 300 301 #undef GLOBAL 302 303 /// @} 304 305 //////////////////////////////////////////////////////////////////////////////// 306 /// @defgroup SPI_Exported_Functions 307 /// @{ 308 309 void SPI_DeInit(SPI_TypeDef* spi); 310 void SPI_Init(SPI_TypeDef* spi, SPI_InitTypeDef* init_struct); 311 void SPI_StructInit(SPI_InitTypeDef* init_struct); 312 void SPI_Cmd(SPI_TypeDef* spi, FunctionalState state); 313 void SPI_ITConfig(SPI_TypeDef* spi, u8 interrupt, FunctionalState state); 314 void SPI_DMACmd(SPI_TypeDef* spi, FunctionalState state); 315 void SPI_FifoTrigger(SPI_TypeDef* spi, SPI_TLF_TypeDef fifo_trigger_value, FunctionalState state); 316 void SPI_SendData(SPI_TypeDef* spi, u32 data); 317 void SPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state); 318 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* spi, SPI_NSS_TypeDef nss); 319 320 void SPI_BiDirectionalLineConfig(SPI_TypeDef* spi, SPI_Direction_TypeDef direction); 321 void SPI_ClearITPendingBit(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt); 322 void SPI_RxBytes(SPI_TypeDef* spi, u16 number); 323 void SPI_SlaveAdjust(SPI_TypeDef* spi, SPI_SlaveAdjust_TypeDef adjust_value); 324 325 bool SPI_DataSizeConfig(SPI_TypeDef* spi, u8 data_size); 326 void SPI_DataSizeTypeConfig(SPI_TypeDef* spi, SPI_DataSize_TypeDef SPI_DataSize); 327 u32 SPI_ReceiveData(SPI_TypeDef* spi); 328 329 FlagStatus SPI_GetFlagStatus(SPI_TypeDef* spi, SPI_FLAG_TypeDef flag); 330 331 ITStatus SPI_GetITStatus(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt); 332 333 //////////////////////////////////////////////////////////////////////////////// 334 // Extended function interface 335 //////////////////////////////////////////////////////////////////////////////// 336 void exSPI_ITCmd(SPI_TypeDef* spi, FunctionalState state); 337 void exSPI_ITConfig(SPI_TypeDef* spi, SPI_IT_TypeDef interrput, FunctionalState state); 338 void exSPI_DMACmd(SPI_TypeDef* spi, FunctionalState state); 339 void exSPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state); 340 void exSPI_DataEdgeAdjust(SPI_TypeDef* spi, SPI_DataEdgeAdjust_TypeDef adjust_value); 341 void I2S_Cmd(SPI_TypeDef* spi, FunctionalState state); 342 void I2S_Init(SPI_TypeDef* spi, I2S_InitTypeDef* I2S_InitStruct); 343 /// @} 344 345 /// @} 346 347 /// @} 348 349 //////////////////////////////////////////////////////////////////////////////// 350 #endif //__HAL_SPI_H 351 //////////////////////////////////////////////////////////////////////////////// 352