1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_spi.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_SPI_H 22 #define __REG_SPI_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 40 41 42 43 44 //////////////////////////////////////////////////////////////////////////////// 45 /// @brief SPI Base Address Definition 46 //////////////////////////////////////////////////////////////////////////////// 47 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) ///< Base Address: 0x40003800 48 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) ///< Base Address: 0x400013000 49 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) ///< Base Address: 0x40003C000 50 51 52 53 54 //////////////////////////////////////////////////////////////////////////////// 55 /// @brief SPI Register Structure Definition 56 //////////////////////////////////////////////////////////////////////////////// 57 #undef USENCOMBINEREGISTER 58 #undef USENNEWREGISTER 59 #undef USENOLDREGISTER 60 #define USENCOMBINEREGISTER 61 #ifdef USENCOMBINEREGISTER 62 typedef struct { 63 union { 64 __IO u32 TDR; ///< SPI transmit data register, offset: 0x00 65 __IO u32 TXREG; 66 }; 67 union { 68 __IO u32 RDR; ///< SPI receive data register, offset: 0x04 69 __IO u32 RXREG; 70 }; 71 union { 72 __IO u32 SR; ///< SPI current state register, offset: 0x08 73 __IO u32 CSTAT; 74 }; 75 union { 76 __IO u32 ISR; ///< SPI interruput state register, offset: 0x0C 77 __IO u32 INTSTAT; 78 }; 79 union { 80 __IO u32 IER; ///< SPI interruput enable register, offset: 0x10 81 __IO u32 INTEN; 82 }; 83 union { 84 __IO u32 ICR; ///< SPI interruput control register, offset: 0x14 85 __IO u32 INTCLR; 86 }; 87 union { 88 __IO u32 GCR; ///< SPI global control register, offset: 0x18 89 __IO u32 GCTL; 90 }; 91 union { 92 __IO u32 CCR; ///< SPI common control register, offset: 0x1C 93 __IO u32 CCTL; 94 }; 95 union { 96 __IO u32 BRR; ///< SPI baud rate control register, offset: 0x20 97 __IO u32 SPBRG; 98 }; 99 union { 100 __IO u32 RDNR; ///< SPI receive data number register, offset: 0x24 101 __IO u32 RXDNR; 102 }; 103 union { 104 __IO u32 NSSR; ///< SPI chip select register, offset: 0x28 105 __IO u32 SCSR; 106 }; 107 union { 108 __IO u32 ECR; ///< SPI extand control register, offset: 0x2C 109 __IO u32 EXTCTL; 110 }; 111 __IO u32 CFGR; ///< I2S configuration register, offset: 0x30 112 } SPI_TypeDef; 113 #endif 114 #ifdef USENNEWREGISTER 115 typedef struct { 116 __IO u32 TDR; ///< SPI transmit data register, offset: 0x00 117 __IO u32 RDR; ///< SPI receive data register, offset: 0x04 118 __IO u32 SR; ///< SPI current state register, offset: 0x08 119 __IO u32 ISR; ///< SPI interruput state register, offset: 0x0C 120 __IO u32 IER; ///< SPI interruput enable register, offset: 0x10 121 __IO u32 ICR; ///< SPI interruput control register, offset: 0x14 122 __IO u32 GCR; ///< SPI global control register, offset: 0x18 123 __IO u32 CCR; ///< SPI common control register, offset: 0x1C 124 __IO u32 BRR; ///< SPI baud rate control register, offset: 0x20 125 __IO u32 RDNR; ///< SPI receive data number register, offset: 0x24 126 __IO u32 NSSR; ///< SPI chip select register, offset: 0x28 127 __IO u32 ECR; ///< SPI extand control register, offset: 0x2C 128 } SPI_TypeDef; 129 #endif 130 #ifdef USENOLDREGISTER 131 typedef struct { 132 __IO u32 TXREG; ///< SPI transmit data register, offset: 0x00 133 __IO u32 RXREG; ///< SPI receive data register, offset: 0x04 134 __IO u32 CSTAT; ///< SPI current state register, offset: 0x08 135 __IO u32 INTSTAT; ///< SPI interruput state register, offset: 0x0C 136 __IO u32 INTEN; ///< SPI interruput enable register, offset: 0x10 137 __IO u32 INTCLR; ///< SPI interruput control register, offset: 0x14 138 __IO u32 GCTL; ///< SPI global control register, offset: 0x18 139 __IO u32 CCTL; ///< SPI common control register, offset: 0x1C 140 __IO u32 SPBRG; ///< SPI baud rate control register, offset: 0x20 141 __IO u32 RXDNR; ///< SPI receive data number register, offset: 0x24 142 __IO u32 NSSR; ///< SPI chip select register, offset: 0x28 143 __IO u32 EXTCTL; ///< SPI extand control register, offset: 0x2C 144 } SPI_TypeDef; 145 #endif 146 147 148 //////////////////////////////////////////////////////////////////////////////// 149 /// @brief SPI type pointer Definition 150 //////////////////////////////////////////////////////////////////////////////// 151 #define SPI2 ((SPI_TypeDef*) SPI2_BASE) 152 #define SPI1 ((SPI_TypeDef*) SPI1_BASE) 153 #define SPI3 ((SPI_TypeDef*) SPI3_BASE) 154 //////////////////////////////////////////////////////////////////////////////// 155 /// @brief SPI_TDR Register Bit Definition 156 //////////////////////////////////////////////////////////////////////////////// 157 #define SPI_TDR_TXREG_Pos (0) 158 #define SPI_TDR_TXREG (0xFFFFFFFFU << SPI_TDR_TXREG_Pos) ///< Transmit data register 159 160 //////////////////////////////////////////////////////////////////////////////// 161 /// @brief SPI_RDR Register Bit Definition 162 //////////////////////////////////////////////////////////////////////////////// 163 #define SPI_RDR_RXREG_Pos (0) 164 #define SPI_RDR_RXREG (0xFFFFFFFFU << SPI_RDR_RXREG_Pos) ///< Receive data register 165 166 //////////////////////////////////////////////////////////////////////////////// 167 /// @brief SPI_SR Register Bit Definition 168 //////////////////////////////////////////////////////////////////////////////// 169 #define SPI_SR_TXEPT_Pos (0) 170 #define SPI_SR_TXEPT (0x01U << SPI_SR_TXEPT_Pos) ///< Transmitter empty bit 171 #define SPI_SR_RXAVL_Pos (1) 172 #define SPI_SR_RXAVL (0x01U << SPI_SR_RXAVL_Pos) ///< Receive available byte data message 173 #define SPI_SR_TXFULL_Pos (2) 174 #define SPI_SR_TXFULL (0x01U << SPI_SR_TXFULL_Pos) ///< Transmitter FIFO full status bit 175 #define SPI_SR_RXAVL_4BYTE_Pos (3) 176 #define SPI_SR_RXAVL_4BYTE (0x01U << SPI_SR_RXAVL_4BYTE_Pos) ///< Receive available 4 byte data message 177 #define SPI_SR_TXFADDR_Pos (4) 178 #define SPI_SR_TXFADDR (0x0FU << SPI_SR_TXFADDR_Pos) ///< Transmit FIFO address 179 #define SPI_SR_RXFADDR_Pos (8) 180 #define SPI_SR_RXFADDR (0x0FU << SPI_SR_RXFADDR_Pos) ///< Receive FIFO address 181 #define SPI_SR_BUSY_Pos (12) 182 #define SPI_SR_BUSY (0x01U << SPI_SR_BUSY_Pos) ///< Data transfer flag 183 #define SPI_SR_CHSIDE_Pos (13) 184 #define SPI_SR_CHSIDE (0x01U << SPI_SR_CHSIDE_Pos) ///< transmission channel 185 //////////////////////////////////////////////////////////////////////////////// 186 /// @brief SPI_ISR Register Bit Definition 187 //////////////////////////////////////////////////////////////////////////////// 188 #define SPI_ISR_TX_INTF_Pos (0) 189 #define SPI_ISR_TX_INTF (0x01U << SPI_ISR_TX_INTF_Pos) ///< Transmit FIFO available interrupt flag bit 190 #define SPI_ISR_RX_INTF_Pos (1) 191 #define SPI_ISR_RX_INTF (0x01U << SPI_ISR_RX_INTF_Pos) ///< Receive data available interrupt flag bit 192 #define SPI_ISR_UNDERRUN_INTF_Pos (2) 193 #define SPI_ISR_UNDERRUN_INTF (0x01U << SPI_ISR_UNDERRUN_INTF_Pos) ///< SPI underrun interrupt flag bit 194 #define SPI_ISR_RXOERR_INTF_Pos (3) 195 #define SPI_ISR_RXOERR_INTF (0x01U << SPI_ISR_RXOERR_INTF_Pos) ///< Receive overrun error interrupt flag bit 196 #define SPI_ISR_RXMATCH_INTF_Pos (4) 197 #define SPI_ISR_RXMATCH_INTF (0x01U << SPI_ISR_RXMATCH_INTF_Pos) ///< Receive data match the RXDNR number, the receive process will be completed and generate the interrupt 198 #define SPI_ISR_RXFULL_INTF_Pos (5) 199 #define SPI_ISR_RXFULL_INTF (0x01U << SPI_ISR_RXFULL_INTF_Pos) ///< RX FIFO full interrupt flag bit 200 #define SPI_ISR_TXEPT_INTF_Pos (6) 201 #define SPI_ISR_TXEPT_INTF (0x01U << SPI_ISR_TXEPT_INTF_Pos) ///< Transmitter empty interrupt flag bit 202 #define SPI_ISR_FRE_INTF_Pos (7) 203 #define SPI_ISR_FRE_INTF (0x01U << SPI_ISR_FRE_INTF_Pos) ///< I2S frame transmission error flag bit 204 //////////////////////////////////////////////////////////////////////////////// 205 /// @brief SPI_IER Register Bit Definition 206 //////////////////////////////////////////////////////////////////////////////// 207 #define SPI_IER_TX_IEN_Pos (0) 208 #define SPI_IER_TX_IEN (0x01U << SPI_IER_TX_IEN_Pos) ///< Transmit FIFO empty interrupt enable bit 209 #define SPI_IER_RX_IEN_Pos (1) 210 #define SPI_IER_RX_IEN (0x01U << SPI_IER_RX_IEN_Pos) ///< Receive FIFO interrupt enable bit 211 #define SPI_IER_UNDERRUN_IEN_Pos (2) 212 #define SPI_IER_UNDERRUN_IEN (0x01U << SPI_IER_UNDERRUN_IEN_Pos) ///< Transmitter underrun interrupt enable bit 213 #define SPI_IER_RXOERR_IEN_Pos (3) 214 #define SPI_IER_RXOERR_IEN (0x01U << SPI_IER_RXOERR_IEN_Pos) ///< Overrun error interrupt enable bit 215 #define SPI_IER_RXMATCH_IEN_Pos (4) 216 #define SPI_IER_RXMATCH_IEN (0x01U << SPI_IER_RXMATCH_IEN_Pos) ///< Receive data complete interrupt enable bit 217 #define SPI_IER_RXFULL_IEN_Pos (5) 218 #define SPI_IER_RXFULL_IEN (0x01U << SPI_IER_RXFULL_IEN_Pos) ///< Receive FIFO full interrupt enable bit 219 #define SPI_IER_TXEPT_IEN_Pos (6) 220 #define SPI_IER_TXEPT_IEN (0x01U << SPI_IER_TXEPT_IEN_Pos) ///< Transmit empty interrupt enable bit 221 #define SPI_IER_FRE_IEN_Pos (7) 222 #define SPI_IER_FRE_IEN (0x01U << SPI_IER_FRE_IEN_Pos) ///< I2S frame transmission interrupt enable bit 223 //////////////////////////////////////////////////////////////////////////////// 224 /// @brief SPI_ICR Register Bit Definition 225 //////////////////////////////////////////////////////////////////////////////// 226 #define SPI_ICR_TX_ICLR_Pos (0) 227 #define SPI_ICR_TX_ICLR (0x01U << SPI_ICR_TX_ICLR_Pos) ///< Transmitter FIFO empty interrupt clear bit 228 #define SPI_ICR_RX_ICLR_Pos (1) 229 #define SPI_ICR_RX_ICLR (0x01U << SPI_ICR_RX_ICLR_Pos) ///< Receive interrupt clear bit 230 #define SPI_ICR_UNDERRUN_ICLR_Pos (2) 231 #define SPI_ICR_UNDERRUN_ICLR (0x01U << SPI_ICR_UNDERRUN_ICLR_Pos) ///< Transmitter underrun interrupt clear bit 232 #define SPI_ICR_RXOERR_ICLR_Pos (3) 233 #define SPI_ICR_RXOERR_ICLR (0x01U << SPI_ICR_RXOERR_ICLR_Pos) ///< Overrun error interrupt clear bit 234 #define SPI_ICR_RXMATCH_ICLR_Pos (4) 235 #define SPI_ICR_RXMATCH_ICLR (0x01U << SPI_ICR_RXMATCH_ICLR_Pos) ///< Receive completed interrupt clear bit 236 #define SPI_ICR_RXFULL_ICLR_Pos (5) 237 #define SPI_ICR_RXFULL_ICLR (0x01U << SPI_ICR_RXFULL_ICLR_Pos) ///< Receiver buffer full interrupt clear bit 238 #define SPI_ICR_TXEPT_ICLR_Pos (6) 239 #define SPI_ICR_TXEPT_ICLR (0x01U << SPI_ICR_TXEPT_ICLR_Pos) ///< Transmitter empty interrupt clear bit 240 #define SPI_ICR_FRE_ICLR_Pos (7) 241 #define SPI_ICR_FRE_ICLR (0x01U << SPI_ICR_FRE_ICLR_Pos) ///< I2S frame transmission interrupt clear bit 242 //////////////////////////////////////////////////////////////////////////////// 243 /// @brief SPI_GCR Register Bit Definition 244 //////////////////////////////////////////////////////////////////////////////// 245 #define SPI_GCR_SPIEN_Pos (0) 246 #define SPI_GCR_SPIEN (0x01U << SPI_GCR_SPIEN_Pos) ///< SPI select bit 247 #define SPI_GCR_IEN_Pos (1) 248 #define SPI_GCR_IEN (0x01U << SPI_GCR_IEN_Pos) ///< SPI interrupt enable bit 249 #define SPI_GCR_MODE_Pos (2) 250 #define SPI_GCR_MODE (0x01U << SPI_GCR_MODE_Pos) ///< Master mode bit 251 #define SPI_GCR_TXEN_Pos (3) 252 #define SPI_GCR_TXEN (0x01U << SPI_GCR_TXEN_Pos) ///< Transmit enable bit 253 #define SPI_GCR_RXEN_Pos (4) 254 #define SPI_GCR_RXEN (0x01U << SPI_GCR_RXEN_Pos) ///< Receive enable bit 255 256 #define SPI_GCR_RXTLF_Pos (5) 257 #define SPI_GCR_RXTLF (0x03U << SPI_GCR_RXTLF_Pos) ///< RX FIFO trigger level bit 258 #define SPI_GCR_RXTLF_One (0x00U << SPI_GCR_RXTLF_Pos) ///< 259 #define SPI_GCR_RXTLF_Half (0x01U << SPI_GCR_RXTLF_Pos) ///< 260 261 #define SPI_GCR_TXTLF_Pos (7) 262 #define SPI_GCR_TXTLF (0x03U << SPI_GCR_TXTLF_Pos) ///< TX FIFO trigger level bit 263 #define SPI_GCR_TXTLF_One (0x00U << SPI_GCR_TXTLF_Pos) ///< 264 #define SPI_GCR_TXTLF_Half (0x01U << SPI_GCR_TXTLF_Pos) ///< 265 #define SPI_GCR_DMAEN_Pos (9) 266 #define SPI_GCR_DMAEN (0x01U << SPI_GCR_DMAEN_Pos) ///< DMA access mode enable 267 #define SPI_GCR_NSS_Pos (10) 268 #define SPI_GCR_NSS (0x01U << SPI_GCR_NSS_Pos) ///< NSS select signal that from software or hardware 269 #define SPI_GCR_DWSEL_Pos (11) 270 #define SPI_GCR_DWSEL (0x01U << SPI_GCR_DWSEL_Pos) ///< Valid byte or double-word data select signal 271 272 #define SPI_GCR_NSSTOG_Pos (12) 273 #define SPI_GCR_NSSTOG (0x01U << SPI_GCR_NSSTOG_Pos) ///< Slave select toggle 274 #define SPI_GCR_PAD_SEL_Pos (13) 275 #define SPI_GCR_PAD_SEL (0x1FU << SPI_GCR_PAD_SEL_Pos) ///< Bus mapping transformation 276 //////////////////////////////////////////////////////////////////////////////// 277 /// @brief SPI_CCR Register Bit Definition 278 //////////////////////////////////////////////////////////////////////////////// 279 #define SPI_CCR_CPHA_Pos (0) 280 #define SPI_CCR_CPHA (0x01U << SPI_CCR_CPHA_Pos) ///< Clock phase select bit 281 #define SPI_CCR_CPOL_Pos (1) 282 #define SPI_CCR_CPOL (0x01U << SPI_CCR_CPOL_Pos) ///< Clock polarity select bit 283 #define SPI_CCR_LSBFE_Pos (2) 284 #define SPI_CCR_LSBFE (0x01U << SPI_CCR_LSBFE_Pos) ///< LSI first enable bit 285 #define SPI_CCR_SPILEN_Pos (3) 286 #define SPI_CCR_SPILEN (0x01U << SPI_CCR_SPILEN_Pos) ///< SPI character length bit 287 #define SPI_CCR_RXEDGE_Pos (4) 288 #define SPI_CCR_RXEDGE (0x01U << SPI_CCR_RXEDGE_Pos) ///< Receive data edge select 289 #define SPI_CCR_TXEDGE_Pos (5) 290 #define SPI_CCR_TXEDGE (0x01U << SPI_CCR_TXEDGE_Pos) ///< Transmit data edge select 291 292 #define SPI_CCR_CPHASEL_Pos (6) 293 #define SPI_CCR_CPHASEL (0x01U << SPI_CCR_CPHASEL) ///< CPHA polarity select 294 295 #define SPI_CCR_HISPD_Pos (7) 296 #define SPI_CCR_HISPD (0x01U << SPI_CCR_HISPD) ///< High speed slave mode 297 298 //////////////////////////////////////////////////////////////////////////////// 299 /// @brief SPI_BRR Register Bit Definition 300 //////////////////////////////////////////////////////////////////////////////// 301 #define SPI_BRR_DIVF_Pos (0) 302 #define SPI_BRR_DIVF (0xFFFFU << SPI_BRR_DIVF_Pos) ///< SPI baud rate control register for baud rate 303 304 //////////////////////////////////////////////////////////////////////////////// 305 /// @brief SPI_RDNR Register Bit Definition 306 //////////////////////////////////////////////////////////////////////////////// 307 #define SPI_RDNR_RDN_Pos (0) 308 #define SPI_RDNR_RDN (0xFFFFU << SPI_RDNR_RDN_Pos) ///< The register is used to hold a count of to be received bytes in next receive process 309 310 //////////////////////////////////////////////////////////////////////////////// 311 /// @brief SPI_NSSR Register Bit Definition 312 //////////////////////////////////////////////////////////////////////////////// 313 #define SPI_NSSR_NSS_Pos (0) 314 #define SPI_NSSR_NSS (0xFFU << SPI_NSSR_NSS_Pos) ///< Chip select output signal in Master mode 315 316 //////////////////////////////////////////////////////////////////////////////// 317 /// @brief SPI_ECR Register Bit Definition 318 //////////////////////////////////////////////////////////////////////////////// 319 #define SPI_ECR_EXTLEN_Pos (0) 320 #define SPI_ECR_EXTLEN (0x1FU << SPI_ECR_EXTLEN_Pos) ///< control SPI data length 321 322 //////////////////////////////////////////////////////////////////////////////// 323 /// @brief I2S_CFGR Register Bit Definition 324 //////////////////////////////////////////////////////////////////////////////// 325 326 #define I2SCFGR_CLEAR_Mask ((u32)0xFE00F388) 327 #define I2S_CFGR_CHLEN_Pos (0) 328 #define I2S_CFGR_CHLEN (0x01U << I2S_CFGR_CHLEN_Pos) ///< Vocal tract length 329 #define I2S_CFGR_DATLEN_Pos (1) 330 #define I2S_CFGR_DATLEN_16 (0x00U << I2S_CFGR_DATLEN_Pos) ///< Audio data width 16 331 #define I2S_CFGR_DATLEN_24 (0x01U << I2S_CFGR_DATLEN_Pos) ///< Audio data width 24 332 #define I2S_CFGR_DATLEN_32 (0x02U << I2S_CFGR_DATLEN_Pos) ///< Audio data width 32 333 334 #define I2S_CFGR_I2SSTD_Pos (4) 335 #define I2S_CFGR_I2SSTD_PCM (0x00U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection PCM standard 336 #define I2S_CFGR_I2SSTD_MSB_R (0x01U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection Right alignment (MSB) standard 337 #define I2S_CFGR_I2SSTD_MSB_L (0x02U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection Left aligned (MSB) standard 338 #define I2S_CFGR_I2SSTD_Philips (0x03U << I2S_CFGR_I2SSTD_Pos) ///< I2S selection Philips standard 339 340 #define I2S_CFGR_PCMSYNC_Pos (6) 341 #define I2S_CFGR_PCMSYNC (0x01U << I2S_CFGR_PCMSYNC_Pos) ///< PCM frame synchronization mode 342 #define I2S_CFGR_SPI_I2S_Pos (10) 343 #define I2S_CFGR_SPI_I2S (0x01U << I2S_CFGR_SPI_I2S_Pos) ///< SPI/I2S module function selection 344 #define I2S_CFGR_MCKOE_Pos (11) 345 #define I2S_CFGR_MCKOE (0x01U << I2S_CFGR_MCKOE_Pos) ///< I2S master clock output enable 346 #define I2S_CFGR_I2SDIV_Pos (16) 347 #define I2S_CFGR_I2SDIV (0x1FFU << I2S_CFGR_I2SDIV_Pos) ///< The frequency division 348 349 350 351 /// @} 352 353 /// @} 354 355 /// @} 356 357 //////////////////////////////////////////////////////////////////////////////// 358 #endif 359 //////////////////////////////////////////////////////////////////////////////// 360