1 //########################################################################### 2 // 3 // FILE: F2837xD_dma.h 4 // 5 // TITLE: DMA Register Definitions. 6 // 7 //########################################################################### 8 // $TI Release: F2837xD Support Library v3.05.00.00 $ 9 // $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ 10 // $Copyright: 11 // Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ 12 // 13 // Redistribution and use in source and binary forms, with or without 14 // modification, are permitted provided that the following conditions 15 // are met: 16 // 17 // Redistributions of source code must retain the above copyright 18 // notice, this list of conditions and the following disclaimer. 19 // 20 // Redistributions in binary form must reproduce the above copyright 21 // notice, this list of conditions and the following disclaimer in the 22 // documentation and/or other materials provided with the 23 // distribution. 24 // 25 // Neither the name of Texas Instruments Incorporated nor the names of 26 // its contributors may be used to endorse or promote products derived 27 // from this software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 // $ 41 //########################################################################### 42 43 #ifndef __F2837xD_DMA_H__ 44 #define __F2837xD_DMA_H__ 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 51 //--------------------------------------------------------------------------- 52 // DMA Individual Register Bit Definitions: 53 54 struct MODE_BITS { // bits description 55 Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select 56 Uint16 rsvd1:2; // 6:5 Reserved 57 Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable 58 Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable 59 Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode 60 Uint16 ONESHOT:1; // 10 One Shot Mode Bit 61 Uint16 CONTINUOUS:1; // 11 Continuous Mode Bit 62 Uint16 rsvd2:2; // 13:12 Reserved 63 Uint16 DATASIZE:1; // 14 Data Size Mode Bit 64 Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit 65 }; 66 67 union MODE_REG { 68 Uint16 all; 69 struct MODE_BITS bit; 70 }; 71 72 struct CONTROL_BITS { // bits description 73 Uint16 RUN:1; // 0 Run Bit 74 Uint16 HALT:1; // 1 Halt Bit 75 Uint16 SOFTRESET:1; // 2 Soft Reset Bit 76 Uint16 PERINTFRC:1; // 3 Interrupt Force Bit 77 Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit 78 Uint16 rsvd2:2; // 6:5 Reserved 79 Uint16 ERRCLR:1; // 7 Error Clear Bit 80 Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit 81 Uint16 SYNCFLG:1; // 9 Sync Flag Bit 82 Uint16 SYNCERR:1; // 10 Sync Error Flag Bit 83 Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit 84 Uint16 BURSTSTS:1; // 12 Burst Status Bit 85 Uint16 RUNSTS:1; // 13 Run Status Bit 86 Uint16 OVRFLG:1; // 14 Overflow Flag Bit 87 Uint16 rsvd1:1; // 15 Reserved 88 }; 89 90 union CONTROL_REG { 91 Uint16 all; 92 struct CONTROL_BITS bit; 93 }; 94 95 struct DMACTRL_BITS { // bits description 96 Uint16 HARDRESET:1; // 0 Hard Reset Bit 97 Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit 98 Uint16 rsvd1:14; // 15:2 Reserved 99 }; 100 101 union DMACTRL_REG { 102 Uint16 all; 103 struct DMACTRL_BITS bit; 104 }; 105 106 struct DEBUGCTRL_BITS { // bits description 107 Uint16 rsvd1:15; // 14:0 Reserved 108 Uint16 FREE:1; // 15 Debug Mode Bit 109 }; 110 111 union DEBUGCTRL_REG { 112 Uint16 all; 113 struct DEBUGCTRL_BITS bit; 114 }; 115 116 struct PRIORITYCTRL1_BITS { // bits description 117 Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit 118 Uint16 rsvd1:15; // 15:1 Reserved 119 }; 120 121 union PRIORITYCTRL1_REG { 122 Uint16 all; 123 struct PRIORITYCTRL1_BITS bit; 124 }; 125 126 struct PRIORITYSTAT_BITS { // bits description 127 Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits 128 Uint16 rsvd1:1; // 3 Reserved 129 Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits 130 Uint16 rsvd2:9; // 15:7 Reserved 131 }; 132 133 union PRIORITYSTAT_REG { 134 Uint16 all; 135 struct PRIORITYSTAT_BITS bit; 136 }; 137 138 struct BURST_SIZE_BITS { // bits description 139 Uint16 BURSTSIZE:5; // 4:0 Burst Transfer Size 140 Uint16 rsvd1:11; // 15:5 Reserved 141 }; 142 143 union BURST_SIZE_REG { 144 Uint16 all; 145 struct BURST_SIZE_BITS bit; 146 }; 147 148 struct BURST_COUNT_BITS { // bits description 149 Uint16 BURSTCOUNT:5; // 4:0 Burst Transfer Count 150 Uint16 rsvd1:11; // 15:5 Reserved 151 }; 152 153 union BURST_COUNT_REG { 154 Uint16 all; 155 struct BURST_COUNT_BITS bit; 156 }; 157 158 struct CH_REGS { 159 union MODE_REG MODE; // Mode Register 160 union CONTROL_REG CONTROL; // Control Register 161 union BURST_SIZE_REG BURST_SIZE; // Burst Size Register 162 union BURST_COUNT_REG BURST_COUNT; // Burst Count Register 163 int16 SRC_BURST_STEP; // Source Burst Step Register 164 int16 DST_BURST_STEP; // Destination Burst Step Register 165 Uint16 TRANSFER_SIZE; // Transfer Size Register 166 Uint16 TRANSFER_COUNT; // Transfer Count Register 167 int16 SRC_TRANSFER_STEP; // Source Transfer Step Register 168 int16 DST_TRANSFER_STEP; // Destination Transfer Step Register 169 Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register 170 Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register 171 int16 SRC_WRAP_STEP; // Source Wrap Step Register 172 Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register 173 Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register 174 int16 DST_WRAP_STEP; // Destination Wrap Step Register 175 Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register 176 Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register 177 Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register 178 Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register 179 Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register 180 Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register 181 Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register 182 Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register 183 }; 184 185 struct DMA_REGS { 186 union DMACTRL_REG DMACTRL; // DMA Control Register 187 union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register 188 Uint16 rsvd0; // Reserved 189 Uint16 rsvd1; // Reserved 190 union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register 191 Uint16 rsvd2; // Reserved 192 union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register 193 Uint16 rsvd3[25]; // Reserved 194 struct CH_REGS CH1; // DMA Channel 1 Registers 195 struct CH_REGS CH2; // DMA Channel 2 Registers 196 struct CH_REGS CH3; // DMA Channel 3 Registers 197 struct CH_REGS CH4; // DMA Channel 4 Registers 198 struct CH_REGS CH5; // DMA Channel 5 Registers 199 struct CH_REGS CH6; // DMA Channel 6 Registers 200 }; 201 202 //--------------------------------------------------------------------------- 203 // DMA External References & Function Declarations: 204 // 205 extern volatile struct DMA_REGS DmaRegs; 206 #ifdef __cplusplus 207 } 208 #endif /* extern "C" */ 209 210 #endif 211 212 //=========================================================================== 213 // End of file. 214 //=========================================================================== 215