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/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/
A Dhpm_bmon_regs.h15 __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ member
A Dhpm_mon_regs.h15 __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ member
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/
A Dhpm_bmon_regs.h15 __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ member
A Dhpm_pmon_regs.h15 __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ member
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/
A Dhpm_bmon_regs.h15 __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ member
A Dhpm_pmon_regs.h15 __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ member
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/
A Dhpm_bmon_regs.h15 __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ member
A Dhpm_pmon_regs.h15 __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ member
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/
A Dhpm_bmon_regs.h15 __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ member
A Dhpm_pmon_regs.h15 __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ member
/bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/
A Dcore_pulp_cluster.h120 __IOM uint32_t STATUS; /**< EU_DEMUX Status register, offset: 0x18 */ member
236 __IOM uint32_t STATUS; /**< EU_BARRIER_DEMUX status register, offset: 0x04 */ member
281 __IOM uint32_t STATUS; /*!< Offset: 0x04 (R/W) DMAMCHAN Channle Status Register */ member
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/
A Dhpm_mon_regs.h15 __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ member
/bsp/CME_M7/StdPeriph_Driver/inc/
A Dcmem7_i2c.h98 #define IS_I2C_STATUS(STATUS) (((STATUS) != 0) && (((STATUS) & ~I2C_STATUS_ALL) == 0)) argument
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/
A Dht32f1xxxx_aes.h128 #define IS_AES_STATUS(STATUS) ((STATUS == AES_SR_IFEMPTY) || \ argument
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/
A Dht32f5xxxx_aes.h135 #define IS_AES_STATUS(STATUS) ((STATUS == AES_SR_IFEMPTY) || \ argument
/bsp/efm32/
A Dmma7455l.h23 #define STATUS 0x09 //09 Status registers (Read only) macro
/bsp/rm48x50/HALCoGen/include/
A Dreg_crc.h49 uint32 STATUS; /**< 0x0028: Interrupt Status Register >**/ member
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Dramecc.h169 __I RAMECC_STATUS_Type STATUS; /**< \brief Offset: 0x3 (R/ 8) Status */ member
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Dramecc.h169 __I RAMECC_STATUS_Type STATUS; /**< \brief Offset: 0x3 (R/ 8) Status */ member
A Dtc.h529 uint32_t STATUS:1; /*!< bit: 3 STATUS */ member
777 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ member
803 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ member
827 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ member
/bsp/microchip/same54/bsp/include/component/
A Dramecc.h169 __I RAMECC_STATUS_Type STATUS; /**< \brief Offset: 0x3 (R/ 8) Status */ member
A Dtc.h529 uint32_t STATUS:1; /*!< bit: 3 STATUS */ member
777 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ member
803 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ member
827 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ member
/bsp/CME_M7/StdPeriph_Driver/src/
A Dcmem7_flash.c31 uint16_t STATUS; /*!< status register */ member
/bsp/microchip/samc21/bsp/samc21/include/component/
A Ddivas.h179 __IO DIVAS_STATUS_Type STATUS; /**< \brief Offset: 0x04 (R/W 8) Status */ member
A Dtc.h507 uint32_t STATUS:1; /*!< bit: 3 STATUS */ member
755 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ member
781 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ member
805 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ member

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