1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_syscfg.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_SYSCFG_H 22 #define __REG_SYSCFG_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 40 41 42 43 44 45 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) ///< Base Address: 0x40010000 46 47 48 49 50 51 52 //////////////////////////////////////////////////////////////////////////////// 53 /// @brief SysTem Configuration Register Structure Definition 54 //////////////////////////////////////////////////////////////////////////////// 55 typedef struct { 56 union { 57 __IO u32 CFGR; ///< SYSCFG configuration register offset: 0x00 58 __IO u32 CFGR1; 59 }; 60 __IO u32 RESERVED0x04; ///< RESERVED register offset: 0x04 61 __IO u32 EXTICR[4]; ///< SYSCFG configuration register offset: 0x08-0x14 62 __IO u32 CFGR2; ///< SYSCFG configuration2 register offset: 0x18 63 __IO u32 PDETCSR; ///< SYSCFG Power Detect configuration stautus reg offset: 0x1C 64 __IO u32 VOSDLY; ///< SYSCFG VOSDLY Counter register offset: 0x20 65 } SYSCFG_TypeDef; 66 67 68 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 69 70 71 72 //////////////////////////////////////////////////////////////////////////////// 73 ///@brief System Configuration (SYSCFG) 74 //////////////////////////////////////////////////////////////////////////////// 75 76 /// @brief SYSCFG_CFGR Register Bit definition 77 #define SYSCFG_CFGR_MEM_MODE_Pos (0) 78 #define SYSCFG_CFGR_MEM_MODE ((u32)0x00000003) ///< SYSCFG_Memory Remap Config 79 #define SYSCFG_CFGR_MEM_MODE_0 ((u32)0x00000001) ///< SYSCFG_Memory Remap Config Bit 0 80 #define SYSCFG_CFGR_MEM_MODE_1 ((u32)0x00000002) ///< SYSCFG_Memory Remap Config Bit 1 81 /// 82 83 #define SYSCFG_CFGR_FSMC_SYNC_EN_Pos (27) 84 #define SYSCFG_CFGR_FSMC_SYNC_EN (0x01U << SYSCFG_CFGR_FSMC_SYNC_EN_Pos)///< FSMC SYNC Enable 85 #define SYSCFG_CFGR_FSMC_AF_ADDR_Pos (28) 86 #define SYSCFG_CFGR_FSMC_AF_ADDR (0x01U << SYSCFG_CFGR_FSMC_AF_ADDR_Pos)///< FSMC Databus AF Address 87 #define SYSCFG_CFGR_FSMC_MODE_Pos (29) 88 #define SYSCFG_CFGR_FSMC_MODE ((u32)0x03<<SYSCFG_CFGR_FSMC_MODE_Pos) ///< FSMC Interface Mode Config 89 #define SYSCFG_CFGR_FSMC_MODE0 ((u32)0x00<<SYSCFG_CFGR_FSMC_MODE_Pos) ///< FSMC Mode Config Mode 0 90 #define SYSCFG_CFGR_FSMC_MODE1 ((u32)0x01<<SYSCFG_CFGR_FSMC_MODE_Pos) ///< FSMC Mode Config Mode 1 91 92 93 /// @brief SYSCFG_EXTICR1 Register Bit definition 94 #define SYSCFG_EXTICR1_EXTI0 ((u16)0x000F) ///< EXTI 0 configuration 95 #define SYSCFG_EXTICR1_EXTI1 ((u16)0x00F0) ///< EXTI 1 configuration 96 #define SYSCFG_EXTICR1_EXTI2 ((u16)0x0F00) ///< EXTI 2 configuration 97 #define SYSCFG_EXTICR1_EXTI3 ((u16)0xF000) ///< EXTI 3 configuration 98 99 /// @brief EXTI0 configuration 100 #define SYSCFG_EXTICR1_EXTI0_PA ((u16)0x0000) ///< PA[0] pin 101 #define SYSCFG_EXTICR1_EXTI0_PB ((u16)0x0001) ///< PB[0] pin 102 #define SYSCFG_EXTICR1_EXTI0_PC ((u16)0x0002) ///< PC[0] pin 103 #define SYSCFG_EXTICR1_EXTI0_PD ((u16)0x0003) ///< PD[0] pin 104 105 /// @brief EXTI1 configuration 106 #define SYSCFG_EXTICR1_EXTI1_PA ((u16)0x0000) ///< PA[1] pin 107 #define SYSCFG_EXTICR1_EXTI1_PB ((u16)0x0010) ///< PB[1] pin 108 #define SYSCFG_EXTICR1_EXTI1_PC ((u16)0x0020) ///< PC[1] pin 109 #define SYSCFG_EXTICR1_EXTI1_PD ((u16)0x0030) ///< PD[1] pin 110 111 /// @brief EXTI2 configuration 112 #define SYSCFG_EXTICR1_EXTI2_PA ((u16)0x0000) ///< PA[2] pin 113 #define SYSCFG_EXTICR1_EXTI2_PB ((u16)0x0100) ///< PB[2] pin 114 #define SYSCFG_EXTICR1_EXTI2_PC ((u16)0x0200) ///< PC[2] pin 115 #define SYSCFG_EXTICR1_EXTI2_PD ((u16)0x0300) ///< PD[2] pin 116 117 118 /// @brief EXTI3 configuration 119 #define SYSCFG_EXTICR1_EXTI3_PA ((u16)0x0000) ///< PA[3] pin 120 #define SYSCFG_EXTICR1_EXTI3_PB ((u16)0x1000) ///< PB[3] pin 121 #define SYSCFG_EXTICR1_EXTI3_PC ((u16)0x2000) ///< PC[3] pin 122 #define SYSCFG_EXTICR1_EXTI3_PD ((u16)0x3000) ///< PD[3] pin 123 124 125 /// @brief SYSCFG_EXTICR2 Register Bit definition 126 #define SYSCFG_EXTICR2_EXTI4 ((u16)0x000F) ///< EXTI 4 configuration 127 #define SYSCFG_EXTICR2_EXTI5 ((u16)0x00F0) ///< EXTI 5 configuration 128 #define SYSCFG_EXTICR2_EXTI6 ((u16)0x0F00) ///< EXTI 6 configuration 129 #define SYSCFG_EXTICR2_EXTI7 ((u16)0xF000) ///< EXTI 7 configuration 130 131 /// @brief EXTI4 configuration 132 #define SYSCFG_EXTICR2_EXTI4_PA ((u16)0x0000) ///< PA[4] pin 133 #define SYSCFG_EXTICR2_EXTI4_PB ((u16)0x0001) ///< PB[4] pin 134 #define SYSCFG_EXTICR2_EXTI4_PC ((u16)0x0002) ///< PC[4] pin 135 #define SYSCFG_EXTICR2_EXTI4_PD ((u16)0x0003) ///< PD[4] pin 136 137 138 /// @brief EXTI5 configuration 139 #define SYSCFG_EXTICR2_EXTI5_PA ((u16)0x0000) ///< PA[5] pin 140 #define SYSCFG_EXTICR2_EXTI5_PB ((u16)0x0010) ///< PB[5] pin 141 #define SYSCFG_EXTICR2_EXTI5_PC ((u16)0x0020) ///< PC[5] pin 142 #define SYSCFG_EXTICR2_EXTI5_PD ((u16)0x0030) ///< PD[5] pin 143 144 /// @brief EXTI6 configuration 145 146 #define SYSCFG_EXTICR2_EXTI6_PA ((u16)0x0000) ///< PA[6] pin 147 #define SYSCFG_EXTICR2_EXTI6_PB ((u16)0x0100) ///< PB[6] pin 148 #define SYSCFG_EXTICR2_EXTI6_PC ((u16)0x0200) ///< PC[6] pin 149 #define SYSCFG_EXTICR2_EXTI6_PD ((u16)0x0300) ///< PD[6] pin 150 151 152 /// @brief EXTI7 configuration 153 #define SYSCFG_EXTICR2_EXTI7_PA ((u16)0x0000) ///< PA[7] pin 154 #define SYSCFG_EXTICR2_EXTI7_PB ((u16)0x1000) ///< PB[7] pin 155 #define SYSCFG_EXTICR2_EXTI7_PC ((u16)0x2000) ///< PC[7] pin 156 #define SYSCFG_EXTICR2_EXTI7_PD ((u16)0x3000) ///< PD[7] pin 157 158 /// @brief SYSCFG_EXTICR3 Register Bit definition 159 #define SYSCFG_EXTICR3_EXTI8 ((u16)0x000F) ///< EXTI 8 configuration 160 #define SYSCFG_EXTICR3_EXTI9 ((u16)0x00F0) ///< EXTI 9 configuration 161 #define SYSCFG_EXTICR3_EXTI10 ((u16)0x0F00) ///< EXTI 10 configuration 162 #define SYSCFG_EXTICR3_EXTI11 ((u16)0xF000) ///< EXTI 11 configuration 163 164 /// @brief EXTI8 configuration 165 #define SYSCFG_EXTICR3_EXTI8_PA ((u16)0x0000) ///< PA[8] pin 166 #define SYSCFG_EXTICR3_EXTI8_PB ((u16)0x0001) ///< PB[8] pin 167 #define SYSCFG_EXTICR3_EXTI8_PC ((u16)0x0002) ///< PC[8] pin 168 #define SYSCFG_EXTICR3_EXTI8_PD ((u16)0x0003) ///< PD[8] pin 169 170 171 /// @brief EXTI9 configuration 172 173 #define SYSCFG_EXTICR3_EXTI9_PA ((u16)0x0000) ///< PA[9] pin 174 #define SYSCFG_EXTICR3_EXTI9_PB ((u16)0x0010) ///< PB[9] pin 175 #define SYSCFG_EXTICR3_EXTI9_PC ((u16)0x0020) ///< PC[9] pin 176 #define SYSCFG_EXTICR3_EXTI9_PD ((u16)0x0030) ///< PD[9] pin 177 178 /// @brief EXTI10 configuration 179 #define SYSCFG_EXTICR3_EXTI10_PA ((u16)0x0000) ///< PA[10] pin 180 #define SYSCFG_EXTICR3_EXTI10_PB ((u16)0x0100) ///< PB[10] pin 181 #define SYSCFG_EXTICR3_EXTI10_PC ((u16)0x0200) ///< PC[10] pin 182 #define SYSCFG_EXTICR3_EXTI10_PD ((u16)0x0300) ///< PE[10] pin 183 184 /// @brief EXTI11 configuration 185 #define SYSCFG_EXTICR3_EXTI11_PA ((u16)0x0000) ///< PA[11] pin 186 #define SYSCFG_EXTICR3_EXTI11_PB ((u16)0x1000) ///< PB[11] pin 187 #define SYSCFG_EXTICR3_EXTI11_PC ((u16)0x2000) ///< PC[11] pin 188 #define SYSCFG_EXTICR3_EXTI11_PD ((u16)0x3000) ///< PD[11] pin 189 190 191 /// @brief SYSCFG_EXTICR4 Register Bit definition 192 #define SYSCFG_EXTICR4_EXTI12 ((u16)0x000F) ///< EXTI 12 configuration 193 #define SYSCFG_EXTICR4_EXTI13 ((u16)0x00F0) ///< EXTI 13 configuration 194 #define SYSCFG_EXTICR4_EXTI14 ((u16)0x0F00) ///< EXTI 14 configuration 195 #define SYSCFG_EXTICR4_EXTI15 ((u16)0xF000) ///< EXTI 15 configuration 196 197 #define SYSCFG_EXTICR4_EXTI12_PA ((u16)0x0000) ///< PA[12] pin for EXTI12 198 #define SYSCFG_EXTICR4_EXTI12_PB ((u16)0x0001) ///< PB[12] pin for EXTI12 199 #define SYSCFG_EXTICR4_EXTI12_PC ((u16)0x0002) ///< PC[12] pin for EXTI12 200 #define SYSCFG_EXTICR4_EXTI12_PD ((u16)0x0003) ///< PD[12] pin for EXTI12 201 202 #define SYSCFG_EXTICR4_EXTI13_PA ((u16)0x0000) ///< PA[13] pin for EXTI13 203 #define SYSCFG_EXTICR4_EXTI13_PB ((u16)0x0010) ///< PB[13] pin for EXTI13 204 #define SYSCFG_EXTICR4_EXTI13_PC ((u16)0x0020) ///< PC[13] pin for EXTI13 205 #define SYSCFG_EXTICR4_EXTI13_PD ((u16)0x0030) ///< PD[13] pin for EXTI13 206 207 #define SYSCFG_EXTICR4_EXTI14_PA ((u16)0x0000) ///< PA[14] pin for EXTI14 208 #define SYSCFG_EXTICR4_EXTI14_PB ((u16)0x0100) ///< PB[14] pin for EXTI14 209 #define SYSCFG_EXTICR4_EXTI14_PC ((u16)0x0200) ///< PC[14] pin for EXTI14 210 #define SYSCFG_EXTICR4_EXTI14_PD ((u16)0x0300) ///< PD[14] pin for EXTI14 211 212 #define SYSCFG_EXTICR4_EXTI15_PA ((u16)0x0000) ///< PA[15] pin for EXTI15 213 #define SYSCFG_EXTICR4_EXTI15_PB ((u16)0x1000) ///< PB[15] pin for EXTI15 214 #define SYSCFG_EXTICR4_EXTI15_PC ((u16)0x2000) ///< PC[15] pin for EXTI15 215 #define SYSCFG_EXTICR4_EXTI15_PD ((u16)0x3000) ///< PD[15] pin for EXTI15 216 217 218 219 220 #define SYSCFG_CFGR2_I2C1_MODE_SEL_Pos (16) 221 #define SYSCFG_CFGR2_I2C1_MODE_SEL (0x01U << SYSCFG_CFGR2_I2C1_MODE_SEL_Pos) ///< I2C1 Enable PushPull mode 222 #define SYSCFG_CFGR2_I2C2_MODE_SEL_Pos (17) 223 #define SYSCFG_CFGR2_I2C2_MODE_SEL (0x01U << SYSCFG_CFGR2_I2C2_MODE_SEL_Pos) ///< I2C2 Enable PushPull mode 224 225 #define SYSCFG_CFGR2_MII_RMII_MODE_SEL_Pos (20) 226 #define SYSCFG_CFGR2_MII_RMII_MODE_SEL (0x01U << SYSCFG_CFGR2_MII_RMII_MODE_SEL_Pos) ///< MII_RMII mode 227 #define SYSCFG_CFGR2_MAC_SPEED_SEL_Pos (21) 228 #define SYSCFG_CFGR2_MAC_SPEED_SEL (0x01U << SYSCFG_CFGR2_MAC_SPEED_SEL_Pos) ///< MAC_SPEED mode 229 230 231 #define SYSCFG_PDETCSR_PVDE_Pos (0) 232 #define SYSCFG_PDETCSR_PVDE (0x01U << SYSCFG_PDETCSR_PVDE_Pos) ///< Power Voltage Detector Enable 233 234 #define SYSCFG_PDETCSR_PLS_Pos (1) 235 #define SYSCFG_PDETCSR_PLS (0x0FU << SYSCFG_PDETCSR_PLS_Pos) 236 237 #define SYSCFG_PDETCSR_PLS_1V7 (0x00U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 1.7V 238 #define SYSCFG_PDETCSR_PLS_2V0 (0x01U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 2.0V 239 #define SYSCFG_PDETCSR_PLS_2V3 (0x02U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 2.3V 240 #define SYSCFG_PDETCSR_PLS_2V6 (0x03U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 2.6V 241 #define SYSCFG_PDETCSR_PLS_2V9 (0x04U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 2.9V 242 #define SYSCFG_PDETCSR_PLS_3V2 (0x05U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 3.2V 243 #define SYSCFG_PDETCSR_PLS_3V5 (0x06U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 3.5V 244 #define SYSCFG_PDETCSR_PLS_3V8 (0x07U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 3.8V 245 #define SYSCFG_PDETCSR_PLS_4V1 (0x08U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 4.1V 246 #define SYSCFG_PDETCSR_PLS_4V4 (0x09U << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 4.4V 247 #define SYSCFG_PDETCSR_PLS_4V7 (0x0AU << SYSCFG_PDETCSR_PLS_Pos) ///< PVD level 4.7V 248 249 // #define PWR_CR_PLS_Pos SYSCFG_PDETCSR_PLS_Pos 250 // #define PWR_CR_PLS SYSCFG_PDETCSR_PLS 251 // #define PWR_CR_PLS_1V8 SYSCFG_PDETCSR_PLS_1V7 ///< PVD level 1.8V 252 // #define PWR_CR_PLS_2V1 SYSCFG_PDETCSR_PLS_2V0 ///< PVD level 2.1V 253 // #define PWR_CR_PLS_2V4 SYSCFG_PDETCSR_PLS_2V3 ///< PVD level 2.4V 254 // #define PWR_CR_PLS_2V7 SYSCFG_PDETCSR_PLS_2V6 ///< PVD level 2.7V 255 // #define PWR_CR_PLS_3V0 SYSCFG_PDETCSR_PLS_2V9 ///< PVD level 3.0V 256 // #define PWR_CR_PLS_3V3 SYSCFG_PDETCSR_PLS_3V2 ///< PVD level 3.3V 257 // #define PWR_CR_PLS_3V6 SYSCFG_PDETCSR_PLS_3V5 ///< PVD level 3.6V 258 // #define PWR_CR_PLS_3V9 SYSCFG_PDETCSR_PLS_3V8 ///< PVD level 3.9V 259 // #define PWR_CR_PLS_4V2 SYSCFG_PDETCSR_PLS_4V1 ///< PVD level 4.2V 260 // #define PWR_CR_PLS_4V5 SYSCFG_PDETCSR_PLS_4V4 ///< PVD level 4.5V 261 // #define PWR_CR_PLS_4V8 SYSCFG_PDETCSR_PLS_4V7 ///< PVD level 4.8V 262 263 #define SYSCFG_PDETCSR_PVDO_Pos (5) 264 #define SYSCFG_PDETCSR_PVDO (0x01U << SYSCFG_PDETCSR_PVDO_Pos) ///< PVD Output 265 // #define PWR_CSR_PVDO_Pos SYSCFG_PDETCSR_PVDO_Pos 266 // #define PWR_CSR_PVDO SYSCFG_PDETCSR_PVDO ///< PVD Output 267 268 #define SYSCFG_PDETCSR_VDTO_Pos (6) 269 #define SYSCFG_PDETCSR_VDTO (0x01U << SYSCFG_PDETCSR_VDTO_Pos) ///< VDT Output Enable 270 271 #define SYSCFG_PDETCSR_VDTE_Pos (8) 272 #define SYSCFG_PDETCSR_VDTE (0x01U << SYSCFG_PDETCSR_VDTE_Pos) ///< VDT Output 273 274 #define SYSCFG_PDETCSR_VDTLS_Pos (9) 275 #define SYSCFG_PDETCSR_VDTLS (0x0FU << SYSCFG_PDETCSR_VDTLS_Pos) 276 #define SYSCFG_PDETCSR_VDTLS_0V9 (0x00U << SYSCFG_PDETCSR_VDTLS_Pos) ///< VDT level 0.9V 277 #define SYSCFG_PDETCSR_VDTLS_1V0 (0x01U << SYSCFG_PDETCSR_VDTLS_Pos) ///< VDT level 1.0V 278 #define SYSCFG_PDETCSR_VDTLS_1V1 (0x02U << SYSCFG_PDETCSR_VDTLS_Pos) ///< VDT level 1.1V 279 #define SYSCFG_PDETCSR_VDTLS_1V2 (0x03U << SYSCFG_PDETCSR_VDTLS_Pos) ///< VDT level 1.2V 280 281 #define SYSCFG_PDETCSR_VBATDIV3EN_Pos (11) 282 #define SYSCFG_PDETCSR_VBATDIV3EN (0x01U << SYSCFG_PDETCSR_VBATDIV3EN_Pos) ///< VBATDIV3 Enable 283 284 #define SYSCFG_VOSDLY_CNT_Pos (0) 285 #define SYSCFG_VOSDLY_CNT (0x03FFU << SYSCFG_VOSDLY_CNT_Pos) ///< SYSCFG VOSDLY CNT 286 287 288 289 290 291 /// @} 292 293 /// @} 294 295 /// @} 296 297 //////////////////////////////////////////////////////////////////////////////// 298 #endif 299 //////////////////////////////////////////////////////////////////////////////// 300