1 #ifndef __DRV_SYS_H__
2 #define __DRV_SYS_H__
3 
4 #include <rtthread.h>
5 #include "drv_common.h"
6 #include "NuMicro.h"
7 
8 typedef enum
9 {
10     USB0_ID_DEVICE,
11     USB0_ID_HOST,
12     USB0_ID_CNT
13 } E_SYS_USB0_ID;
14 
15 struct nu_module
16 {
17     char      *name;
18     void      *m_pvBase;
19     uint32_t   u32RstId;
20     IRQn_Type  eIRQn;
21 } ;
22 typedef struct nu_module *nu_module_t;
23 
24 typedef struct
25 {
26     vu32     vu32RegAddr;
27     char    *szRegName;
28     vu32     vu32BitMask;
29     char    *szBMName;
30     vu32     vu32Value;
31     char    *szVName;
32 } S_NU_REG;
33 
34 #define SYS_GPA_MFPL       (SYS_BASE + 0x0080U)
35 #define SYS_GPA_MFPH       (SYS_BASE + 0x0084U)
36 #define SYS_GPB_MFPL       (SYS_BASE + 0x0088U)
37 #define SYS_GPB_MFPH       (SYS_BASE + 0x008CU)
38 #define SYS_GPC_MFPL       (SYS_BASE + 0x0090U)
39 #define SYS_GPC_MFPH       (SYS_BASE + 0x0094U)
40 #define SYS_GPD_MFPL       (SYS_BASE + 0x0098U)
41 #define SYS_GPD_MFPH       (SYS_BASE + 0x009CU)
42 #define SYS_GPE_MFPL       (SYS_BASE + 0x00A0U)
43 #define SYS_GPE_MFPH       (SYS_BASE + 0x00A4U)
44 #define SYS_GPF_MFPL       (SYS_BASE + 0x00A8U)
45 #define SYS_GPF_MFPH       (SYS_BASE + 0x00ACU)
46 #define SYS_GPG_MFPL       (SYS_BASE + 0x00B0U)
47 #define SYS_GPG_MFPH       (SYS_BASE + 0x00B4U)
48 #define SYS_GPH_MFPL       (SYS_BASE + 0x00B8U)
49 #define SYS_GPH_MFPH       (SYS_BASE + 0x00BCU)
50 #define SYS_GPI_MFPL       (SYS_BASE + 0x00C0U)
51 #define SYS_GPI_MFPH       (SYS_BASE + 0x00C4U)
52 #define SYS_GPJ_MFPL       (SYS_BASE + 0x00C8U)
53 #define SYS_GPJ_MFPH       (SYS_BASE + 0x00CCU)
54 #define SYS_GPK_MFPL       (SYS_BASE + 0x00D0U)
55 #define SYS_GPK_MFPH       (SYS_BASE + 0x00D4U)
56 #define SYS_GPL_MFPL       (SYS_BASE + 0x00D8U)
57 #define SYS_GPL_MFPH       (SYS_BASE + 0x00DCU)
58 #define SYS_GPM_MFPL       (SYS_BASE + 0x00E0U)
59 #define SYS_GPM_MFPH       (SYS_BASE + 0x00E4U)
60 #define SYS_GPN_MFPL       (SYS_BASE + 0x00E8U)
61 #define SYS_GPN_MFPH       (SYS_BASE + 0x00ECU)
62 
63 #define SYS_USBPMISCR      (SYS_BASE + 0x0060U)
64 #define SYS_USBP0PCR       (SYS_BASE + 0x0064U)
65 #define SYS_USBP1PCR       (SYS_BASE + 0x0068U)
66 
67 #define CLK_PWRCTL         (CLK_BASE + 0x0000U)
68 #define CLK_SYSCLK0        (CLK_BASE + 0x0004U)
69 #define CLK_SYSCLK1        (CLK_BASE + 0x0008U)
70 #define CLK_APBCLK0        (CLK_BASE + 0x000CU)
71 #define CLK_APBCLK1        (CLK_BASE + 0x0010U)
72 #define CLK_APBCLK2        (CLK_BASE + 0x0014U)
73 #define CLK_CLKSEL0        (CLK_BASE + 0x0018U)
74 #define CLK_CLKSEL1        (CLK_BASE + 0x001CU)
75 #define CLK_CLKSEL2        (CLK_BASE + 0x0020U)
76 #define CLK_CLKSEL3        (CLK_BASE + 0x0024U)
77 #define CLK_CLKSEL4        (CLK_BASE + 0x0028U)
78 
79 #define CLK_CLKDIV0        (CLK_BASE + 0x002CU)
80 #define CLK_CLKDIV1        (CLK_BASE + 0x0030U)
81 #define CLK_CLKDIV2        (CLK_BASE + 0x0034U)
82 #define CLK_CLKDIV3        (CLK_BASE + 0x0038U)
83 #define CLK_CLKDIV4        (CLK_BASE + 0x003CU)
84 #define CLK_CLKOCTL        (CLK_BASE + 0x0040U)
85 
86 #define NUREG_EXPORT(vu32RegAddr, vu32BitMask, vu32Value)  { vu32RegAddr, #vu32RegAddr, vu32BitMask, #vu32BitMask, vu32Value, #vu32Value }
87 
88 void nu_clock_base_init(void);
89 void nu_sys_ip_reset(uint32_t u32ModuleIndex);
90 void nu_sys_ipclk_enable(uint32_t eIPClkIdx);
91 void nu_sys_ipclk_disable(uint32_t eIPClkIdx);
92 E_SYS_USB0_ID nu_sys_usb0_role(void);
93 void nu_sys_check_register(S_NU_REG *psNuReg);
94 
95 #endif
96