1 /** 2 ****************************************************************************** 3 * @file lib_cmp.h 4 * @author Application Team 5 * @version V1.1.0 6 * @date 2019-10-28 7 * @brief CMP library. 8 ****************************************************************************** 9 * @attention 10 * 11 ****************************************************************************** 12 */ 13 #ifndef __LIB_CMP_H 14 #define __LIB_CMP_H 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #include "target.h" 21 22 /* CMP Time struct */ 23 typedef struct 24 { 25 uint32_t DebSel; 26 uint32_t SignalSourceSel; 27 uint32_t BiasSel; 28 } CMP_TypeDef; 29 30 typedef struct 31 { 32 uint32_t ModeSel; 33 uint32_t CheckPeriod; 34 uint32_t CheckNum; 35 } CMP_CountTypeDef; 36 37 typedef struct 38 { 39 uint32_t DebSel; 40 uint32_t OutputSel; 41 } CMP_OutputTypeDef; 42 43 typedef struct 44 { 45 uint32_t INTNumSel; 46 uint32_t SubSel; 47 uint32_t THRNum; 48 } CMP_INTTypeDef; 49 50 /* Macros --------------------------------------------------------------------*/ 51 52 /***** CMP_DEBConfig *****/ 53 //CMPx 54 #define CMP_1 (0x00U) 55 #define CMP_2 (0x02U) 56 #define IS_CMP(__CMP__) (((__CMP__) == CMP_1) || ((__CMP__) == CMP_2)) 57 /************** Bits definition for ANA_REG2 register ******************/ 58 #define ANA_REG2_CMP1SEL_0 (0x0U << ANA_REG2_CMP1SEL_Pos) 59 #define ANA_REG2_CMP1SEL_1 (0x1U << ANA_REG2_CMP1SEL_Pos) 60 #define ANA_REG2_CMP1SEL_2 (0x2U << ANA_REG2_CMP1SEL_Pos) 61 #define ANA_REG2_CMP1SEL_3 (0x3U << ANA_REG2_CMP1SEL_Pos) 62 #define ANA_REG2_CMP2SEL_0 (0x0U << ANA_REG2_CMP2SEL_Pos) 63 #define ANA_REG2_CMP2SEL_1 (0x1U << ANA_REG2_CMP2SEL_Pos) 64 #define ANA_REG2_CMP2SEL_2 (0x2U << ANA_REG2_CMP2SEL_Pos) 65 #define ANA_REG2_CMP2SEL_3 (0x3U << ANA_REG2_CMP2SEL_Pos) 66 /************** Bits definition for ANA_REG5 register ******************/ 67 #define ANA_REG5_CMP1IT_0 (0x0U << ANA_REG5_CMP1IT_Pos) 68 #define ANA_REG5_CMP1IT_1 (0x1U << ANA_REG5_CMP1IT_Pos) 69 #define ANA_REG5_CMP1IT_2 (0x2U << ANA_REG5_CMP1IT_Pos) 70 #define ANA_REG5_CMP1IT_3 (0x3U << ANA_REG5_CMP1IT_Pos) 71 #define ANA_REG5_CMP2IT_0 (0x0U << ANA_REG5_CMP2IT_Pos) 72 #define ANA_REG5_CMP2IT_1 (0x1U << ANA_REG5_CMP2IT_Pos) 73 #define ANA_REG5_CMP2IT_2 (0x2U << ANA_REG5_CMP2IT_Pos) 74 #define ANA_REG5_CMP2IT_3 (0x3U << ANA_REG5_CMP2IT_Pos) 75 /************** Bits definition for ANA_CTRL register ******************/ 76 //Debounce 77 #define CMP_DEB_NONE (0x0U) 78 #define CMP_DEB_RTCCLK_2 (0x1U) 79 #define CMP_DEB_RTCCLK_3 (0x2U) 80 #define CMP_DEB_RTCCLK_4 (0x3U) 81 #define IS_CMP_DEB(__DEB__) (((__DEB__) == CMP_DEB_NONE) ||\ 82 ((__DEB__) == CMP_DEB_RTCCLK_2) ||\ 83 ((__DEB__) == CMP_DEB_RTCCLK_3) ||\ 84 ((__DEB__) == CMP_DEB_RTCCLK_4)) 85 86 /***** SourceSelect (CMP_ConfigSignalSource) *****/ 87 #define CMP_SIGNALSRC_PPIN_TO_VREF 0x00 88 #define CMP_SIGNALSRC_PPIN_TO_BGPREF 0x01 89 #define CMP_SIGNALSRC_PBAT_TO_VREF 0x80 90 #define CMP_SIGNALSRC_PBAT_TO_BGPREF 0x81 91 #define CMP_SIGNALSRC_NPIN_TO_VREF 0x10 92 #define CMP_SIGNALSRC_NPIN_TO_BGPREF 0x11 93 #define CMP_SIGNALSRC_PPIN_TO_NPIN 0x20 94 #define CMP_SIGNALSRC_PBAT_TO_NPIN 0xA0 95 96 #define IS_CMP_SIGNALSRC(__SIGNALSRC__) (((__SIGNALSRC__) == CMP_SIGNALSRC_PPIN_TO_VREF) ||\ 97 ((__SIGNALSRC__) == CMP_SIGNALSRC_PPIN_TO_BGPREF) ||\ 98 ((__SIGNALSRC__) == CMP_SIGNALSRC_PPIN_TO_NPIN) ||\ 99 ((__SIGNALSRC__) == CMP_SIGNALSRC_PBAT_TO_NPIN) ||\ 100 ((__SIGNALSRC__) == CMP_SIGNALSRC_PBAT_TO_VREF) ||\ 101 ((__SIGNALSRC__) == CMP_SIGNALSRC_PBAT_TO_BGPREF) ||\ 102 ((__SIGNALSRC__) == CMP_SIGNALSRC_NPIN_TO_VREF) ||\ 103 ((__SIGNALSRC__) == CMP_SIGNALSRC_NPIN_TO_BGPREF)) 104 105 /***** BiasSel (CMP_BiasConfig) *****/ 106 #define CMP_BIAS_20nA (0x0U) 107 #define CMP_BIAS_100nA (0x1U) 108 #define CMP_BIAS_500nA (0x2U) 109 #define IS_CMP_BIAS(__BIAS__) (((__BIAS__) == CMP_BIAS_20nA) ||\ 110 ((__BIAS__) == CMP_BIAS_100nA) ||\ 111 ((__BIAS__) == CMP_BIAS_500nA)) 112 113 /***** CheckPeriod (CMP_CheckFrequecnyConfig) *****/ 114 #define CMP_PERIOD_30US 0 115 #define CMP_PERIOD_7_8125MS 1 116 #define CMP_PERIOD_125MS 2 117 #define CMP_PERIOD_250MS 3 118 #define CMP_PERIOD_500MS 4 119 #define IS_CMP_CHECKPERIOD(__CHECKPERIOD__) (((__CHECKPERIOD__) == CMP_PERIOD_30US) ||\ 120 ((__CHECKPERIOD__) == CMP_PERIOD_7_8125MS)||\ 121 ((__CHECKPERIOD__) == CMP_PERIOD_125MS) ||\ 122 ((__CHECKPERIOD__) == CMP_PERIOD_250MS) ||\ 123 ((__CHECKPERIOD__) == CMP_PERIOD_500MS)) 124 125 /***** Mode (CMP_ModeConfig) *****/ 126 #define CMP_MODE_OFF (0x0U) 127 #define CMP_MODE_RISING (0x1U) 128 #define CMP_MODE_FALLING (0x2U) 129 #define CMP_MODE_BOTH (0x3U) 130 #define IS_CMP_MODE(__MODE__) (((__MODE__) == CMP_MODE_OFF) ||\ 131 ((__MODE__) == CMP_MODE_RISING) ||\ 132 ((__MODE__) == CMP_MODE_FALLING) ||\ 133 ((__MODE__) == CMP_MODE_BOTH)) 134 135 //CountSel 136 #define CMP_COUNT_NOSUB 0 137 #define CMP_COUNT_SUB 1 138 #define IS_CMP_COUNT(__COUNT__) (((__COUNT__) == CMP_COUNT_NOSUB) ||\ 139 ((__COUNT__) == CMP_COUNT_SUB)) 140 141 //SubSel 142 #define CMP_INTNUM_EVERY 0 143 #define CMP_INTNUM_1 1 144 #define IS_CMP_INTNUM(__INTNUM__) (((__INTNUM__) == CMP_INTNUM_EVERY) ||\ 145 ((__INTNUM__) == CMP_INTNUM_1)) 146 147 //THRNum 148 #define IS_CMP_THRNUM(__THRNUM__) ((__THRNUM__) < 65536UL) 149 150 #define CMP_CHKNUM_1 0 151 #define CMP_CHKNUM_2 1 152 #define CMP_CHKNUM_3 2 153 #define CMP_CHKNUM_4 3 154 #define CMP_CHKNUM_5 4 155 #define CMP_CHKNUM_6 5 156 #define CMP_CHKNUM_7 6 157 #define CMP_CHKNUM_8 7 158 #define CMP_CHKNUM_9 8 159 #define CMP_CHKNUM_10 9 160 #define CMP_CHKNUM_11 10 161 #define CMP_CHKNUM_12 11 162 #define CMP_CHKNUM_13 12 163 #define CMP_CHKNUM_14 13 164 #define CMP_CHKNUM_15 14 165 #define CMP_CHKNUM_16 15 166 #define IS_CMP_CHKNUM(__CHKNUM__) (__CHKNUM__ < 16) 167 168 //DebSel 169 //SubSel 170 #define CMP_OUTPUT_DEB 0 171 #define CMP_OUTPUT_NODEB 1 172 #define IS_CMP_OUTPUTDEB(__OUTPUTDEB__) (((__OUTPUTDEB__) == CMP_OUTPUT_DEB) ||\ 173 ((__OUTPUTDEB__) == CMP_OUTPUT_NODEB)) 174 175 /* Exported Functions ------------------------------------------------------- */ 176 /* CMP Exported Functions Group1: 177 (De)Initialization ------------------------*/ 178 void CMP_DeInit(uint32_t CMPx); 179 void CMP_Init(uint32_t CMPx, CMP_TypeDef *InitStruct); 180 void CMP_StructInit(CMP_TypeDef *InitStruct); 181 void CMP_CountStructInit(CMP_CountTypeDef *InitStruct); 182 void CMP_CountInit(uint32_t CMPx, CMP_CountTypeDef *InitStruct); 183 void CMP_INTStructInit(CMP_INTTypeDef *InitStruct); 184 void CMP_INTInit(uint32_t CMPx, CMP_INTTypeDef *InitStruct); 185 void CMP_OutputStructInit(CMP_OutputTypeDef *InitStruct); 186 void CMP_OutputInit(uint32_t CMPx, CMP_OutputTypeDef *InitStruct); 187 /* CMP Exported Functions Group2: 188 Interrupt (flag) --------------------------*/ 189 void CMP_INTConfig(uint32_t CMPx, uint32_t NewState); 190 uint8_t CMP_GetINTStatus(uint32_t CMPx); 191 void CMP_ClearINTStatus(uint32_t CMPx); 192 /* CMP Exported Functions Group3: 193 MISC Configuration ------------------------*/ 194 void CMP_Cmd(uint32_t CMPx, uint32_t NewState); 195 uint32_t CMP_GetCNTValue(uint32_t CMPx); 196 void CMP_ClearCNTValue(uint32_t CMPx); 197 uint8_t CMP_GetOutputValue(uint32_t CMPx); 198 199 #ifdef __cplusplus 200 } 201 #endif 202 203 #endif /* __LIB_CMP_H */ 204 205 /*********************************** END OF FILE ******************************/ 206