1 /** @file reg_rti.h 2 * @brief RTI Register Layer Header File 3 * @date 29.May.2013 4 * @version 03.05.02 5 * 6 * This file contains: 7 * - Definitions 8 * - Types 9 * - Interface Prototypes 10 * . 11 * which are relevant for the RTI driver. 12 */ 13 14 /* (c) Texas Instruments 2009-2013, All rights reserved. */ 15 16 #ifndef __REG_RTI_H__ 17 #define __REG_RTI_H__ 18 19 #include "sys_common.h" 20 21 22 23 /* USER CODE BEGIN (0) */ 24 /* USER CODE END */ 25 26 /* Rti Register Frame Definition */ 27 /** @struct rtiBase 28 * @brief RTI Register Frame Definition 29 * 30 * This type is used to access the RTI Registers. 31 */ 32 /** @typedef rtiBASE_t 33 * @brief RTI Register Frame Type Definition 34 * 35 * This type is used to access the RTI Registers. 36 */ 37 typedef volatile struct rtiBase 38 { 39 uint32 GCTRL; /**< 0x0000: Global Control Register */ 40 uint32 TBCTRL; /**< 0x0004: Timebase Control Register */ 41 uint32 CAPCTRL; /**< 0x0008: Capture Control Register */ 42 uint32 COMPCTRL; /**< 0x000C: Compare Control Register */ 43 struct 44 { 45 uint32 FRCx; /**< 0x0010,0x0030: Free Running Counter x Register */ 46 uint32 UCx; /**< 0x0014,0x0034: Up Counter x Register */ 47 uint32 CPUCx; /**< 0x0018,0x0038: Compare Up Counter x Register */ 48 uint32 rsvd1; /**< 0x001C,0x003C: Reserved */ 49 uint32 CAFRCx; /**< 0x0020,0x0040: Capture Free Running Counter x Register */ 50 uint32 CAUCx; /**< 0x0024,0x0044: Capture Up Counter x Register */ 51 uint32 rsvd2[2U]; /**< 0x0028,0x0048: Reserved */ 52 } CNT[2U]; /**< Counter x selection: 53 - 0: Counter 0 54 - 1: Counter 1 */ 55 struct 56 { 57 uint32 COMPx; /**< 0x0050,0x0058,0x0060,0x0068: Compare x Register */ 58 uint32 UDCPx; /**< 0x0054,0x005C,0x0064,0x006C: Update Compare x Register */ 59 } CMP[4U]; /**< Compare x selection: 60 - 0: Compare 0 61 - 1: Compare 1 62 - 2: Compare 2 63 - 3: Compare 3 */ 64 uint32 TBLCOMP; /**< 0x0070: External Clock Timebase Low Compare Register */ 65 uint32 TBHCOMP; /**< 0x0074: External Clock Timebase High Compare Register */ 66 uint32 rsvd3[2U]; /**< 0x0078: Reserved */ 67 uint32 SETINT; /**< 0x0080: Set/Status Interrupt Register */ 68 uint32 CLEARINT; /**< 0x0084: Clear/Status Interrupt Register */ 69 uint32 INTFLAG; /**< 0x0088: Interrupt Flag Register */ 70 uint32 rsvd4; /**< 0x008C: Reserved */ 71 uint32 DWDCTRL; /**< 0x0090: Digital Watchdog Control Register */ 72 uint32 DWDPRLD; /**< 0x0094: Digital Watchdog Preload Register */ 73 uint32 WDSTATUS; /**< 0x0098: Watchdog Status Register */ 74 uint32 WDKEY; /**< 0x009C: Watchdog Key Register */ 75 uint32 DWDCNTR; /**< 0x00A0: Digital Watchdog Down Counter */ 76 uint32 WWDRXNCTRL; /**< 0x00A4: Digital Windowed Watchdog Reaction Control */ 77 uint32 WWDSIZECTRL; /**< 0x00A8: Digital Windowed Watchdog Window Size Control */ 78 uint32 INTCLRENABLE; /**< 0x00AC: RTI Compare Interrupt Clear Enable Register */ 79 uint32 COMP0CLR; /**< 0x00B0: RTI Compare 0 Clear Register */ 80 uint32 COMP1CLR; /**< 0x00B4: RTI Compare 1 Clear Register */ 81 uint32 COMP2CLR; /**< 0x00B8: RTI Compare 2 Clear Register */ 82 uint32 COMP3CLR; /**< 0x00BC: RTI Compare 3 Clear Register */ 83 } rtiBASE_t; 84 85 /** @def rtiREG1 86 * @brief RTI1 Register Frame Pointer 87 * 88 * This pointer is used by the RTI driver to access the RTI1 registers. 89 */ 90 #define rtiREG1 ((rtiBASE_t *)0xFFFFFC00U) 91 92 /* USER CODE BEGIN (1) */ 93 /* USER CODE END */ 94 95 96 #endif 97