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Searched defs:TIM4_BASE (Results 1 – 25 of 44) sorted by relevance

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/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/
A Dab32vg1_hal_tim.h28 #define TIM4_BASE ((hal_sfr_t)&TMR4CON) macro
/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_tim.h52 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) ///< Base Address: … macro
/bsp/acm32/acm32f4xx-nucleo/libraries/Device/
A DACM32F4.h688 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) macro
/bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/WCH/CH32V10x/Include/
A Dch32v10x.h515 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) macro
/bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/
A Dch32v10x.h515 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) macro
/bsp/mm32l3xx/Libraries/MM32L3xx/Include/
A DMM32L3xx.h948 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) macro
/bsp/mm32f103x/Libraries/MM32F103/Include/
A DMM32F103.h957 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) macro
/bsp/tkm32F499/Libraries/CMSIS_and_startup/
A Dtk499.h1282 #define TIM4_BASE (APB1PERIPH_BASE + 0x0400) macro
/bsp/mm32l07x/Libraries/MM32L0xx/Include/
A DMM32L0xx.h889 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) macro
/bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/CMSIS/WCH/CH32F10x/Include/
A Dch32f10x.h611 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) macro
/bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/StdPeriph_Driver/inc/
A Dch32f10x.h611 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) macro
/bsp/wch/arm/Libraries/CH32F20x_StdPeriph_Driver/CMSIS/WCH/CH32F20x/Include/
A Dch32f20x.h969 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) macro
/bsp/wch/arm/Libraries/CH32F20x_StdPeriph_Driver/StdPeriph_Driver/inc/
A Dch32f20x.h969 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) macro
/bsp/airm2m/air32f103/libraries/AIR32F10xLib/inc/
A Dair32f10x.h968 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) macro
/bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/
A Dn32g43x.h924 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) macro
/bsp/n32/libraries/N32WB452_Firmware_Library/CMSIS/device/
A Dn32wb452.h982 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) macro
/bsp/n32/libraries/N32L40x_Firmware_Library/CMSIS/device/
A Dn32l40x.h939 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) macro
/bsp/n32/libraries/N32L43x_Firmware_Library/CMSIS/device/
A Dn32l43x.h965 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) macro
/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/
A Dstm32l100xb.h579 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) macro
A Dstm32l100xba.h579 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) macro
A Dstm32l151xb.h579 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) macro
A Dstm32l151xba.h579 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) macro
A Dstm32l152xb.h594 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) macro
A Dstm32l152xba.h579 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) macro
/bsp/n32/libraries/N32G4FR_Firmware_Library/CMSIS/device/
A Dn32g4fr.h1061 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) macro

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