1 /* 2 * Copyright 2021 MindMotion Microelectronics Co., Ltd. 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef __HAL_TIM_32B_H__ 9 #define __HAL_TIM_32B_H__ 10 11 #include "hal_common.h" 12 13 /*! 14 * @addtogroup TIM_32B 15 * @{ 16 */ 17 18 /*! 19 * @brief TIM_32B driver version number. 20 */ 21 #define TIM_32B_DRIVER_VERSION 0u /*!< TIM_32B_0. */ 22 23 /*! 24 * @addtogroup TIM_32B_CHANNEL_SELECTION 25 * @{ 26 */ 27 #define TIM_32B_CHN_NUM (4u) /*!< The total number of TIM_32B channel. */ 28 #define TIM_32B_CHN_1 (0u) /*!< The selection of TIM_32B Channel 1. */ 29 #define TIM_32B_CHN_2 (1u) /*!< The selection of TIM_32B Channel 2. */ 30 #define TIM_32B_CHN_3 (2u) /*!< The selection of TIM_32B Channel 3. */ 31 #define TIM_32B_CHN_4 (3u) /*!< The selection of TIM_32B Channel 4. */ 32 /*! 33 *@} 34 */ 35 36 /*! 37 * @addtogroup TIM_32B_INT 38 * @brief Enable interrupt. 39 * @{ 40 */ 41 #define TIM_32B_INT_UPDATE_PERIOD (1u << 0u) /*!< Timer update period interrupt switchers. */ 42 #define TIM_32B_INT_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture interrupt switchers. */ 43 #define TIM_32B_INT_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture interrupt switchers. */ 44 #define TIM_32B_INT_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture interrupt switchers. */ 45 #define TIM_32B_INT_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture interrupt switchers. */ 46 #define TIM_32B_INT_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event interrupt switchers. */ 47 /*! 48 * @} 49 */ 50 51 /*! 52 * @addtogroup TIM_32B_DMA 53 * @brief Enable DMA. 54 * @{ 55 */ 56 #define TIM_32B_DMA_UPDATE_PERIOD (1u << 8u) /*!< Timer update period DMA switchers. */ 57 #define TIM_32B_DMA_CHN1_EVENT (1u << 9u) /*!< Channel 1 event for output compare or input capture DMA switchers. */ 58 #define TIM_32B_DMA_CHN2_EVENT (1u << 10u) /*!< Channel 2 event for output compare or input capture DMA switchers. */ 59 #define TIM_32B_DMA_CHN3_EVENT (1u << 11u) /*!< Channel 3 event for output compare or input capture DMA switchers. */ 60 #define TIM_32B_DMA_CHN4_EVENT (1u << 12u) /*!< Channel 4 event for output compare or input capture DMA switchers. */ 61 #define TIM_32B_DMA_TRGOUT_EVENT (1u << 14u) /*!< Trigger out event DMA switchers. */ 62 /*! 63 * @} 64 */ 65 66 /*! 67 * @addtogroup TIM_32B_INT_STATUS 68 * @brief Check interrupt status. 69 * @{ 70 */ 71 #define TIM_32B_STATUS_UPDATE_PERIOD (1u << 0u) /*!< Timer update period interrupt flag. */ 72 #define TIM_32B_STATUS_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture interrupt flag. */ 73 #define TIM_32B_STATUS_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture interrupt flag. */ 74 #define TIM_32B_STATUS_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture interrupt flag. */ 75 #define TIM_32B_STATUS_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture interrupt flag. */ 76 #define TIM_32B_STATUS_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event interrupt flag. */ 77 #define TIM_32B_STATUS_CHN1_OVER_EVENT (1u << 9u) /*!< Channel 1 event for output overcompare or input overcapture interrupt flag. */ 78 #define TIM_32B_STATUS_CHN2_OVER_EVENT (1u << 10u) /*!< Channel 2 event for output overcompare or input overcapture interrupt flag. */ 79 #define TIM_32B_STATUS_CHN3_OVER_EVENT (1u << 11u) /*!< Channel 3 event for output overcompare or input overcapture interrupt flag. */ 80 #define TIM_32B_STATUS_CHN4_OVER_EVENT (1u << 12u) /*!< Channel 4 event for output overcompare or input overcapture interrupt flag. */ 81 /*! 82 * @} 83 */ 84 85 /*! 86 * @addtogroup TIM_32B_SWTRG 87 * @brief Events to be triggered by software. 88 * @{ 89 */ 90 #define TIM_32B_SWTRG_UPDATE_PERIOD (1u << 0u) /*!< Timer update period software trigger. */ 91 #define TIM_32B_SWTRG_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture software trigger. */ 92 #define TIM_32B_SWTRG_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture software trigger. */ 93 #define TIM_32B_SWTRG_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture software trigger. */ 94 #define TIM_32B_SWTRG_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture software trigger. */ 95 #define TIM_32B_SWTRG_COM_EVENT (1u << 5u) /*!< COM event software trigger. */ 96 #define TIM_32B_SWTRG_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event software trigger. */ 97 /*! 98 * @} 99 */ 100 101 /*! 102 * @brief Counter period working mode. 103 */ 104 typedef enum 105 { 106 TIM_32B_PeriodMode_Continuous = 0u, /*!< Counter works circularly once started. */ 107 TIM_32B_PeriodMode_OneTimeRun = 1u, /*!< Counter only works one time once started. */ 108 } TIM_32B_PeriodMode_Type; 109 110 /*! 111 * @brief Counter count direction. 112 */ 113 typedef enum 114 { 115 TIM_32B_CountMode_Increasing = 0u, /*!< Counter counts incrementally from 0 to period and generates an update. */ 116 TIM_32B_CountMode_Decreasing = 1u, /*!< Counter counts decrementally from period to 0 and generates an update. */ 117 TIM_32B_CountMode_CenterAligned1 = 2u, /*!< Counter counts center-aligned from 0 to period - 1 then from period to 0 and generates an update. */ 118 TIM_32B_CountMode_CenterAligned2 = 3u, /*!< Counter counts center-aligned from 0 to period - 1 and generates an update then from period to 0. */ 119 TIM_32B_CountMode_CenterAligned3 = 4u, /*!< Counter counts center-aligned from 0 to period - 1 and generates an update then from period to 0 and generates another update. */ 120 } TIM_32B_CountMode_Type; 121 122 /*! 123 * @brief TIM output compare reference polairty event. 124 */ 125 typedef enum 126 { 127 TIM_32B_OutputCompareRefOut_None = 0u, /*!< Reference will not be changed. */ 128 TIM_32B_OutputCompareRefOut_HighOnMatch = 1u, /*!< Reference will be high when counter value equals channel value. */ 129 TIM_32B_OutputCompareRefOut_LowOnMatch = 2u, /*!< Reference will be low when counter value equals channel value. */ 130 TIM_32B_OutputCompareRefOut_ToggleOnMatch = 3u, /*!< Reference will toggle. */ 131 TIM_32B_OutputCompareRefOut_LowAlways = 4u, /*!< Reference will always be low. */ 132 TIM_32B_OutputCompareRefOut_HighAlways = 5u, /*!< Reference will always be high. */ 133 TIM_32B_OutputCompareRefOut_FallingEdgeOnMatch = 6u, /*!< PWM mode 1. */ 134 TIM_32B_OutputCompareRefOut_RisingEdgeOnMatch = 7u, /*!< PWM mode 2. */ 135 } TIM_32B_OutputCompareRefOut_Type; 136 137 /*! 138 * @brief TIM input capture active edge selection and output compare active polarity selection. 139 * | conf | TIM_32B_PinPolarity_Rising | TIM_32B_PinPolarity_Falling | 140 * | -------------- | -------------------------- | --------------------------- | 141 * | input capture | detects rising edge | detects falling edge | 142 * | output compare | high polarity is active | low polarity is active | 143 * | encoder mode | input remains | input reverses | 144 */ 145 typedef enum 146 { 147 TIM_32B_PinPolarity_Disable = 0u, /*!< Disable channel. */ 148 TIM_32B_PinPolarity_Rising = 1u, /*!< See the table above. */ 149 TIM_32B_PinPolarity_Falling = 2u, /*!< See the table above. */ 150 TIM_32B_PinPolarity_RisingOrFalling = 3u, /*!< For input capture, detect both the rising and falling edge. */ 151 }TIM_32B_PinPolarity_Type; 152 153 /*! 154 * @brief TIM Input active times to evoke capture. 155 */ 156 typedef enum 157 { 158 TIM_32B_InputCaptureInDiv_OnEveryCapture = 0u, /*!< Every input call capture. */ 159 TIM_32B_InputCaptureInDiv_OnEach2Capture = 1u, /*!< Every two input call capture. */ 160 TIM_32B_InputCaptureInDiv_OnEach4Capture = 2u, /*!< Every four input call capture. */ 161 TIM_32B_InputCaptureInDiv_OnEach8Capture = 3u, /*!< Every eight input call capture. */ 162 } TIM_32B_InputCaptureInDiv_Type; 163 164 /*! 165 * @brief TIM Input sampling filter. 166 */ 167 typedef enum 168 { 169 TIM_32B_InputCaptureInFilter_Alt0 = 0u, /*!< Filter swicther 0. */ 170 TIM_32B_InputCaptureInFilter_Alt1 = 1u, /*!< Filter swicther 1. */ 171 TIM_32B_InputCaptureInFilter_Alt2 = 2u, /*!< Filter swicther 2. */ 172 TIM_32B_InputCaptureInFilter_Alt3 = 3u, /*!< Filter swicther 3. */ 173 TIM_32B_InputCaptureInFilter_Alt4 = 4u, /*!< Filter swicther 4. */ 174 TIM_32B_InputCaptureInFilter_Alt5 = 5u, /*!< Filter swicther 5. */ 175 TIM_32B_InputCaptureInFilter_Alt6 = 6u, /*!< Filter swicther 6. */ 176 TIM_32B_InputCaptureInFilter_Alt7 = 7u, /*!< Filter swicther 7. */ 177 TIM_32B_InputCaptureInFilter_Alt8 = 8u, /*!< Filter swicther 8. */ 178 TIM_32B_InputCaptureInFilter_Alt9 = 9u, /*!< Filter swicther 9. */ 179 TIM_32B_InputCaptureInFilter_Alt10 = 10u, /*!< Filter swicther 10. */ 180 TIM_32B_InputCaptureInFilter_Alt11 = 11u, /*!< Filter swicther 11. */ 181 TIM_32B_InputCaptureInFilter_Alt12 = 12u, /*!< Filter swicther 12. */ 182 TIM_32B_InputCaptureInFilter_Alt13 = 13u, /*!< Filter swicther 13. */ 183 TIM_32B_InputCaptureInFilter_Alt14 = 14u, /*!< Filter swicther 14. */ 184 TIM_32B_InputCaptureInFilter_Alt15 = 15u, /*!< Filter swicther 15. */ 185 } TIM_32B_InputCaptureInFilter_Type; 186 187 /*! 188 * @brief TIM channel IO mode. 189 */ 190 typedef enum 191 { 192 TIM_32B_ChannelIOMode_Out = 0u, /*!< Channel output. */ 193 TIM_32B_ChannelIOMode_In = 1u, /*!< Channel input, capture signal from direct channel. */ 194 TIM_32B_ChannelIOMode_Alt2 = 2u, /*!< Channel input, capture signal from indirect channel. */ 195 TIM_32B_ChannelIOMode_Alt3 = 3u, /*!< Channel input, capture signal from trc. */ 196 } TIM_32B_ChannelIOMode_Type; 197 198 /*! 199 * @brief TIM external trigger input active edge selection. 200 */ 201 typedef enum 202 { 203 TIM_32B_ExtTriggerPinPolarity_Disable = 0u, /*!< Disable external trigger input. */ 204 TIM_32B_ExtTriggerPinPolarity_Rising = 1u, /*!< Detect the rising edge from external trigger. */ 205 TIM_32B_ExtTriggerPinPolarity_Falling = 2u, /*!< Detect the falling edge from external trigger. */ 206 }TIM_32B_ExtTriggerPinPolarity_Type; 207 208 /*! 209 * @brief TIM external trigger active input times to drive counter. 210 */ 211 typedef enum 212 { 213 TIM_32B_ExtTriggerInDiv_OnEveryCapture = 0u, /*!< Every input call capture. */ 214 TIM_32B_ExtTriggerInDiv_OnEach2Capture = 1u, /*!< Every two input call capture. */ 215 TIM_32B_ExtTriggerInDiv_OnEach4Capture = 2u, /*!< Every four input call capture. */ 216 TIM_32B_ExtTriggerInDiv_OnEach8Capture = 3u, /*!< Every eight input call capture. */ 217 } TIM_32B_ExtTriggerInDiv_Type; 218 219 /*! 220 * @brief TIM external trigger sampling filter. 221 */ 222 typedef enum 223 { 224 TIM_32B_ExtTriggerInFilter_Alt0 = 0u, /*!< Filter swicther 0. */ 225 TIM_32B_ExtTriggerInFilter_Alt1 = 1u, /*!< Filter swicther 1. */ 226 TIM_32B_ExtTriggerInFilter_Alt2 = 2u, /*!< Filter swicther 2. */ 227 TIM_32B_ExtTriggerInFilter_Alt3 = 3u, /*!< Filter swicther 3. */ 228 TIM_32B_ExtTriggerInFilter_Alt4 = 4u, /*!< Filter swicther 4. */ 229 TIM_32B_ExtTriggerInFilter_Alt5 = 5u, /*!< Filter swicther 5. */ 230 TIM_32B_ExtTriggerInFilter_Alt6 = 6u, /*!< Filter swicther 6. */ 231 TIM_32B_ExtTriggerInFilter_Alt7 = 7u, /*!< Filter swicther 7. */ 232 TIM_32B_ExtTriggerInFilter_Alt8 = 8u, /*!< Filter swicther 8. */ 233 TIM_32B_ExtTriggerInFilter_Alt9 = 9u, /*!< Filter swicther 9. */ 234 TIM_32B_ExtTriggerInFilter_Alt10 = 10u, /*!< Filter swicther 10. */ 235 TIM_32B_ExtTriggerInFilter_Alt11 = 11u, /*!< Filter swicther 11. */ 236 TIM_32B_ExtTriggerInFilter_Alt12 = 12u, /*!< Filter swicther 12. */ 237 TIM_32B_ExtTriggerInFilter_Alt13 = 13u, /*!< Filter swicther 13. */ 238 TIM_32B_ExtTriggerInFilter_Alt14 = 14u, /*!< Filter swicther 14. */ 239 TIM_32B_ExtTriggerInFilter_Alt15 = 15u, /*!< Filter swicther 15. */ 240 } TIM_32B_ExtTriggerInFilter_Type; 241 242 /*! 243 * @brief TIM Dead area time step length. 244 */ 245 typedef enum 246 { 247 TIM_32B_DeadAreaStep_Alt0 = 0u, /*!< Dead area step = clock source step. */ 248 TIM_32B_DeadAreaStep_Alt1 = 1u, /*!< Dead area step = 2 * clock source step. */ 249 TIM_32B_DeadAreaStep_Alt2 = 2u, /*!< Dead area step = 4 * clock source step. */ 250 } TIM_32B_DeadAreaStep_Type; 251 252 /*! 253 * @brief TIM master mode output signal source. 254 */ 255 typedef enum 256 { 257 TIM_32B_MasterOut_Alt0 = 0u, /*!< Software update period trigger signal works as master output. */ 258 TIM_32B_MasterOut_Alt1 = 1u, /*!< Counter enable signal works as master output. */ 259 TIM_32B_MasterOut_Alt2 = 2u, /*!< Update period event works as master output. */ 260 TIM_32B_MasterOut_Alt3 = 3u, /*!< Channel capture or compare event works as master output. */ 261 TIM_32B_MasterOut_Alt4 = 4u, /*!< Reference signal of channel 1 works as master output. */ 262 TIM_32B_MasterOut_Alt5 = 5u, /*!< Reference signal of channel 2 works as master output. */ 263 TIM_32B_MasterOut_Alt6 = 6u, /*!< Reference signal of channel 3 works as master output. */ 264 TIM_32B_MasterOut_Alt7 = 7u, /*!< Reference signal of channel 4 works as master output. */ 265 } TIM_32B_MasterOut_Type; 266 267 /*! 268 * @brief TIM slave mode input object source. 269 */ 270 typedef enum 271 { 272 TIM_32B_SlaveIn_Alt0 = 0u, /*!< Internal trigger 0. */ 273 TIM_32B_SlaveIn_Alt1 = 1u, /*!< Internal trigger 1. */ 274 TIM_32B_SlaveIn_Alt2 = 2u, /*!< Internal trigger 2.*/ 275 TIM_32B_SlaveIn_Alt3 = 3u, /*!< Internal trigger 3. */ 276 TIM_32B_SlaveIn_Alt4 = 4u, /*!< Edge detector of timer input channel 1. */ 277 TIM_32B_SlaveIn_Alt5 = 5u, /*!< Timer input channel 1. */ 278 TIM_32B_SlaveIn_Alt6 = 6u, /*!< Timer input channel 2. */ 279 TIM_32B_SlaveIn_Alt7 = 7u, /*!< External trigger input. */ 280 } TIM_32B_SlaveIn_Type; 281 282 /*! 283 * @brief TIM slave mode counter response. 284 */ 285 typedef enum 286 { 287 TIM_32B_SlaveResp_Disable = 0u, /*!< Disable the slave mode. */ 288 TIM_32B_SlaveResp_Alt1 = 1u, /*!< Counting in encoder mode 1. */ 289 TIM_32B_SlaveResp_Alt2 = 2u, /*!< Counting in encoder mode 2.*/ 290 TIM_32B_SlaveResp_Alt3 = 3u, /*!< Counting in encoder mode 3. */ 291 TIM_32B_SlaveResp_Alt4 = 4u, /*!< Reset counter. */ 292 TIM_32B_SlaveResp_Alt5 = 5u, /*!< Counter treat the signal as a gate. */ 293 TIM_32B_SlaveResp_Alt6 = 6u, /*!< Start the counter. */ 294 TIM_32B_SlaveResp_Alt7 = 7u, /*!< Counter counts on rising edges. */ 295 } TIM_32B_SlaveResp_Type; 296 297 /*! 298 * @brief TIM DMA Burst transfer base address. 299 */ 300 typedef enum 301 { 302 TIM_32B_DMABurstBaseAddr_Alt0 = 0u, /*!< Start from CR1 register. */ 303 TIM_32B_DMABurstBaseAddr_Alt1 = 1u, /*!< Start from CR2 register. */ 304 TIM_32B_DMABurstBaseAddr_Alt2 = 2u, /*!< Start from SMCR register. */ 305 TIM_32B_DMABurstBaseAddr_Alt3 = 3u, /*!< Start from DIER register. */ 306 TIM_32B_DMABurstBaseAddr_Alt4 = 4u, /*!< Start from SR register. */ 307 TIM_32B_DMABurstBaseAddr_Alt5 = 5u, /*!< Start from EGR register. */ 308 TIM_32B_DMABurstBaseAddr_Alt6 = 6u, /*!< Start from CCMR1 register. */ 309 TIM_32B_DMABurstBaseAddr_Alt7 = 7u, /*!< Start from CCMR2 register. */ 310 TIM_32B_DMABurstBaseAddr_Alt8 = 8u, /*!< Start from CCER register. */ 311 TIM_32B_DMABurstBaseAddr_Alt9 = 9u, /*!< Start from CNT register. */ 312 TIM_32B_DMABurstBaseAddr_Alt10 = 10u, /*!< Start from PSC register. */ 313 TIM_32B_DMABurstBaseAddr_Alt11 = 11u, /*!< Start from ARR register. */ 314 TIM_32B_DMABurstBaseAddr_Alt12 = 12u, /*!< Start from CCR1 register. */ 315 TIM_32B_DMABurstBaseAddr_Alt13 = 13u, /*!< Start from CCR2 register. */ 316 TIM_32B_DMABurstBaseAddr_Alt14 = 14u, /*!< Start from CCR3 register. */ 317 TIM_32B_DMABurstBaseAddr_Alt15 = 15u, /*!< Start from CCR4 register. */ 318 } TIM_32B_DMABurstBaseAddr_Type; 319 320 /*! 321 * @brief TIM DMA Burst transfer length. 322 */ 323 typedef enum 324 { 325 TIM_32B_DMABurstBaseLen_Alt0 = 0u, /*!< Sequentially visit 1 register from base register */ 326 TIM_32B_DMABurstBaseLen_Alt1 = 1u, /*!< Sequentially visit 2 registers from base register */ 327 TIM_32B_DMABurstBaseLen_Alt2 = 2u, /*!< Sequentially visit 3 registers from base register */ 328 TIM_32B_DMABurstBaseLen_Alt3 = 3u, /*!< Sequentially visit 4 registers from base register */ 329 TIM_32B_DMABurstBaseLen_Alt4 = 4u, /*!< Sequentially visit 5 registers from base register */ 330 TIM_32B_DMABurstBaseLen_Alt5 = 5u, /*!< Sequentially visit 6 registers from base register */ 331 TIM_32B_DMABurstBaseLen_Alt6 = 6u, /*!< Sequentially visit 7 registers from base register */ 332 TIM_32B_DMABurstBaseLen_Alt7 = 7u, /*!< Sequentially visit 8 registers from base register */ 333 TIM_32B_DMABurstBaseLen_Alt8 = 8u, /*!< Sequentially visit 9 registers from base register */ 334 TIM_32B_DMABurstBaseLen_Alt9 = 9u, /*!< Sequentially visit 10 registers from base register */ 335 TIM_32B_DMABurstBaseLen_Alt10 = 10u, /*!< Sequentially visit 11 registers from base register */ 336 TIM_32B_DMABurstBaseLen_Alt11 = 11u, /*!< Sequentially visit 12 registers from base register */ 337 TIM_32B_DMABurstBaseLen_Alt12 = 12u, /*!< Sequentially visit 13 registers from base register */ 338 TIM_32B_DMABurstBaseLen_Alt13 = 13u, /*!< Sequentially visit 14 registers from base register */ 339 TIM_32B_DMABurstBaseLen_Alt14 = 14u, /*!< Sequentially visit 15 registers from base register */ 340 TIM_32B_DMABurstBaseLen_Alt15 = 15u, /*!< Sequentially visit 16 registers from base register */ 341 TIM_32B_DMABurstBaseLen_Alt16 = 16u, /*!< Sequentially visit 17 registers from base register */ 342 TIM_32B_DMABurstBaseLen_Alt17 = 17u, /*!< Sequentially visit 18 registers from base register */ 343 } TIM_32B_DMABurstBaseLen_Type; 344 345 /*! 346 * @brief TIM encoder direction. 347 */ 348 typedef enum 349 { 350 TIM_32B_EncoderDirection_Forward = 0u, /*!< Encoder rotates in forward direction. */ 351 TIM_32B_EncoderDirection_Backward = 1u, /*!< Encoder rotates in backward direction. */ 352 } TIM_32B_EncoderDirection_Type; 353 354 /*! 355 * @brief This type of structure instance is used to keep the settings when calling the @ref TIM_32B_Init() to initialize the TIM module time base unit. 356 */ 357 typedef struct 358 { 359 uint32_t ClockFreqHz; /*!< Frequence of clock source for counter. */ 360 uint32_t StepFreqHz; /*!< Step length value. Counter freq = ClockSourceFreqHz / (ClockSourceDiv+1). */ 361 uint32_t Period; /*!< Counter counting period length, from 0 to Period. */ 362 bool EnablePreloadPeriod; /*!< Enable the preload of period value. If enable, it will be updated in next period, otherwise immediately. */ 363 TIM_32B_PeriodMode_Type PeriodMode; /*!< Counter working period times. */ 364 TIM_32B_CountMode_Type CountMode; /*!< Counter count direction. */ 365 } TIM_32B_Init_Type; 366 367 /*! 368 * @brief This type of structure instance is used to setup the output compare feature when calling the @ref TIM_32B_EnableOutputCompare() to enable the TIM module output compare channel. 369 */ 370 typedef struct 371 { 372 uint32_t ChannelValue; /*!< Value to be compared with counter. */ 373 bool EnableFastOutput; /*!< Enable fast response to the trigger input event. */ 374 bool EnablePreLoadChannelValue; /*!< Enable the preload of channel value. If enable, it will be updated in next period, otherwise immediately. */ 375 TIM_32B_OutputCompareRefOut_Type RefOutMode; /*!< The reference output when counter matching the channel value. */ 376 bool ClearRefOutOnExtTrigger; /*!< External trigger high will clear the reference. */ 377 TIM_32B_PinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */ 378 } TIM_32B_OutputCompareConf_Type; 379 380 /*! 381 * @brief This type of structure instance is used to setup the input capture feature when calling the @ref TIM_32B_EnableInputCapture() to enable the TIM module input capture channel. 382 */ 383 typedef struct 384 { 385 TIM_32B_InputCaptureInDiv_Type InDiv; /*!< The division of filtered input. */ 386 TIM_32B_InputCaptureInFilter_Type InFilter; /*!< The filter sampling time for initial input. */ 387 TIM_32B_PinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */ 388 } TIM_32B_InputCaptureConf_Type; 389 390 /*! 391 * @brief This type of structure instance is used to setup the dead time feature when calling the @ref TIM_32B_EnableDeadArea() to enable the TIM module dead time area set. 392 */ 393 typedef struct 394 { 395 TIM_32B_DeadAreaStep_Type StepFreqHz; /*!< Dead time area step set. */ 396 } TIM_32B_DeadAreaConf_Type; 397 398 /*! 399 * @brief This type of structure instance is used to setup the master mode configuration when calling the @ref TIM_32B_EnableMasterMode(). 400 */ 401 typedef struct 402 { 403 TIM_32B_MasterOut_Type Out; /*!< Master mode output selection. */ 404 bool EnableSync; /*!< Enable sychronize with slave timers. */ 405 } TIM_32B_MasterModeConf_Type; 406 407 /*! 408 * @brief This type of structure instance is used to setup the slave mode configuration when calling the @ref TIM_32B_EnableSlaveMode(). 409 */ 410 typedef struct 411 { 412 TIM_32B_SlaveIn_Type In; /*!< Input trigger selection for slave timer. */ 413 TIM_32B_SlaveResp_Type Resp; /*!< Slave timer counter response for its input trigger. */ 414 } TIM_32B_SlaveModeConf_Type; 415 416 /*! 417 * @brief This type of structure instance is used to setup the external trigger input configuration when calling the @ref TIM_32B_EnableExtTriggerIn(). 418 */ 419 typedef struct 420 { 421 TIM_32B_ExtTriggerInDiv_Type InDiv; /*!< The division of filtered input. */ 422 TIM_32B_ExtTriggerInFilter_Type InFilter; /*!< The filter sampling time for initial input. */ 423 TIM_32B_ExtTriggerPinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */ 424 } TIM_32B_ExtTriggerInConf_Type; 425 426 /*! 427 * @brief This type of structure instance is used to setup the dma burst configuration when calling the @ref TIM_32B_EnableDMABurst(). 428 */ 429 typedef struct 430 { 431 TIM_32B_DMABurstBaseAddr_Type BaseAddr; /*!< The base address to start transfer. */ 432 TIM_32B_DMABurstBaseLen_Type Length; /*!< Length of sequential registers DMA burst visits. */ 433 } TIM_32B_DMABurstConf_Type; 434 435 /*! 436 * @brief Set the timer's step for indicated TIM module. 437 * 438 * @param TIMx TIM_32B instance. 439 * @param init Pointer to the initialization structure. See to @ref TIM_32B_Init_Type. 440 * @return val 'true' to set the timer's step successfully, 'false' to fail because the invalid StepFreqHz. 441 */ 442 bool TIM_32B_Init(TIM_32B_Type * TIMx, TIM_32B_Init_Type * init); 443 444 /*! 445 * @brief Start counting. 446 * 447 * @param TIMx TIM_32B instance. 448 * @return None. 449 */ 450 void TIM_32B_Start(TIM_32B_Type * TIMx); 451 452 /*! 453 * @brief Stop counting immediately. 454 * 455 * @param TIMx TIM_32B instance. 456 * @return None. 457 */ 458 void TIM_32B_Stop(TIM_32B_Type * TIMx); 459 460 /*! 461 * @brief Get the indicated TIMx Counter value. 462 * 463 * @param TIMx TIM_32B_Type instance. 464 * @return The current value of the counter register. 465 */ 466 uint32_t TIM_32B_GetCounterValue(TIM_32B_Type * TIMx); 467 468 /*! 469 * @brief Clear the indicated TIMx Counter. 470 * 471 * @param TIMx TIM_32B_Type instance. 472 * @return None. 473 */ 474 void TIM_32B_ClearCounterValue(TIM_32B_Type * TIMx); 475 476 /*! 477 * @brief Enable the TIM_32B interrupts. 478 * 479 * @param TIMx TIM_32B_Type instance. 480 * @param interrupts Interrupts to be enabled.See to @ref TIM_32B_INT. 481 * @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs. 482 * @return None. 483 */ 484 void TIM_32B_EnableInterrupts(TIM_32B_Type * TIMx, uint32_t interrupts, bool enable); 485 486 /*! 487 * @brief Enable the TIM_32B DMAs. 488 * 489 * @param TIMx TIM_32B_Type instance. 490 * @param dmas DMA masks to be enabled. See to @ref TIM_32B_DMA. 491 * @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs. 492 * @return None. 493 */ 494 void TIM_32B_EnableDMA(TIM_32B_Type * TIMx, uint32_t dmas, bool enable); 495 496 /*! 497 * @brief Software trigger events to call interrupts or DMAs. 498 * 499 * Can simultaneously trigger multiple events. 500 * 501 * @param TIMx TIM_32B instance. See to @ref TIM_32B_SWTRG. 502 * @param swtrgs Trigger the events to generate interrupts. 503 */ 504 void TIM_32B_DoSwTrigger(TIM_32B_Type * TIMx, uint32_t swtrgs); 505 506 /*! 507 * @brief Get the status of the indicated timer. 508 * 509 * @param TIMx TIM_32B_Type instance. 510 * @return Interrupt status flags. See to @ref TIM_32B_INT_STATUS. 511 */ 512 uint32_t TIM_32B_GetInterruptStatus(TIM_32B_Type * TIMx); 513 514 /*! 515 * @brief Clear the status of indicated interrupt. 516 * 517 * @param TIMx TIM_32B_Type instance. 518 * @param status The required clear flag type. See to @ref TIM_32B_INT_STATUS. 519 * @return None. 520 */ 521 void TIM_32B_ClearInterruptStatus(TIM_32B_Type * TIMx, uint32_t status); 522 523 /*! 524 * @brief Enable the output compare feature of indicated timer channel. 525 * 526 * If need to change the IO mode of the working channel, channel must be disabled first, then modify. 527 * 528 * @param TIMx TIM_32B_Type instance. 529 * @param channel Output channel instance. See to @ref TIM_32B_CHANNEL_SELECTION. 530 * @param conf Pointer to the configuration structure. See to @ref TIM_32B_OutputCompareConf_Type. 531 * @return None. 532 */ 533 void TIM_32B_EnableOutputCompare(TIM_32B_Type * TIMx, uint32_t channel, TIM_32B_OutputCompareConf_Type * conf); 534 535 /*! 536 * @brief Enable the input capture feature of indicated timer channel. 537 * 538 * If need to change the IO mode of the working channel, channel must be disabled first, then modify. 539 * 540 * @param TIMx TIM_32B_Type instance. 541 * @param channel Input channel instance. See to @ref TIM_32B_CHANNEL_SELECTION. 542 * @param conf Pointer to the configuration structure. See to @ref TIM_32B_InputCaptureConf_Type. 543 * @return None. 544 */ 545 void TIM_32B_EnableInputCapture(TIM_32B_Type * TIMx, uint32_t channel, TIM_32B_InputCaptureConf_Type * conf); 546 547 /*! 548 * @brief Get the value of the indicated timer channel. 549 * 550 * When capture event happens, counter value will be kept in its indicated channel. 551 * 552 * @param TIMx TIM_32B_Type instance. 553 * @param channel Channel instance to get the value. See to @ref TIM_32B_CHANNEL_SELECTION. 554 * @return Value of the indiacted timer channel. 555 */ 556 uint32_t TIM_32B_GetChannelValue(TIM_32B_Type * TIMx, uint32_t channel); 557 558 /*! 559 * @brief Put the value into the indicated timer channel. 560 * 561 * When in output compare, channel value would be the compared with counter value. 562 * 563 * @param TIMx TIM_32B_Type instance. 564 * @param channel Channel instance to put the value. See to @ref TIM_32B_CHANNEL_SELECTION. 565 * @param value The value to be set in the indicated timer channel. 566 * @return None. 567 */ 568 void TIM_32B_PutChannelValue(TIM_32B_Type * TIMx, uint32_t channel, uint32_t value); 569 570 /*! 571 * @brief Enable the dead area of the indicated timer. 572 * 573 * @param TIMx TIM_32B_Type instance. 574 * @param conf Pointer to the configuration structure. See to @ref TIM_32B_DeadAreaConf_Type. 575 * @return None. 576 */ 577 void TIM_32B_EnableDeadArea(TIM_32B_Type * TIMx, TIM_32B_DeadAreaConf_Type * conf); 578 579 /*! 580 * @brief Enable the master mode of the indicated timer. 581 * 582 * Master mode transfer the timer signal to other timers. 583 * 584 * @param TIMx TIM_32B_Type instance. 585 * @param conf Pointer to the configuration structure. See to @ref TIM_32B_MasterModeConf_Type. 586 * @return None. 587 */ 588 void TIM_32B_EnableMasterMode(TIM_32B_Type * TIMx, TIM_32B_MasterModeConf_Type * conf); 589 590 /*! 591 * @brief Enable the slave mode of the indicated timer. 592 * 593 * Slave mode can control the working state of counter. 594 * 595 * @param TIMx TIM_32B_Type instance. 596 * @param conf Pointer to the configuration structure. See to @ref TIM_32B_SlaveModeConf_Type. 597 * @return None. 598 */ 599 void TIM_32B_EnableSlaveMode(TIM_32B_Type * TIMx, TIM_32B_SlaveModeConf_Type * conf); 600 601 /*! 602 * @brief Enable the external trigger input of the indicated counter. 603 * 604 * External trigger signal will trigger counter do addition. 605 * Its div and filter along with the counter StepFreqHz will affect. 606 * 607 * @param TIMx TIM_32B_Type instance. 608 * @param conf Pointer to the configuration structure. See to @ref TIM_32B_ExtTriggerInConf_Type. 609 * @return None. 610 */ 611 void TIM_32B_EnableExtTriggerIn(TIM_32B_Type * TIMx, TIM_32B_ExtTriggerInConf_Type * conf); 612 613 /*! 614 * @brief Enable the dma burst transfer of the indicated timer. 615 * 616 * @param TIMx TIM_32B_Type instance. 617 * @param conf Pointer to the configuration structure. See to @ref TIM_32B_DMABurstConf_Type. 618 * @return Address of DMA Burst transfer base register address. 619 */ 620 uint32_t TIM_32B_EnableDMABurst(TIM_32B_Type * TIMx, TIM_32B_DMABurstConf_Type * conf); 621 622 /*! 623 * @brief Get the encoder rotating direction and the counted encoder pulse times. 624 * 625 * @param TIMx TIM_32B_Type instance. 626 * @param value The counter value for pulse times. 627 * @return Encoder rotating direction. See to @ref TIM_32B_EncoderDirection_Type. 628 */ 629 TIM_32B_EncoderDirection_Type TIM_32B_GetEncoder(TIM_32B_Type * TIMx, uint32_t * value); 630 631 /*! 632 *@} 633 */ 634 #endif /* __HAL_TIM_32B_H__ */ 635 636