Home
last modified time | relevance | path

Searched defs:TIM_CR1_UDIS (Results 1 – 25 of 37) sorted by relevance

12

/bsp/mm32f327x/Libraries/MM32F327x/Include/
A Dreg_tim.h124 #define TIM_CR1_UDIS (0x01U << TIM_CR1_UDIS_Pos) ///< Update disable macro
/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/
A Dft32f030x6.h3366 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ macro
A Dft32f032x8.h3449 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ macro
A Dft32f030x8.h3407 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ macro
A Dft32f032x6.h3448 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ macro
A Dft32f072x8.h3458 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ macro
A Dft32f072xb.h3687 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ macro
/bsp/mm32l3xx/Libraries/MM32L3xx/Include/
A DMM32L3xx.h2951 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ macro
/bsp/mm32f103x/Libraries/MM32F103/Include/
A DMM32F103.h2960 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ macro
/bsp/tkm32F499/Libraries/CMSIS_and_startup/
A Dtk499.h3254 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ macro
/bsp/mm32l07x/Libraries/MM32L0xx/Include/
A DMM32L0xx.h3066 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ macro
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/HK32F0xx/Include/
A Dhk32f030x4x6x8.h4216 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ macro
A Dhk32f04ax4x6x8.h4196 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ macro
A Dhk32f031x4x6.h4267 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ macro
/bsp/airm2m/air32f103/libraries/AIR32F10xLib/inc/
A Dair32f10x.h3429 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */ macro
/bsp/stm32/libraries/STM32L1xx_HAL/CMSIS/Device/ST/STM32L1xx/Include/
A Dstm32l100xb.h5589 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ macro
A Dstm32l100xba.h5737 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ macro
A Dstm32l151xb.h5541 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ macro
A Dstm32l151xba.h5617 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ macro
A Dstm32l152xb.h5691 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ macro
A Dstm32l152xba.h5752 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ macro
A Dstm32l100xc.h6306 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ macro
A Dstm32l151xca.h6559 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ macro
A Dstm32l151xc.h6474 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ macro
A Dstm32l162xdx.h6913 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ macro

Completed in 748 milliseconds

12