1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_tim.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_TIM_H 22 #define __REG_TIM_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 40 41 42 43 44 45 46 //////////////////////////////////////////////////////////////////////////////// 47 /// @brief TIM Base Address Definition 48 //////////////////////////////////////////////////////////////////////////////// 49 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) ///< Base Address: 0x40012C00 50 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) ///< Base Address: 0x40000000 51 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) ///< Base Address: 0x40000400 52 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) ///< Base Address: 0x40000800 53 54 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) ///< Base Address: 0x40000C00 55 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) ///< Base Address: 0x40001000 56 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) ///< Base Address: 0x40001400 57 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400) ///< Base Address: 0x40013400 58 59 60 61 62 63 64 65 //////////////////////////////////////////////////////////////////////////////// 66 /// @brief Timer Register Structure Definition 67 //////////////////////////////////////////////////////////////////////////////// 68 typedef struct { 69 __IO u32 CR1; ///< TIM control register 1, offset: 0x00 70 __IO u32 CR2; ///< TIM control register 2, offset: 0x04 71 __IO u32 SMCR; ///< TIM slave Mode Control register, offset: 0x08 72 __IO u32 DIER; ///< TIM DMA/interrupt enable register, offset: 0x0C 73 __IO u32 SR; ///< TIM status register, offset: 0x10 74 __IO u32 EGR; ///< TIM event generation register, offset: 0x14 75 __IO u32 CCMR1; ///< TIM capture/compare mode register 1, offset: 0x18 76 __IO u32 CCMR2; ///< TIM capture/compare mode register 2, offset: 0x1C 77 __IO u32 CCER; ///< TIM capture/compare enable register, offset: 0x20 78 __IO u32 CNT; ///< TIM counter register, offset: 0x24 79 __IO u32 PSC; ///< TIM prescaler register, offset: 0x28 80 __IO u32 ARR; ///< TIM auto-reload register, offset: 0x2C 81 __IO u32 RCR; ///< TIM repetition counter register, offset: 0x30 82 __IO u32 CCR1; ///< TIM capture/compare register 1, offset: 0x34 83 __IO u32 CCR2; ///< TIM capture/compare register 2, offset: 0x38 84 __IO u32 CCR3; ///< TIM capture/compare register 3, offset: 0x3C 85 __IO u32 CCR4; ///< TIM capture/compare register 4, offset: 0x40 86 __IO u32 BDTR; ///< TIM break and dead-time register, offset: 0x44 87 __IO u32 DCR; ///< TIM DMA control register, offset: 0x48 88 __IO u32 DMAR; ///< TIM DMA address for full transfer register, offset: 0x4C 89 __IO u32 OR; ///< Option register, offset: 0x50 90 __IO u32 CCMR3; ///< TIM capture/compare mode register 3, offset: 0x54 91 __IO u32 CCR5; ///< TIM capture/compare register 5, offset: 0x58 92 __IO u32 PDER; ///< PWM Shift repeat enable register, offset: 0x5C 93 __IO u32 CCR1FALL; ///< PWM shift count CCR1 register, offset: 0x60 94 __IO u32 CCR2FALL; ///< PWM shift count CCR2 register, offset: 0x64 95 __IO u32 CCR3FALL; ///< PWM shift count CCR3 register, offset: 0x68 96 __IO u32 CCR4FALL; ///< PWM shift count CCR4 register, offset: 0x6c 97 __IO u32 CCR5FALL; ///< PWM shift count CCR5 register, offset: 0x70 98 } TIM_TypeDef; 99 100 101 //////////////////////////////////////////////////////////////////////////////// 102 /// @brief TIM type pointer Definition 103 //////////////////////////////////////////////////////////////////////////////// 104 #define TIM1 ((TIM_TypeDef*) TIM1_BASE) 105 #define TIM2 ((TIM_TypeDef*) TIM2_BASE) 106 #define TIM3 ((TIM_TypeDef*) TIM3_BASE) 107 #define TIM4 ((TIM_TypeDef*) TIM4_BASE) 108 109 #define TIM5 ((TIM_TypeDef*) TIM5_BASE) 110 #define TIM6 ((TIM_TypeDef*) TIM6_BASE) 111 #define TIM7 ((TIM_TypeDef*) TIM7_BASE) 112 113 #define TIM8 ((TIM_TypeDef*) TIM8_BASE) 114 115 116 117 118 //////////////////////////////////////////////////////////////////////////////// 119 /// @brief TIM_CR1 Register Bit Definition 120 //////////////////////////////////////////////////////////////////////////////// 121 #define TIM_CR1_CEN_Pos (0) 122 #define TIM_CR1_CEN (0x01U << TIM_CR1_CEN_Pos) ///< Counter enable 123 #define TIM_CR1_UDIS_Pos (1) 124 #define TIM_CR1_UDIS (0x01U << TIM_CR1_UDIS_Pos) ///< Update disable 125 #define TIM_CR1_URS_Pos (2) 126 #define TIM_CR1_URS (0x01U << TIM_CR1_URS_Pos) ///< Update request source 127 #define TIM_CR1_OPM_Pos (3) 128 #define TIM_CR1_OPM (0x01U << TIM_CR1_OPM_Pos) ///< One pulse mode 129 #define TIM_CR1_DIR_Pos (4) 130 #define TIM_CR1_DIR (0x01U << TIM_CR1_DIR_Pos) ///< Direction 131 #define TIM_CR1_CMS_Pos (5) 132 #define TIM_CR1_CMS (0x03U << TIM_CR1_CMS_Pos) ///< CMS[1:0] bits (Center-aligned mode selection) 133 #define TIM_CR1_CMS_EDGEALIGNED (0x00U << TIM_CR1_CMS_Pos) ///< Edge-aligned mode 134 #define TIM_CR1_CMS_CENTERALIGNED1 (0x01U << TIM_CR1_CMS_Pos) ///< Center-aligned mode 1 135 #define TIM_CR1_CMS_CENTERALIGNED2 (0x02U << TIM_CR1_CMS_Pos) ///< Center-aligned mode 2 136 #define TIM_CR1_CMS_CENTERALIGNED3 (0x03U << TIM_CR1_CMS_Pos) ///< Center-aligned mode 3 137 #define TIM_CR1_ARPEN_Pos (7) 138 #define TIM_CR1_ARPEN (0x01U << TIM_CR1_ARPEN_Pos) ///< Auto-reload preload enable 139 #define TIM_CR1_CKD_Pos (8) 140 #define TIM_CR1_CKD (0x03U << TIM_CR1_CKD_Pos) ///< CKD[1:0] bits (clock division) 141 #define TIM_CR1_CKD_DIV1 (0x00U << TIM_CR1_CKD_Pos) ///< Divided by 1 142 #define TIM_CR1_CKD_DIV2 (0x01U << TIM_CR1_CKD_Pos) ///< Divided by 2 143 #define TIM_CR1_CKD_DIV4 (0x02U << TIM_CR1_CKD_Pos) ///< Divided by 4 144 145 //////////////////////////////////////////////////////////////////////////////// 146 /// @brief TIM_CR2 Register Bit Definition 147 //////////////////////////////////////////////////////////////////////////////// 148 #define TIM_CR2_CCPC_Pos (0) 149 #define TIM_CR2_CCPC (0x01U << TIM_CR2_CCPC_Pos) ///< Capture/Compare Preloaded Control 150 #define TIM_CR2_CCUS_Pos (2) 151 #define TIM_CR2_CCUS (0x01U << TIM_CR2_CCUS_Pos) ///< Capture/Compare Control Update Selection 152 #define TIM_CR2_CCDS_Pos (3) 153 #define TIM_CR2_CCDS (0x01U << TIM_CR2_CCDS_Pos) ///< Capture/Compare DMA Selection 154 #define TIM_CR2_MMS_Pos (4) 155 #define TIM_CR2_MMS (0x07U << TIM_CR2_MMS_Pos) ///< MMS[2:0] bits (Master Mode Selection) 156 #define TIM_CR2_MMS_RESET (0x00U << TIM_CR2_MMS_Pos) ///< Master Mode Select: Reset 157 #define TIM_CR2_MMS_ENABLE (0x01U << TIM_CR2_MMS_Pos) ///< Master Mode Select: Enable 158 #define TIM_CR2_MMS_UPDATE (0x02U << TIM_CR2_MMS_Pos) ///< Master Mode Select: Update 159 #define TIM_CR2_MMS_OC1 (0x03U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC1 160 #define TIM_CR2_MMS_OC1REF (0x04U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC1Ref 161 #define TIM_CR2_MMS_OC2REF (0x05U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC2Ref 162 #define TIM_CR2_MMS_OC3REF (0x06U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC3Ref 163 #define TIM_CR2_MMS_OC4REF (0x07U << TIM_CR2_MMS_Pos) ///< Master Mode Select: OC4Ref 164 #define TIM_CR2_TI1S_Pos (7) 165 #define TIM_CR2_TI1S (0x01U << TIM_CR2_TI1S_Pos) ///< TI1 Selection 166 #define TIM_CR2_OIS1_Pos (8) 167 #define TIM_CR2_OIS1 (0x01U << TIM_CR2_OIS1_Pos) ///< Output Idle state 1 (OC1 output) 168 #define TIM_CR2_OIS1N_Pos (9) 169 #define TIM_CR2_OIS1N (0x01U << TIM_CR2_OIS1N_Pos) ///< Output Idle state 1 (OC1N output) 170 #define TIM_CR2_OIS2_Pos (10) 171 #define TIM_CR2_OIS2 (0x01U << TIM_CR2_OIS2_Pos) ///< Output Idle state 2 (OC2 output) 172 #define TIM_CR2_OIS2N_Pos (11) 173 #define TIM_CR2_OIS2N (0x01U << TIM_CR2_OIS2N_Pos) ///< Output Idle state 2 (OC2N output) 174 #define TIM_CR2_OIS3_Pos (12) 175 #define TIM_CR2_OIS3 (0x01U << TIM_CR2_OIS3_Pos) ///< Output Idle state 3 (OC3 output) 176 #define TIM_CR2_OIS3N_Pos (13) 177 #define TIM_CR2_OIS3N (0x01U << TIM_CR2_OIS3N_Pos) ///< Output Idle state 3 (OC3N output) 178 #define TIM_CR2_OIS4_Pos (14) 179 #define TIM_CR2_OIS4 (0x01U << TIM_CR2_OIS4_Pos) ///< Output Idle state 4 (OC4 output) 180 181 182 #define TIM_CR2_OIS5_Pos (16) 183 #define TIM_CR2_OIS5 (0x01U << TIM_CR2_OIS5_Pos) ///< Output Idle state 5 (OC5 output) 184 185 //////////////////////////////////////////////////////////////////////////////// 186 /// @brief TIM_SMCR Register Bit Definition 187 //////////////////////////////////////////////////////////////////////////////// 188 #define TIM_SMCR_SMS_Pos (0) 189 #define TIM_SMCR_SMS (0x07U << TIM_SMCR_SMS_Pos) ///< SMS[2:0] bits (Slave mode selection) 190 #define TIM_SMCR_SMS_OFF (0x00U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: OFF 191 #define TIM_SMCR_SMS_ENCODER1 (0x01U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Encoder1 192 #define TIM_SMCR_SMS_ENCODER2 (0x02U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Encoder2 193 #define TIM_SMCR_SMS_ENCODER3 (0x03U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Encoder3 194 #define TIM_SMCR_SMS_RESET (0x04U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Reset 195 #define TIM_SMCR_SMS_GATED (0x05U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Gated 196 #define TIM_SMCR_SMS_TRIGGER (0x06U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: Trigger 197 #define TIM_SMCR_SMS_EXTERNAL1 (0x07U << TIM_SMCR_SMS_Pos) ///< Slave Mode select: External1 198 199 #define TIM_SMCR_OCCS_Pos (3) 200 #define TIM_SMCR_OCCS (0x01U << TIM_SMCR_OCCS_Pos) ///< Output compare clear selection 201 202 #define TIM_SMCR_TS_Pos (4) 203 #define TIM_SMCR_TS (0x07U << TIM_SMCR_TS_Pos) ///< TS[2:0] bits (Trigger selection) 204 #define TIM_SMCR_TS_ITR0 (0x00U << TIM_SMCR_TS_Pos) ///< Internal Trigger 0 (ITR0) 205 #define TIM_SMCR_TS_ITR1 (0x01U << TIM_SMCR_TS_Pos) ///< Internal Trigger 1 (ITR1) 206 #define TIM_SMCR_TS_ITR2 (0x02U << TIM_SMCR_TS_Pos) ///< Internal Trigger 2 (ITR2) 207 #define TIM_SMCR_TS_ITR3 (0x03U << TIM_SMCR_TS_Pos) ///< Internal Trigger 3 (ITR3) 208 #define TIM_SMCR_TS_TI1F_ED (0x04U << TIM_SMCR_TS_Pos) ///< TI1 Edge Detector (TI1F_ED) 209 #define TIM_SMCR_TS_TI1FP1 (0x05U << TIM_SMCR_TS_Pos) ///< Filtered Timer Input 1 (TI1FP1) 210 #define TIM_SMCR_TS_TI2FP2 (0x06U << TIM_SMCR_TS_Pos) ///< Filtered Timer Input 2 (TI2FP2) 211 #define TIM_SMCR_TS_ETRF (0x07U << TIM_SMCR_TS_Pos) ///< External Trigger input (ETRF) 212 #define TIM_SMCR_MSM_Pos (7) 213 #define TIM_SMCR_MSM (0x01U << TIM_SMCR_MSM_Pos) ///< Master/slave mode 214 #define TIM_SMCR_ETF_Pos (8) 215 #define TIM_SMCR_ETF (0x0FU << TIM_SMCR_ETF_Pos) ///< ETF[3:0] bits (External trigger filter) 216 #define TIM_SMCR_ETF_0 (0x01U << TIM_SMCR_ETF_Pos) ///< Bit 0 217 #define TIM_SMCR_ETF_1 (0x02U << TIM_SMCR_ETF_Pos) ///< Bit 1 218 #define TIM_SMCR_ETF_2 (0x04U << TIM_SMCR_ETF_Pos) ///< Bit 2 219 #define TIM_SMCR_ETF_3 (0x08U << TIM_SMCR_ETF_Pos) ///< Bit 3 220 #define TIM_SMCR_ETPS_Pos (12) 221 #define TIM_SMCR_ETPS (0x03U << TIM_SMCR_ETPS_Pos) ///< ETPS[1:0] bits (External trigger prescaler) 222 #define TIM_SMCR_ETPS_OFF (0x00U << TIM_SMCR_ETPS_Pos) ///< Prescaler OFF 223 #define TIM_SMCR_ETPS_DIV2 (0x01U << TIM_SMCR_ETPS_Pos) ///< ETRP frequency divided by 2 224 #define TIM_SMCR_ETPS_DIV4 (0x02U << TIM_SMCR_ETPS_Pos) ///< ETRP frequency divided by 4 225 #define TIM_SMCR_ETPS_DIV8 (0x03U << TIM_SMCR_ETPS_Pos) ///< ETRP frequency divided by 8 226 #define TIM_SMCR_ECEN_Pos (14) 227 #define TIM_SMCR_ECEN (0x01U << TIM_SMCR_ECEN_Pos) ///< External clock enable 228 #define TIM_SMCR_ETP_Pos (15) 229 #define TIM_SMCR_ETP (0x01U << TIM_SMCR_ETP_Pos) ///< External trigger polarity 230 //////////////////////////////////////////////////////////////////////////////// 231 /// @brief TIM_DIER Register Bit Definition 232 //////////////////////////////////////////////////////////////////////////////// 233 #define TIM_DIER_UI_Pos (0) 234 #define TIM_DIER_UI (0x01U << TIM_DIER_UI_Pos) ///< Update interrupt enable 235 #define TIM_DIER_CC1I_Pos (1) 236 #define TIM_DIER_CC1I (0x01U << TIM_DIER_CC1I_Pos) ///< Capture/Compare 1 interrupt enable 237 #define TIM_DIER_CC2I_Pos (2) 238 #define TIM_DIER_CC2I (0x01U << TIM_DIER_CC2I_Pos) ///< Capture/Compare 2 interrupt enable 239 #define TIM_DIER_CC3I_Pos (3) 240 #define TIM_DIER_CC3I (0x01U << TIM_DIER_CC3I_Pos) ///< Capture/Compare 3 interrupt enable 241 #define TIM_DIER_CC4I_Pos (4) 242 #define TIM_DIER_CC4I (0x01U << TIM_DIER_CC4I_Pos) ///< Capture/Compare 4 interrupt enable 243 #define TIM_DIER_COMI_Pos (5) 244 #define TIM_DIER_COMI (0x01U << TIM_DIER_COMI_Pos) ///< COM interrupt enable 245 #define TIM_DIER_TI_Pos (6) 246 #define TIM_DIER_TI (0x01U << TIM_DIER_TI_Pos) ///< Trigger interrupt enable 247 #define TIM_DIER_BI_Pos (7) 248 #define TIM_DIER_BI (0x01U << TIM_DIER_BI_Pos) ///< Break interrupt enable 249 #define TIM_DIER_UD_Pos (8) 250 #define TIM_DIER_UD (0x01U << TIM_DIER_UD_Pos) ///< Update DMA request enable 251 #define TIM_DIER_CC1D_Pos (9) 252 #define TIM_DIER_CC1D (0x01U << TIM_DIER_CC1D_Pos) ///< Capture/Compare 1 DMA request enable 253 #define TIM_DIER_CC2D_Pos (10) 254 #define TIM_DIER_CC2D (0x01U << TIM_DIER_CC2D_Pos) ///< Capture/Compare 2 DMA request enable 255 #define TIM_DIER_CC3D_Pos (11) 256 #define TIM_DIER_CC3D (0x01U << TIM_DIER_CC3D_Pos) ///< Capture/Compare 3 DMA request enable 257 #define TIM_DIER_CC4D_Pos (12) 258 #define TIM_DIER_CC4D (0x01U << TIM_DIER_CC4D_Pos) ///< Capture/Compare 4 DMA request enable 259 #define TIM_DIER_COMD_Pos (13) 260 #define TIM_DIER_COMD (0x01U << TIM_DIER_COMD_Pos) ///< COM DMA request enable 261 #define TIM_DIER_TD_Pos (14) 262 #define TIM_DIER_TD (0x01U << TIM_DIER_TD_Pos) ///< Trigger DMA request enable 263 #define TIM_DIER_CC5I_Pos (16) 264 #define TIM_DIER_CC5I (0x01U << TIM_DIER_CC5I_Pos) ///< Capture/Compare 5 interrupt enable 265 266 //////////////////////////////////////////////////////////////////////////////// 267 /// @brief TIM_SR Register Bit Definition 268 //////////////////////////////////////////////////////////////////////////////// 269 #define TIM_SR_UI_Pos (0) 270 #define TIM_SR_UI (0x01U << TIM_SR_UI_Pos) ///< Update interrupt Flag 271 #define TIM_SR_CC1I_Pos (1) 272 #define TIM_SR_CC1I (0x01U << TIM_SR_CC1I_Pos) ///< Capture/Compare 1 interrupt Flag 273 #define TIM_SR_CC2I_Pos (2) 274 #define TIM_SR_CC2I (0x01U << TIM_SR_CC2I_Pos) ///< Capture/Compare 2 interrupt Flag 275 #define TIM_SR_CC3I_Pos (3) 276 #define TIM_SR_CC3I (0x01U << TIM_SR_CC3I_Pos) ///< Capture/Compare 3 interrupt Flag 277 #define TIM_SR_CC4I_Pos (4) 278 #define TIM_SR_CC4I (0x01U << TIM_SR_CC4I_Pos) ///< Capture/Compare 4 interrupt Flag 279 #define TIM_SR_COMI_Pos (5) 280 #define TIM_SR_COMI (0x01U << TIM_SR_COMI_Pos) ///< COM interrupt Flag 281 #define TIM_SR_TI_Pos (6) 282 #define TIM_SR_TI (0x01U << TIM_SR_TI_Pos) ///< Trigger interrupt Flag 283 #define TIM_SR_BI_Pos (7) 284 #define TIM_SR_BI (0x01U << TIM_SR_BI_Pos) ///< Break interrupt Flag 285 #define TIM_SR_CC1O_Pos (9) 286 #define TIM_SR_CC1O (0x01U << TIM_SR_CC1O_Pos) ///< Capture/Compare 1 Overcapture Flag 287 #define TIM_SR_CC2O_Pos (10) 288 #define TIM_SR_CC2O (0x01U << TIM_SR_CC2O_Pos) ///< Capture/Compare 2 Overcapture Flag 289 #define TIM_SR_CC3O_Pos (11) 290 #define TIM_SR_CC3O (0x01U << TIM_SR_CC3O_Pos) ///< Capture/Compare 3 Overcapture Flag 291 #define TIM_SR_CC4O_Pos (12) 292 #define TIM_SR_CC4O (0x01U << TIM_SR_CC4O_Pos) ///< Capture/Compare 4 Overcapture Flag 293 294 #define TIM_SR_CC5I_Pos (16) 295 #define TIM_SR_CC5I (0x01U << TIM_SR_CC5I_Pos) ///< Capture/Compare 5 interrupt Flag 296 297 //////////////////////////////////////////////////////////////////////////////// 298 /// @brief TIM_EGR Register Bit Definition 299 //////////////////////////////////////////////////////////////////////////////// 300 #define TIM_EGR_UG_Pos (0) 301 #define TIM_EGR_UG (0x01U << TIM_EGR_UG_Pos) ///< Update Generation 302 #define TIM_EGR_CC1G_Pos (1) 303 #define TIM_EGR_CC1G (0x01U << TIM_EGR_CC1G_Pos) ///< Capture/Compare 1 Generation 304 #define TIM_EGR_CC2G_Pos (2) 305 #define TIM_EGR_CC2G (0x01U << TIM_EGR_CC2G_Pos) ///< Capture/Compare 2 Generation 306 #define TIM_EGR_CC3G_Pos (3) 307 #define TIM_EGR_CC3G (0x01U << TIM_EGR_CC3G_Pos) ///< Capture/Compare 3 Generation 308 #define TIM_EGR_CC4G_Pos (4) 309 #define TIM_EGR_CC4G (0x01U << TIM_EGR_CC4G_Pos) ///< Capture/Compare 4 Generation 310 #define TIM_EGR_COMG_Pos (5) 311 #define TIM_EGR_COMG (0x01U << TIM_EGR_COMG_Pos) ///< Capture/Compare Control Update Generation 312 #define TIM_EGR_TG_Pos (6) 313 #define TIM_EGR_TG (0x01U << TIM_EGR_TG_Pos) ///< Trigger Generation 314 #define TIM_EGR_BG_Pos (7) 315 #define TIM_EGR_BG (0x01U << TIM_EGR_BG_Pos) ///< Break Generation 316 317 #define TIM_EGR_CC5G_Pos (16) 318 #define TIM_EGR_CC5G (0x01U << TIM_EGR_CC5G_Pos) ///< Capture/Compare 5 Generation 319 320 //////////////////////////////////////////////////////////////////////////////// 321 /// @brief TIM_CCMR1 Register Bit Definition 322 //////////////////////////////////////////////////////////////////////////////// 323 #define TIM_CCMR1_CC1S_Pos (0) 324 #define TIM_CCMR1_CC1S (0x03U << TIM_CCMR1_CC1S_Pos) ///< CC1S[1:0] bits (Capture/Compare 1 Selection) 325 #define TIM_CCMR1_CC1S_OC (0x00U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as output 326 #define TIM_CCMR1_CC1S_DIRECTTI (0x01U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as input, IC1 is mapped on TI1 327 #define TIM_CCMR1_CC1S_INDIRECTTI (0x02U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as input, IC1 is mapped on TI2 328 #define TIM_CCMR1_CC1S_TRC (0x03U << TIM_CCMR1_CC1S_Pos) ///< Channel is configured as input, IC1 is mapped on TRC 329 #define TIM_CCMR1_OC1FEN_Pos (2) 330 #define TIM_CCMR1_OC1FEN (0x01U << TIM_CCMR1_OC1FEN_Pos) ///< Output Compare 1 Fast enable 331 332 #define TIM_CCMR1_OC1PEN_Pos (3) 333 #define TIM_CCMR1_OC1PEN (0x01U << TIM_CCMR1_OC1PEN_Pos) ///< Output Compare 1 Preload enable 334 #define TIM_CCMR1_OC1M_Pos (4) 335 #define TIM_CCMR1_OC1M (0x07U << TIM_CCMR1_OC1M_Pos) ///< OC1M[2:0] bits (Output Compare 1 Mode) 336 #define TIM_CCMR1_OC1M_TIMING (0x00U << TIM_CCMR1_OC1M_Pos) ///< Timing 337 #define TIM_CCMR1_OC1M_ACTIVE (0x01U << TIM_CCMR1_OC1M_Pos) ///< Active 338 #define TIM_CCMR1_OC1M_INACTIVE (0x02U << TIM_CCMR1_OC1M_Pos) ///< Inactive 339 #define TIM_CCMR1_OC1M_TOGGLE (0x03U << TIM_CCMR1_OC1M_Pos) ///< Toggle 340 #define TIM_CCMR1_OC1M_FORCEINACTIVE (0x04U << TIM_CCMR1_OC1M_Pos) ///< Forceinactive 341 #define TIM_CCMR1_OC1M_FORCEACTIVE (0x05U << TIM_CCMR1_OC1M_Pos) ///< Forceactive 342 #define TIM_CCMR1_OC1M_PWM1 (0x06U << TIM_CCMR1_OC1M_Pos) ///< PWM1 343 #define TIM_CCMR1_OC1M_PWM2 (0x07U << TIM_CCMR1_OC1M_Pos) ///< PWM2 344 345 #define TIM_CCMR1_OC1CEN_Pos (7) 346 #define TIM_CCMR1_OC1CEN (0x01U << TIM_CCMR1_OC1CEN_Pos) ///< Output Compare 1Clear Enable 347 #define TIM_CCMR1_CC2S_Pos (8) 348 #define TIM_CCMR1_CC2S (0x03U << TIM_CCMR1_CC2S_Pos) ///< CC2S[1:0] bits (Capture/Compare 2 Selection) 349 #define TIM_CCMR1_CC2S_OC (0x00U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as output 350 #define TIM_CCMR1_CC2S_DIRECTTI (0x01U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as input, IC2 is mapped on TI2 351 #define TIM_CCMR1_CC2S_INDIRECTTI (0x02U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as input, IC2 is mapped on TI1 352 #define TIM_CCMR1_CC2S_TRC (0x03U << TIM_CCMR1_CC2S_Pos) ///< Channel is configured as input, IC2 is mapped on TRC 353 #define TIM_CCMR1_OC2FEN_Pos (10) 354 #define TIM_CCMR1_OC2FEN (0x01U << TIM_CCMR1_OC2FEN_Pos) ///< Output Compare 2 Fast enable 355 #define TIM_CCMR1_OC2PEN_Pos (11) 356 #define TIM_CCMR1_OC2PEN (0x01U << TIM_CCMR1_OC2PEN_Pos) ///< Output Compare 2 Preload enable 357 #define TIM_CCMR1_OC2M_Pos (12) 358 #define TIM_CCMR1_OC2M (0x07U << TIM_CCMR1_OC2M_Pos) ///< OC2M[2:0] bits (Output Compare 2 Mode) 359 #define TIM_CCMR1_OC2M_TIMING (0x00U << TIM_CCMR1_OC2M_Pos) ///< Timing 360 #define TIM_CCMR1_OC2M_ACTIVE (0x01U << TIM_CCMR1_OC2M_Pos) ///< Active 361 #define TIM_CCMR1_OC2M_INACTIVE (0x02U << TIM_CCMR1_OC2M_Pos) ///< Inactive 362 #define TIM_CCMR1_OC2M_TOGGLE (0x03U << TIM_CCMR1_OC2M_Pos) ///< Toggle 363 #define TIM_CCMR1_OC2M_FORCEINACTIVE (0x04U << TIM_CCMR1_OC2M_Pos) ///< Forceinactive 364 #define TIM_CCMR1_OC2M_FORCEACTIVE (0x05U << TIM_CCMR1_OC2M_Pos) ///< Forceactive 365 #define TIM_CCMR1_OC2M_PWM1 (0x06U << TIM_CCMR1_OC2M_Pos) ///< PWM1 366 #define TIM_CCMR1_OC2M_PWM2 (0x07U << TIM_CCMR1_OC2M_Pos) ///< PWM2 367 #define TIM_CCMR1_OC2CEN_Pos (15) 368 #define TIM_CCMR1_OC2CEN (0x01U << TIM_CCMR1_OC2CEN_Pos) ///< Output Compare 2 Clear Enable 369 370 #define TIM_CCMR1_IC1PSC_Pos (2) 371 #define TIM_CCMR1_IC1PSC (0x03U << TIM_CCMR1_IC1PSC_Pos) ///< IC1PSC[1:0] bits (Input Capture 1 Prescaler) 372 #define TIM_CCMR1_IC1PSC_DIV1 (0x00U << TIM_CCMR1_IC1PSC_Pos) ///< No Prescaler 373 #define TIM_CCMR1_IC1PSC_DIV2 (0x01U << TIM_CCMR1_IC1PSC_Pos) ///< Capture is done once every 2 events 374 #define TIM_CCMR1_IC1PSC_DIV4 (0x02U << TIM_CCMR1_IC1PSC_Pos) ///< Capture is done once every 4 events 375 #define TIM_CCMR1_IC1PSC_DIV8 (0x03U << TIM_CCMR1_IC1PSC_Pos) ///< Capture is done once every 8 events 376 #define TIM_CCMR1_IC1F_Pos (4) 377 #define TIM_CCMR1_IC1F (0x0FU << TIM_CCMR1_IC1F_Pos) ///< IC1F[3:0] bits (Input Capture 1 Filter) 378 #define TIM_CCMR1_IC1F_0 (0x01U << TIM_CCMR1_IC1F_Pos) ///< Bit 0 379 #define TIM_CCMR1_IC1F_1 (0x02U << TIM_CCMR1_IC1F_Pos) ///< Bit 1 380 #define TIM_CCMR1_IC1F_2 (0x04U << TIM_CCMR1_IC1F_Pos) ///< Bit 2 381 #define TIM_CCMR1_IC1F_3 (0x08U << TIM_CCMR1_IC1F_Pos) ///< Bit 3 382 383 #define TIM_CCMR1_IC2PSC_Pos (10) 384 #define TIM_CCMR1_IC2PSC (0x03U << TIM_CCMR1_IC2PSC_Pos) ///< IC2PSC[1:0] bits (Input Capture 2 Prescaler) 385 #define TIM_CCMR1_IC2PSC_DIV1 (0x00U << TIM_CCMR1_IC2PSC_Pos) ///< No Prescaler 386 #define TIM_CCMR1_IC2PSC_DIV2 (0x01U << TIM_CCMR1_IC2PSC_Pos) ///< Capture is done once every 2 events 387 #define TIM_CCMR1_IC2PSC_DIV4 (0x02U << TIM_CCMR1_IC2PSC_Pos) ///< Capture is done once every 4 events 388 #define TIM_CCMR1_IC2PSC_DIV8 (0x03U << TIM_CCMR1_IC2PSC_Pos) ///< Capture is done once every 8 events 389 #define TIM_CCMR1_IC2F_Pos (12) 390 #define TIM_CCMR1_IC2F (0x0FU << TIM_CCMR1_IC2F_Pos) ///< IC2F[3:0] bits (Input Capture 2 Filter) 391 #define TIM_CCMR1_IC2F_0 (0x01U << TIM_CCMR1_IC2F_Pos) ///< Bit 0 392 #define TIM_CCMR1_IC2F_1 (0x02U << TIM_CCMR1_IC2F_Pos) ///< Bit 1 393 #define TIM_CCMR1_IC2F_2 (0x04U << TIM_CCMR1_IC2F_Pos) ///< Bit 2 394 #define TIM_CCMR1_IC2F_3 (0x08U << TIM_CCMR1_IC2F_Pos) ///< Bit 3 395 396 //////////////////////////////////////////////////////////////////////////////// 397 /// @brief TIM_CCMR2 Register Bit Definition 398 //////////////////////////////////////////////////////////////////////////////// 399 #define TIM_CCMR2_CC3S_Pos (0) 400 #define TIM_CCMR2_CC3S (0x03U << TIM_CCMR2_CC3S_Pos) ///< CC3S[1:0] bits (Capture/Compare 3 Selection) 401 #define TIM_CCMR2_CC3S_OC (0x00U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as output 402 #define TIM_CCMR2_CC3S_DIRECTTI (0x01U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as input, IC3 is mapped on TI3 403 #define TIM_CCMR2_CC3S_INDIRECTTI (0x02U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as input, IC3 is mapped on TI4 404 #define TIM_CCMR2_CC3S_TRC (0x03U << TIM_CCMR2_CC3S_Pos) ///< Channel is configured as input, IC3 is mapped on TRC 405 #define TIM_CCMR2_OC3FEN_Pos (2) 406 #define TIM_CCMR2_OC3FEN (0x01U << TIM_CCMR2_OC3FEN_Pos) ///< Output Compare 3 Fast enable 407 #define TIM_CCMR2_IC3PSC_Pos (2) 408 #define TIM_CCMR2_IC3PSC (0x03U << TIM_CCMR2_IC3PSC_Pos) ///< IC3PSC[1:0] bits (Input Capture 3 Prescaler) 409 #define TIM_CCMR2_IC3PSC_DIV1 (0x00U << TIM_CCMR2_IC3PSC_Pos) ///< No Prescaler 410 #define TIM_CCMR2_IC3PSC_DIV2 (0x01U << TIM_CCMR2_IC3PSC_Pos) ///< Capture is done once every 2 events 411 #define TIM_CCMR2_IC3PSC_DIV4 (0x02U << TIM_CCMR2_IC3PSC_Pos) ///< Capture is done once every 4 events 412 #define TIM_CCMR2_IC3PSC_DIV8 (0x03U << TIM_CCMR2_IC3PSC_Pos) ///< Capture is done once every 8 events 413 #define TIM_CCMR2_OC3PEN_Pos (3) 414 #define TIM_CCMR2_OC3PEN (0x01U << TIM_CCMR2_OC3PEN_Pos) ///< Output Compare 3 Preload enable 415 #define TIM_CCMR2_OC3M_Pos (4) 416 #define TIM_CCMR2_OC3M (0x07U << TIM_CCMR2_OC3M_Pos) ///< OC3M[2:0] bits (Output Compare 3 Mode) 417 #define TIM_CCMR2_OC3M_TIMING (0x00U << TIM_CCMR2_OC3M_Pos) ///< Timing 418 #define TIM_CCMR2_OC3M_ACTIVE (0x01U << TIM_CCMR2_OC3M_Pos) ///< Active 419 #define TIM_CCMR2_OC3M_INACTIVE (0x02U << TIM_CCMR2_OC3M_Pos) ///< Inactive 420 #define TIM_CCMR2_OC3M_TOGGLE (0x03U << TIM_CCMR2_OC3M_Pos) ///< Toggle 421 #define TIM_CCMR2_OC3M_FORCEINACTIVE (0x04U << TIM_CCMR2_OC3M_Pos) ///< Forceinactive 422 #define TIM_CCMR2_OC3M_FORCEACTIVE (0x05U << TIM_CCMR2_OC3M_Pos) ///< Forceactive 423 #define TIM_CCMR2_OC3M_PWM1 (0x06U << TIM_CCMR2_OC3M_Pos) ///< PWM1 424 #define TIM_CCMR2_OC3M_PWM2 (0x07U << TIM_CCMR2_OC3M_Pos) ///< PWM2 425 #define TIM_CCMR2_IC3F_Pos (4) 426 #define TIM_CCMR2_IC3F (0x0FU << TIM_CCMR2_IC3F_Pos) ///< IC3F[3:0] bits (Input Capture 3 Filter) 427 #define TIM_CCMR2_IC3F_0 (0x01U << TIM_CCMR2_IC3F_Pos) ///< Bit 0 428 #define TIM_CCMR2_IC3F_1 (0x02U << TIM_CCMR2_IC3F_Pos) ///< Bit 1 429 #define TIM_CCMR2_IC3F_2 (0x04U << TIM_CCMR2_IC3F_Pos) ///< Bit 2 430 #define TIM_CCMR2_IC3F_3 (0x08U << TIM_CCMR2_IC3F_Pos) ///< Bit 3 431 #define TIM_CCMR2_OC3CEN_Pos (7) 432 #define TIM_CCMR2_OC3CEN (0x01U << TIM_CCMR2_OC3CEN_Pos) ///< Output Compare 3 Clear Enable 433 #define TIM_CCMR2_CC4S_Pos (8) 434 #define TIM_CCMR2_CC4S (0x03U << TIM_CCMR2_CC4S_Pos) ///< CC4S[1:0] bits (Capture/Compare 4 Selection) 435 #define TIM_CCMR2_CC4S_OC (0x00U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as output 436 #define TIM_CCMR2_CC4S_DIRECTTI (0x01U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as input, IC4 is mapped on TI4 437 #define TIM_CCMR2_CC4S_INDIRECTTI (0x02U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as input, IC4 is mapped on TI3 438 #define TIM_CCMR2_CC4S_TRC (0x03U << TIM_CCMR2_CC4S_Pos) ///< Channel is configured as input, IC4 is mapped on TRC 439 #define TIM_CCMR2_OC4FEN_Pos (10) 440 #define TIM_CCMR2_OC4FEN (0x01U << TIM_CCMR2_OC4FEN_Pos) ///< Output Compare 4 Fast enable 441 #define TIM_CCMR2_OC4PEN_Pos (11) 442 #define TIM_CCMR2_OC4PEN (0x01U << TIM_CCMR2_OC4PEN_Pos) ///< Output Compare 4 Preload enable 443 #define TIM_CCMR2_OC4M_Pos (12) 444 #define TIM_CCMR2_OC4M (0x07U << TIM_CCMR2_OC4M_Pos) ///< OC4M[2:0] bits (Output Compare 4 Mode) 445 #define TIM_CCMR2_OC4M_TIMING (0x00U << TIM_CCMR2_OC4M_Pos) ///< Timing 446 #define TIM_CCMR2_OC4M_ACTIVE (0x01U << TIM_CCMR2_OC4M_Pos) ///< Active 447 #define TIM_CCMR2_OC4M_INACTIVE (0x02U << TIM_CCMR2_OC4M_Pos) ///< Inactive 448 #define TIM_CCMR2_OC4M_TOGGLE (0x03U << TIM_CCMR2_OC4M_Pos) ///< Toggle 449 #define TIM_CCMR2_OC4M_FORCEINACTIVE (0x04U << TIM_CCMR2_OC4M_Pos) ///< Forceinactive 450 #define TIM_CCMR2_OC4M_FORCEACTIVE (0x05U << TIM_CCMR2_OC4M_Pos) ///< Forceactive 451 #define TIM_CCMR2_OC4M_PWM1 (0x06U << TIM_CCMR2_OC4M_Pos) ///< PWM1 452 #define TIM_CCMR2_OC4M_PWM2 (0x07U << TIM_CCMR2_OC4M_Pos) ///< PWM2 453 #define TIM_CCMR2_OC4CEN_Pos (15) 454 #define TIM_CCMR2_OC4CEN (0x01U << TIM_CCMR2_OC4CEN_Pos) ///< Output Compare 4 Clear Enable 455 #define TIM_CCMR2_IC4PSC_Pos (10) 456 #define TIM_CCMR2_IC4PSC (0x03U << TIM_CCMR2_IC4PSC_Pos) ///< IC4PSC[1:0] bits (Input Capture 4 Prescaler) 457 #define TIM_CCMR2_IC4PSC_DIV1 (0x00U << TIM_CCMR2_IC4PSC_Pos) ///< No Prescaler 458 #define TIM_CCMR2_IC4PSC_DIV2 (0x01U << TIM_CCMR2_IC4PSC_Pos) ///< Capture is done once every 2 events 459 #define TIM_CCMR2_IC4PSC_DIV4 (0x02U << TIM_CCMR2_IC4PSC_Pos) ///< Capture is done once every 4 events 460 #define TIM_CCMR2_IC4PSC_DIV8 (0x03U << TIM_CCMR2_IC4PSC_Pos) ///< Capture is done once every 8 events 461 #define TIM_CCMR2_IC4F_Pos (12) 462 #define TIM_CCMR2_IC4F (0x0FU << TIM_CCMR2_IC4F_Pos) ///< IC4F[3:0] bits (Input Capture 4 Filter) 463 #define TIM_CCMR2_IC4F_0 (0x01U << TIM_CCMR2_IC4F_Pos) ///< Bit 0 464 #define TIM_CCMR2_IC4F_1 (0x02U << TIM_CCMR2_IC4F_Pos) ///< Bit 1 465 #define TIM_CCMR2_IC4F_2 (0x04U << TIM_CCMR2_IC4F_Pos) ///< Bit 2 466 #define TIM_CCMR2_IC4F_3 (0x08U << TIM_CCMR2_IC4F_Pos) ///< Bit 3 467 468 //////////////////////////////////////////////////////////////////////////////// 469 /// @brief TIM_CCER Register Bit Definition 470 //////////////////////////////////////////////////////////////////////////////// 471 #define TIM_CCER_CC1EN_Pos (0) 472 #define TIM_CCER_CC1EN (0x01U << TIM_CCER_CC1EN_Pos) ///< Capture/Compare 1 output enable 473 #define TIM_CCER_CC1P_Pos (1) 474 #define TIM_CCER_CC1P (0x01U << TIM_CCER_CC1P_Pos) ///< Capture/Compare 1 output Polarity 475 #define TIM_CCER_CC1NEN_Pos (2) 476 #define TIM_CCER_CC1NEN (0x01U << TIM_CCER_CC1NEN_Pos) ///< Capture/Compare 1 Complementary output enable 477 #define TIM_CCER_CC1NP_Pos (3) 478 #define TIM_CCER_CC1NP (0x01U << TIM_CCER_CC1NP_Pos) ///< Capture/Compare 1 Complementary output Polarity 479 #define TIM_CCER_CC2EN_Pos (4) 480 #define TIM_CCER_CC2EN (0x01U << TIM_CCER_CC2EN_Pos) ///< Capture/Compare 2 output enable 481 #define TIM_CCER_CC2P_Pos (5) 482 #define TIM_CCER_CC2P (0x01U << TIM_CCER_CC2P_Pos) ///< Capture/Compare 2 output Polarity 483 #define TIM_CCER_CC2NEN_Pos (6) 484 #define TIM_CCER_CC2NEN (0x01U << TIM_CCER_CC2NEN_Pos) ///< Capture/Compare 2 Complementary output enable 485 #define TIM_CCER_CC2NP_Pos (7) 486 #define TIM_CCER_CC2NP (0x01U << TIM_CCER_CC2NP_Pos) ///< Capture/Compare 2 Complementary output Polarity 487 #define TIM_CCER_CC3EN_Pos (8) 488 #define TIM_CCER_CC3EN (0x01U << TIM_CCER_CC3EN_Pos) ///< Capture/Compare 3 output enable 489 #define TIM_CCER_CC3P_Pos (9) 490 #define TIM_CCER_CC3P (0x01U << TIM_CCER_CC3P_Pos) ///< Capture/Compare 3 output Polarity 491 #define TIM_CCER_CC3NEN_Pos (10) 492 #define TIM_CCER_CC3NEN (0x01U << TIM_CCER_CC3NEN_Pos) ///< Capture/Compare 3 Complementary output enable 493 #define TIM_CCER_CC3NP_Pos (11) 494 #define TIM_CCER_CC3NP (0x01U << TIM_CCER_CC3NP_Pos) ///< Capture/Compare 3 Complementary output Polarity 495 #define TIM_CCER_CC4EN_Pos (12) 496 #define TIM_CCER_CC4EN (0x01U << TIM_CCER_CC4EN_Pos) ///< Capture/Compare 4 output enable 497 #define TIM_CCER_CC4P_Pos (13) 498 #define TIM_CCER_CC4P (0x01U << TIM_CCER_CC4P_Pos) ///< Capture/Compare 4 output Polarity 499 #define TIM_CCER_CC4NP_Pos (15) 500 #define TIM_CCER_CC4NP (0x01U << TIM_CCER_CC4NP_Pos) ///< Capture/Compare 4 complementary output polarity 501 502 #define TIM_CCER_CC5EN_Pos (16) 503 #define TIM_CCER_CC5EN (0x01U << TIM_CCER_CC5EN_Pos) ///< Capture/Compare 5 output enable 504 #define TIM_CCER_CC5P_Pos (17) 505 #define TIM_CCER_CC5P (0x01U << TIM_CCER_CC5P_Pos) ///< Capture/Compare 5 output Polarity 506 507 //////////////////////////////////////////////////////////////////////////////// 508 /// @brief TIM_CNT Register Bit Definition 509 //////////////////////////////////////////////////////////////////////////////// 510 #define TIM_CNT_CNT (0xFFFFU) ///< Counter Value 511 512 513 //////////////////////////////////////////////////////////////////////////////// 514 /// @brief TIM_PSC Register Bit Definition 515 //////////////////////////////////////////////////////////////////////////////// 516 #define TIM_PSC_PSC (0xFFFFU) ///< Prescaler Value 517 518 //////////////////////////////////////////////////////////////////////////////// 519 /// @brief TIM_ARR Register Bit Definition 520 //////////////////////////////////////////////////////////////////////////////// 521 #define TIM_ARR_ARR (0xFFFFU) ///< actual auto-reload Value 522 523 524 //////////////////////////////////////////////////////////////////////////////// 525 /// @brief TIM_RCR Register Bit Definition 526 //////////////////////////////////////////////////////////////////////////////// 527 #define TIM_RCR_REP (0xFFU) ///< Repetition Counter Value 528 529 #define TIM_RCR_REP_CNT_Pos (8) 530 #define TIM_RCR_REP_CNT (0xFFU << TIM_RCR_REP_CNT_Pos) ///< Repetition counter value of real-time writing 531 532 //////////////////////////////////////////////////////////////////////////////// 533 /// @brief TIM_CCR1 Register Bit Definition 534 //////////////////////////////////////////////////////////////////////////////// 535 #define TIM_CCR1_CCR1 (0xFFFFU) ///< Capture/Compare 1 Value 536 537 538 //////////////////////////////////////////////////////////////////////////////// 539 /// @brief TIM_CCR2 Register Bit Definition 540 //////////////////////////////////////////////////////////////////////////////// 541 #define TIM_CCR2_CCR2 (0xFFFFU) ///< Capture/Compare 2 Value 542 543 544 //////////////////////////////////////////////////////////////////////////////// 545 /// @brief TIM_CCR3 Register Bit Definition 546 //////////////////////////////////////////////////////////////////////////////// 547 #define TIM_CCR3_CCR3 (0xFFFFU) ///< Capture/Compare 3 Value 548 549 550 //////////////////////////////////////////////////////////////////////////////// 551 /// @brief TIM_CCR4 Register Bit Definition 552 //////////////////////////////////////////////////////////////////////////////// 553 #define TIM_CCR4_CCR4 (0xFFFFU) ///< Capture/Compare 4 Value 554 555 556 //////////////////////////////////////////////////////////////////////////////// 557 /// @brief TIM_BDTR Register Bit Definition 558 //////////////////////////////////////////////////////////////////////////////// 559 #define TIM_BDTR_DTG_Pos (0) 560 #define TIM_BDTR_DTG (0xFFU << TIM_BDTR_DTG_Pos) ///< DTG[0:7] bits (Dead-Time Generator set-up) 561 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) ///< Bit 0 562 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) ///< Bit 1 563 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) ///< Bit 2 564 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) ///< Bit 3 565 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) ///< Bit 4 566 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) ///< Bit 5 567 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) ///< Bit 6 568 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) ///< Bit 7 569 #define TIM_BDTR_LOCK_Pos (8) 570 #define TIM_BDTR_LOCK (0x03U << TIM_BDTR_LOCK_Pos) ///< LOCK[1:0] bits (Lock Configuration) 571 #define TIM_BDTR_LOCK_OFF (0x00U << TIM_BDTR_LOCK_Pos) ///< Lock Off 572 #define TIM_BDTR_LOCK_1 (0x01U << TIM_BDTR_LOCK_Pos) ///< Lock Level 1 573 #define TIM_BDTR_LOCK_2 (0x02U << TIM_BDTR_LOCK_Pos) ///< Lock Level 2 574 #define TIM_BDTR_LOCK_3 (0x03U << TIM_BDTR_LOCK_Pos) ///< Lock Level 3 575 #define TIM_BDTR_OSSI_Pos (10) 576 #define TIM_BDTR_OSSI (0x01U << TIM_BDTR_OSSI_Pos) ///< Off-State Selection for Idle mode 577 #define TIM_BDTR_OSSR_Pos (11) 578 #define TIM_BDTR_OSSR (0x01U << TIM_BDTR_OSSR_Pos) ///< Off-State Selection for Run mode 579 #define TIM_BDTR_BKEN_Pos (12) 580 #define TIM_BDTR_BKEN (0x01U << TIM_BDTR_BKEN_Pos) ///< Break enable 581 #define TIM_BDTR_BKP_Pos (13) 582 #define TIM_BDTR_BKP (0x01U << TIM_BDTR_BKP_Pos) ///< Break Polarity 583 #define TIM_BDTR_AOEN_Pos (14) 584 #define TIM_BDTR_AOEN (0x01U << TIM_BDTR_AOEN_Pos) ///< Automatic Output enable 585 #define TIM_BDTR_MOEN_Pos (15) 586 #define TIM_BDTR_MOEN (0x01U << TIM_BDTR_MOEN_Pos) ///< Main Output enable 587 588 #define TIM_BDTR_DOEN_Pos (16) 589 #define TIM_BDTR_DOEN (0x01U << TIM_BDTR_DOEN_Pos) ///< Direct Output enable 590 //////////////////////////////////////////////////////////////////////////////// 591 /// @brief TIM_DCR Register Bit Definition 592 //////////////////////////////////////////////////////////////////////////////// 593 #define TIM_DCR_DBA_Pos (0) 594 #define TIM_DCR_DBA (0x1FU << TIM_DCR_DBA_Pos) ///< DBA[4:0] bits (DMA Base Address) 595 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) ///< Bit 0 596 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) ///< Bit 1 597 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) ///< Bit 2 598 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) ///< Bit 3 599 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) ///< Bit 4 600 #define TIM_DCR_DBL_Pos (8) 601 #define TIM_DCR_DBL (0x1FU << TIM_DCR_DBL_Pos) ///< DBL[4:0] bits (DMA Burst Length) 602 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) ///< Bit 0 603 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) ///< Bit 1 604 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) ///< Bit 2 605 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) ///< Bit 3 606 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) ///< Bit 4 607 608 //////////////////////////////////////////////////////////////////////////////// 609 /// @brief TIM_DMAR Register Bit Definition 610 //////////////////////////////////////////////////////////////////////////////// 611 #define TIM_DMAR_DMAB (0xFFFFU) ///< DMA register for burst accesses 612 613 //////////////////////////////////////////////////////////////////////////////// 614 /// @brief TIM_CCMR3 Register Bit Definition 615 //////////////////////////////////////////////////////////////////////////////// 616 #define TIM_CCMR3_OC5FEN_Pos (2) 617 #define TIM_CCMR3_OC5FEN (0x01U << TIM_CCMR3_OC5FEN_Pos) ///< Output Compare 5 Fast enable 618 #define TIM_CCMR3_OC5PEN_Pos (3) 619 #define TIM_CCMR3_OC5PEN (0x01U << TIM_CCMR3_OC5PEN_Pos) ///< Output Compare 5 Preload enable 620 #define TIM_CCMR3_OC5M_Pos (4) 621 #define TIM_CCMR3_OC5M (0x07U << TIM_CCMR3_OC5M_Pos) ///< OC5M[2:0] bits (Output Compare 5 Mode) 622 623 #define TIM_CCMR3_OC5CEN_Pos (7) 624 #define TIM_CCMR3_OC5CEN (0x01U << TIM_CCMR3_OC5CEN_Pos) ///< Output Compare 5 Clear Enable 625 //////////////////////////////////////////////////////////////////////////////// 626 /// @brief TIM_CCR5 Register Bit Definition 627 //////////////////////////////////////////////////////////////////////////////// 628 #define TIM_CCR5_CCR5 (0xFFFF) ///< Capture/Compare 5 Value 629 630 //////////////////////////////////////////////////////////////////////////////// 631 /// @brief TIM_PDER Register Bit Definition 632 //////////////////////////////////////////////////////////////////////////////// 633 #define TIM_PDER_CCDREPE_Pos (0) 634 #define TIM_PDER_CCDREPE (0x01U << TIM_PDER_CCDREPE_Pos) ///< DMA request flow enable 635 #define TIM_PDER_CCR1SHIFTEN_Pos (1) 636 #define TIM_PDER_CCR1SHIFTEN (0x01U << TIM_PDER_CCR1SHIFTEN_Pos) ///< CCR1 pwm shift enable 637 #define TIM_PDER_CCR2SHIFTEN_Pos (2) 638 #define TIM_PDER_CCR2SHIFTEN (0x01U << TIM_PDER_CCR2SHIFTEN_Pos) ///< CCR2 pwm shift enable 639 #define TIM_PDER_CCR3SHIFTEN_Pos (3) 640 #define TIM_PDER_CCR3SHIFTEN (0x01U << TIM_PDER_CCR3SHIFTEN_Pos) ///< CCR3 pwm shift enable 641 #define TIM_PDER_CCR4SHIFTEN_Pos (4) 642 #define TIM_PDER_CCR4SHIFTEN (0x01U << TIM_PDER_CCR4SHIFTEN_Pos) ///< CCR4 pwm shift enable 643 #define TIM_PDER_CCR5SHIFTEN_Pos (5) 644 #define TIM_PDER_CCR5SHIFTEN (0x01U << TIM_PDER_CCR5SHIFTEN_Pos) ///< CCR5 pwm shift enable 645 646 //////////////////////////////////////////////////////////////////////////////// 647 /// @brief TIM_CCR1FALL Register Bit Definition 648 //////////////////////////////////////////////////////////////////////////////// 649 #define TIM_CCR1FALL_CCR1FALL (0xFFFFU) ///< Capture/compare value for ch1 when counting down in PWM center-aligned mode 650 651 //////////////////////////////////////////////////////////////////////////////// 652 /// @brief TIM_CCR2FALL Register Bit Definition 653 //////////////////////////////////////////////////////////////////////////////// 654 #define TIM_CCR2FALL_CCR2FALL (0xFFFFU) ///< Capture/compare value for ch2 when counting down in PWM center-aligned mode 655 656 //////////////////////////////////////////////////////////////////////////////// 657 /// @brief TIM_CCR3FALL Register Bit Definition 658 //////////////////////////////////////////////////////////////////////////////// 659 #define TIM_CCR3FALL_CCR3FALL (0xFFFFU) ///< Capture/compare value for ch3 when counting down in PWM center-aligned mode 660 661 //////////////////////////////////////////////////////////////////////////////// 662 /// @brief TIM_CCR4FALL Register Bit Definition 663 //////////////////////////////////////////////////////////////////////////////// 664 #define TIM_CCR4FALL_CCR4FALL (0xFFFFU) ///< Capture/compare value for ch4 when counting down in PWM center-aligned mode 665 666 //////////////////////////////////////////////////////////////////////////////// 667 /// @brief TIM_CCR5FALL Register Bit Definition 668 //////////////////////////////////////////////////////////////////////////////// 669 #define TIM_CCR5FALL_CCR5FALL (0xFFFFU) ///< Capture/compare value for ch5 when counting down in PWM center-aligned mode 670 671 672 673 /// @} 674 675 /// @} 676 677 /// @} 678 679 //////////////////////////////////////////////////////////////////////////////// 680 #endif 681 //////////////////////////////////////////////////////////////////////////////// 682