1 ////////////////////////////////////////////////////////////////////////////////
2 /// @file hal_tim.c
3 /// @author AE TEAM
4 /// @brief THIS FILE PROVIDES ALL THE TIM FIRMWARE FUNCTIONS.
5 ////////////////////////////////////////////////////////////////////////////////
6 /// @attention
7 ///
8 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
9 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
10 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
11 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
12 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
13 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
14 ///
15 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
16 ////////////////////////////////////////////////////////////////////////////////
17
18 // Define to prevent recursive inclusion
19 #define _HAL_TIM_C_
20
21 // Files includes
22 #include "hal_rcc.h"
23 #include "hal_tim.h"
24
25 ////////////////////////////////////////////////////////////////////////////////
26 /// @addtogroup MM32_Hardware_Abstract_Layer
27 /// @{
28
29 ////////////////////////////////////////////////////////////////////////////////
30 /// @addtogroup TIM_HAL
31 /// @{
32
33 ////////////////////////////////////////////////////////////////////////////////
34 /// @addtogroup TIM_Exported_Functions
35 /// @{
36
37 ////////////////////////////////////////////////////////////////////////////////
38 /// @brief Deinitializes the tim peripheral registers to their default reset values.
39 /// @param tim: select the TIM peripheral.
40 /// @retval None.
41 ////////////////////////////////////////////////////////////////////////////////
TIM_DeInit(TIM_TypeDef * tim)42 void TIM_DeInit(TIM_TypeDef* tim)
43 {
44 switch (*(vu32*)&tim) {
45 case (u32)TIM1:
46 exRCC_APB2PeriphReset(RCC_APB2ENR_TIM1);
47 break;
48 case (u32)TIM2:
49 exRCC_APB1PeriphReset(RCC_APB1ENR_TIM2);
50 break;
51 case (u32)TIM3:
52 exRCC_APB1PeriphReset(RCC_APB1ENR_TIM3);
53 break;
54 case (u32)TIM4:
55 exRCC_APB1PeriphReset(RCC_APB1ENR_TIM4);
56 break;
57
58 case (u32)TIM5:
59 exRCC_APB1PeriphReset(RCC_APB1ENR_TIM5);
60 break;
61 case (u32)TIM6:
62 exRCC_APB1PeriphReset(RCC_APB1ENR_TIM6);
63 break;
64 case (u32)TIM7:
65 exRCC_APB1PeriphReset(RCC_APB1ENR_TIM7);
66 break;
67
68 case (u32)TIM8:
69 exRCC_APB2PeriphReset(RCC_APB2ENR_TIM8);
70 break;
71
72 default:
73 break;
74 }
75 }
76
77 ////////////////////////////////////////////////////////////////////////////////
78 /// @brief Initializes the tim Time Base Unit peripheral according to
79 /// the specified parameters in the init_struct.
80 /// @param tim: select the TIM peripheral.
81 /// @param init_struct: pointer to a TIM_TimeBaseInitTypeDef
82 /// structure that contains the configuration information for the
83 /// specified TIM peripheral.
84 /// @retval None.
85 ////////////////////////////////////////////////////////////////////////////////
TIM_TimeBaseInit(TIM_TypeDef * tim,TIM_TimeBaseInitTypeDef * init_struct)86 void TIM_TimeBaseInit(TIM_TypeDef* tim, TIM_TimeBaseInitTypeDef* init_struct)
87 {
88 MODIFY_REG(tim->CR1, TIM_CR1_CKD, init_struct->TIM_ClockDivision);
89
90 if ((tim == TIM1) || (tim == TIM2) || (tim == TIM3) || (tim == TIM4) || (tim == TIM5) || (tim == TIM8))
91 MODIFY_REG(tim->CR1, TIM_CR1_CMS | TIM_CR1_DIR, init_struct->TIM_CounterMode);
92
93 if ((tim == TIM1) || (tim == TIM8) )
94
95 MODIFY_REG(tim->RCR, TIM_RCR_REP, init_struct->TIM_RepetitionCounter);
96
97 WRITE_REG(tim->ARR, init_struct->TIM_Period);
98 WRITE_REG(tim->PSC, init_struct->TIM_Prescaler);
99 WRITE_REG(tim->EGR, TIM_PSCReloadMode_Immediate);
100 }
101
102 ////////////////////////////////////////////////////////////////////////////////
103 /// @brief Initializes the tim Channel1 according to the specified
104 /// parameters in the init_struct.
105 /// @param tim: select the TIM peripheral.
106 /// @param init_struct: pointer to a TIM_OCInitTypeDef structure that
107 /// contains the configuration information for the specified TIM peripheral.
108 /// @retval None.
109 ////////////////////////////////////////////////////////////////////////////////
TIM_OC1Init(TIM_TypeDef * tim,TIM_OCInitTypeDef * init_struct)110 void TIM_OC1Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
111 {
112 MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, init_struct->TIM_OCMode);
113 MODIFY_REG(tim->CCER, TIM_CCER_CC1P | TIM_CCER_CC1EN, \
114 ((u32)init_struct->TIM_OCPolarity) | ((u32)init_struct->TIM_OutputState));
115 WRITE_REG(tim->CCR1, init_struct->TIM_Pulse);
116
117 if ((tim == TIM1) || (tim == TIM8)) {
118 MODIFY_REG(tim->CCER, TIM_CCER_CC1NP | TIM_CCER_CC1NEN, \
119 ((u32)init_struct->TIM_OCNPolarity) | ((u32)init_struct->TIM_OutputNState));
120 MODIFY_REG(tim->CR2, TIM_CR2_OIS1 | TIM_CR2_OIS1N, \
121 ((u32)init_struct->TIM_OCIdleState) | ((u32)init_struct->TIM_OCNIdleState));
122 }
123 }
124
125 ////////////////////////////////////////////////////////////////////////////////
126 /// @brief Initializes the tim Channel2 according to the specified
127 /// parameters in the init_struct.
128 /// @param tim: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
129 /// @param init_struct: pointer to a TIM_OCInitTypeDef structure that
130 /// contains the configuration information for the specified TIM peripheral.
131 /// @retval None.
132 ////////////////////////////////////////////////////////////////////////////////
TIM_OC2Init(TIM_TypeDef * tim,TIM_OCInitTypeDef * init_struct)133 void TIM_OC2Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
134 {
135 MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, init_struct->TIM_OCMode << 8);
136 MODIFY_REG(tim->CCER, TIM_CCER_CC2EN | TIM_CCER_CC2P, \
137 (init_struct->TIM_OCPolarity << 4) | (init_struct->TIM_OutputState << 4));
138 WRITE_REG(tim->CCR2, init_struct->TIM_Pulse);
139
140 if ((tim == TIM1) || (tim == TIM8)) {
141 MODIFY_REG(tim->CCER, TIM_CCER_CC2NP | TIM_CCER_CC2NEN, \
142 (init_struct->TIM_OCNPolarity << 4) | (init_struct->TIM_OutputNState << 4));
143 MODIFY_REG(tim->CR2, TIM_CR2_OIS2 | TIM_CR2_OIS2N, \
144 (init_struct->TIM_OCIdleState << 2) | (init_struct->TIM_OCNIdleState << 2));
145 }
146 }
147
148 ////////////////////////////////////////////////////////////////////////////////
149 /// @brief Initializes the tim Channel3 according to the specified
150 /// parameters in the init_struct.
151 /// @param tim: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
152 /// @param init_struct: pointer to a TIM_OCInitTypeDef structure that
153 /// contains the configuration information for the specified TIM peripheral.
154 /// @retval None.
155 ////////////////////////////////////////////////////////////////////////////////
TIM_OC3Init(TIM_TypeDef * tim,TIM_OCInitTypeDef * init_struct)156 void TIM_OC3Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
157 {
158 MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, init_struct->TIM_OCMode);
159 MODIFY_REG(tim->CCER, TIM_CCER_CC3EN | TIM_CCER_CC3P, \
160 (init_struct->TIM_OCPolarity << 8) | (init_struct->TIM_OutputState << 8));
161 WRITE_REG(tim->CCR3, init_struct->TIM_Pulse);
162
163 if ((tim == TIM1) || (tim == TIM8)) {
164 MODIFY_REG(tim->CCER, TIM_CCER_CC3NP | TIM_CCER_CC3NEN, \
165 (init_struct->TIM_OCNPolarity << 8) | (init_struct->TIM_OutputNState << 8));
166 MODIFY_REG(tim->CR2, TIM_CR2_OIS3 | TIM_CR2_OIS3N, \
167 (init_struct->TIM_OCIdleState << 4) | (init_struct->TIM_OCNIdleState << 4));
168 }
169 }
170
171 ////////////////////////////////////////////////////////////////////////////////
172 /// @brief Initializes the tim Channel4 according to the specified
173 /// parameters in the init_struct.
174 /// @param tim:select the TIM peripheral.
175 /// @param init_struct: pointer to a TIM_OCInitTypeDef structure that
176 /// contains the configuration information for the specified TIM peripheral.
177 /// @retval None.
178 ////////////////////////////////////////////////////////////////////////////////
TIM_OC4Init(TIM_TypeDef * tim,TIM_OCInitTypeDef * init_struct)179 void TIM_OC4Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
180 {
181 MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, (init_struct->TIM_OCMode) << 8);
182 MODIFY_REG(tim->CCER, TIM_CCER_CC4EN | TIM_CCER_CC4P, \
183 (init_struct->TIM_OCPolarity << 12) | (init_struct->TIM_OutputState << 12));
184 WRITE_REG(tim->CCR4, init_struct->TIM_Pulse);
185
186 if ((tim == TIM1) || (tim == TIM8))
187 MODIFY_REG(tim->CR2, TIM_CR2_OIS4, init_struct->TIM_OCIdleState << 6);
188 }
189
190 ////////////////////////////////////////////////////////////////////////////////
191 /// @brief Initializes the TIM peripheral according to the specified
192 /// parameters in the init_struct.
193 /// @param tim: select the TIM peripheral.
194 /// @param init_struct: pointer to a TIM_ICInitTypeDef structure that
195 /// contains the configuration information for the specified TIM peripheral.
196 /// @retval None.
197 ////////////////////////////////////////////////////////////////////////////////
TIM_ICInit(TIM_TypeDef * tim,TIM_ICInitTypeDef * init_struct)198 void TIM_ICInit(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct)
199 {
200 switch (init_struct->TIM_Channel) {
201 case TIM_Channel_1:
202 TI1_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
203 TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler);
204 break;
205 case TIM_Channel_2:
206 TI2_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
207 TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler);
208 break;
209 case TIM_Channel_3:
210 TI3_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
211 TIM_SetIC3Prescaler(tim, init_struct->TIM_ICPrescaler);
212 break;
213 case TIM_Channel_4:
214 TI4_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
215 TIM_SetIC4Prescaler(tim, init_struct->TIM_ICPrescaler);
216 break;
217 default:
218 break;
219 }
220 }
221
222 ////////////////////////////////////////////////////////////////////////////////
223 /// @brief Configures the TIM peripheral according to the specified
224 /// parameters in the init_struct to measure an external PWM signal.
225 /// @param tim: select the TIM peripheral.
226 /// @param init_struct: pointer to a TIM_ICInitTypeDef structure that
227 /// contains the configuration information for the specified TIM peripheral.
228 /// @retval None.
229 ////////////////////////////////////////////////////////////////////////////////
TIM_PWMIConfig(TIM_TypeDef * tim,TIM_ICInitTypeDef * init_struct)230 void TIM_PWMIConfig(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct)
231 {
232 u16 icoppositepolarity = TIM_ICPolarity_Rising;
233 u16 icoppositeselection = TIM_ICSelection_DirectTI;
234 icoppositepolarity = (init_struct->TIM_ICPolarity == TIM_ICPolarity_Rising) ? TIM_ICPolarity_Falling : TIM_ICPolarity_Rising;
235 icoppositeselection =
236 (init_struct->TIM_ICSelection == TIM_ICSelection_DirectTI) ? TIM_ICSelection_IndirectTI : TIM_ICSelection_DirectTI;
237 if (init_struct->TIM_Channel == TIM_Channel_1) {
238 TI1_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
239 TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler);
240 TI2_Configure(tim, icoppositepolarity, icoppositeselection, init_struct->TIM_ICFilter);
241 TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler);
242 }
243 else {
244 TI2_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
245 TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler);
246 TI1_Configure(tim, icoppositepolarity, icoppositeselection, init_struct->TIM_ICFilter);
247 TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler);
248 }
249 }
250
251 ////////////////////////////////////////////////////////////////////////////////
252 /// @brief Configures the: Break feature, dead time, Lock level, the OSSI,
253 /// the OSSR State and the AOE(automatic output enable).
254 /// @param tim: select the TIM
255 /// @param init_struct: pointer to a TIM_BDTRInitTypeDef structure that
256 /// contains the BDTR Register configuration information for the TIM peripheral.
257 /// @retval None.
258 ////////////////////////////////////////////////////////////////////////////////
TIM_BDTRConfig(TIM_TypeDef * tim,TIM_BDTRInitTypeDef * init_struct)259 void TIM_BDTRConfig(TIM_TypeDef* tim, TIM_BDTRInitTypeDef* init_struct)
260 {
261 tim->BDTR = (u32)init_struct->TIM_OSSRState | init_struct->TIM_OSSIState | init_struct->TIM_LOCKLevel |
262 init_struct->TIM_DeadTime | init_struct->TIM_Break | init_struct->TIM_BreakPolarity |
263 init_struct->TIM_AutomaticOutput;
264 }
265
266 ////////////////////////////////////////////////////////////////////////////////
267 /// @brief Fills each init_struct member with its default value.
268 /// @param init_struct : pointer to a TIM_TimeBaseInitTypeDef
269 /// structure which will be initialized.
270 /// @retval None.
271 ////////////////////////////////////////////////////////////////////////////////
TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef * init_struct)272 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* init_struct)
273 {
274 init_struct->TIM_Period = 0xFFFFFFFF;
275 init_struct->TIM_Prescaler = 0x0000;
276 init_struct->TIM_ClockDivision = TIM_CKD_DIV1;
277 init_struct->TIM_CounterMode = TIM_CounterMode_Up;
278 init_struct->TIM_RepetitionCounter = 0x00;
279 }
280
281 ////////////////////////////////////////////////////////////////////////////////
282 /// @brief Fills each init_struct member with its default value.
283 /// @param init_struct : pointer to a TIM_OCInitTypeDef structure which will
284 /// be initialized.
285 /// @retval None.
286 ////////////////////////////////////////////////////////////////////////////////
TIM_OCStructInit(TIM_OCInitTypeDef * init_struct)287 void TIM_OCStructInit(TIM_OCInitTypeDef* init_struct)
288 {
289 init_struct->TIM_OCMode = TIM_OCMode_Timing;
290 init_struct->TIM_OutputState = TIM_OutputState_Disable;
291 init_struct->TIM_OutputNState = TIM_OutputNState_Disable;
292 init_struct->TIM_Pulse = 0x00000000;
293 init_struct->TIM_OCPolarity = TIM_OCPolarity_High;
294 init_struct->TIM_OCNPolarity = TIM_OCNPolarity_High;
295 init_struct->TIM_OCIdleState = TIM_OCIdleState_Reset;
296 init_struct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
297 }
298
299 ////////////////////////////////////////////////////////////////////////////////
300 /// @brief Fills each init_struct member with its default value.
301 /// @param init_struct: pointer to a TIM_ICInitTypeDef structure which will
302 /// be initialized.
303 /// @retval None.
304 ////////////////////////////////////////////////////////////////////////////////
TIM_ICStructInit(TIM_ICInitTypeDef * init_struct)305 void TIM_ICStructInit(TIM_ICInitTypeDef* init_struct)
306 {
307 init_struct->TIM_Channel = TIM_Channel_1;
308 init_struct->TIM_ICPolarity = TIM_ICPolarity_Rising;
309 init_struct->TIM_ICSelection = TIM_ICSelection_DirectTI;
310 init_struct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
311 init_struct->TIM_ICFilter = 0x00;
312 }
313
314 ////////////////////////////////////////////////////////////////////////////////
315 /// @brief Fills each init_struct member with its default value.
316 /// @param init_struct: pointer to a TIM_BDTRInitTypeDef structure which
317 /// will be initialized.
318 /// @retval None.
319 ////////////////////////////////////////////////////////////////////////////////
TIM_BDTRStructInit(TIM_BDTRInitTypeDef * init_struct)320 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* init_struct)
321 {
322 init_struct->TIM_OSSRState = TIM_OSSRState_Disable;
323 init_struct->TIM_OSSIState = TIM_OSSIState_Disable;
324 init_struct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
325 init_struct->TIM_DeadTime = 0x00;
326 init_struct->TIM_Break = TIM_Break_Disable;
327 init_struct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
328 init_struct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
329 }
330
331 ////////////////////////////////////////////////////////////////////////////////
332 /// @brief Enables or disables the specified TIM peripheral.
333 /// @param tim: where x can be 1 to 17 to select the tim peripheral.
334 /// @param state: new state of the tim peripheral.
335 /// This parameter can be: ENABLE or DISABLE.
336 /// @retval None.
337 ////////////////////////////////////////////////////////////////////////////////
TIM_Cmd(TIM_TypeDef * tim,FunctionalState state)338 void TIM_Cmd(TIM_TypeDef* tim, FunctionalState state)
339 {
340 (state) ? SET_BIT(tim->CR1, TIM_CR1_CEN) : CLEAR_BIT(tim->CR1, TIM_CR1_CEN);
341 }
342
343 ////////////////////////////////////////////////////////////////////////////////
344 /// @brief Enables or disables the TIM peripheral Main Outputs.
345 /// @param tim: where x can be 1, 8, 16 or 17 to select the tim peripheral.
346 /// @param state: new state of the TIM peripheral Main Outputs.
347 /// This parameter can be: ENABLE or DISABLE.
348 /// @retval None.
349 ////////////////////////////////////////////////////////////////////////////////
TIM_CtrlPWMOutputs(TIM_TypeDef * tim,FunctionalState state)350 void TIM_CtrlPWMOutputs(TIM_TypeDef* tim, FunctionalState state)
351 {
352 (state) ? SET_BIT(tim->BDTR, TIM_BDTR_MOEN) : CLEAR_BIT(tim->BDTR, TIM_BDTR_MOEN);
353 }
354
355 ////////////////////////////////////////////////////////////////////////////////
356 /// @brief Enables or disables the specified TIM interrupts.
357 /// @param tim: select the tim peripheral.
358 /// @param it: specifies the TIM interrupts sources to be enabled or disabled.
359 /// This parameter can be any combination of the following values:
360 /// @arg TIM_IT_Update: TIM update Interrupt source
361 /// @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
362 /// @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
363 /// @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
364 /// @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
365 /// @arg TIM_IT_COM: TIM Commutation Interrupt source
366 /// @arg TIM_IT_Trigger: TIM Trigger Interrupt source
367 /// @arg TIM_IT_Break: TIM Break Interrupt source
368 /// @note
369 /// - Partial timer can have TIM_IT_Update or TIM_IT_CC1.
370 /// - TIM_IT_Break is used only with partial timer.
371 /// - TIM_IT_COM is used only with partial timer.
372 /// @param state: new state of the TIM interrupts.
373 /// This parameter can be: ENABLE or DISABLE.
374 /// @retval None.
375 ////////////////////////////////////////////////////////////////////////////////
TIM_ITConfig(TIM_TypeDef * tim,u32 it,FunctionalState state)376 void TIM_ITConfig(TIM_TypeDef* tim, u32 it, FunctionalState state) //TIMIT_TypeDef
377 {
378 (state) ? SET_BIT(tim->DIER, it) : CLEAR_BIT(tim->DIER, it);
379 }
380
381 ////////////////////////////////////////////////////////////////////////////////
382 /// @brief Configures the tim event to be generate by software.
383 /// @param tim: select the TIM peripheral.
384 /// @param source: specifies the event source.
385 /// This parameter can be one or more of the following values:
386 /// @arg TIM_EventSource_Update: Timer update Event source
387 /// @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
388 /// @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
389 /// @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
390 /// @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
391 /// @arg TIM_EventSource_COM: Timer COM event source
392 /// @arg TIM_EventSource_Trigger: Timer Trigger Event source
393 /// @arg TIM_EventSource_Break: Timer Break event source
394 /// @note
395 /// - TIM_EventSource_COM and TIM_EventSource_Break are used only with partial timer.
396 /// @retval None.
397 ////////////////////////////////////////////////////////////////////////////////
TIM_GenerateEvent(TIM_TypeDef * tim,TIMEGR_Typedef source)398 void TIM_GenerateEvent(TIM_TypeDef* tim, TIMEGR_Typedef source)
399 {
400 WRITE_REG(tim->EGR, source);
401 }
402 ////////////////////////////////////////////////////////////////////////////////
403 /// @brief Configures the tim's DMA interface.
404 /// @param tim: select the TIM peripheral.
405 /// @param dma_base: DMA Base address.
406 /// This parameter can be one of the following values:
407 /// @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
408 /// TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
409 /// TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
410 /// TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
411 /// TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
412 /// TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
413 /// TIM_DMABase_DCR.
414 /// @param length: DMA Burst length.
415 /// This parameter can be one value between:
416 /// TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
417 /// @retval None.
418 ////////////////////////////////////////////////////////////////////////////////
TIM_DMAConfig(TIM_TypeDef * tim,TIMDMABASE_Typedef dma_base,TIMDMABURSTLENGTH_Typedef length)419 void TIM_DMAConfig(TIM_TypeDef* tim, TIMDMABASE_Typedef dma_base, TIMDMABURSTLENGTH_Typedef length)
420 {
421 WRITE_REG(tim->DCR, ((u32)dma_base) | ((u32)length));
422 }
423 ////////////////////////////////////////////////////////////////////////////////
424 /// @brief Enables or disables the tim's DMA Requests.
425 /// @param tim: select the TIM peripheral.
426 /// @param source: specifies the DMA Request sources.
427 /// This parameter can be any combination of the following values:
428 /// @arg TIM_DMA_Update: TIM update Interrupt source
429 /// @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
430 /// @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
431 /// @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
432 /// @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
433 /// @arg TIM_DMA_COM: TIM Commutation DMA source
434 /// @arg TIM_DMA_Trigger: TIM Trigger DMA source
435 /// @param state: new state of the DMA Request sources.
436 /// This parameter can be: ENABLE or DISABLE.
437 /// @retval None.
438 ////////////////////////////////////////////////////////////////////////////////
TIM_DMACmd(TIM_TypeDef * tim,TIMDMASRC_Typedef source,FunctionalState state)439 void TIM_DMACmd(TIM_TypeDef* tim, TIMDMASRC_Typedef source, FunctionalState state)
440 {
441 (state) ? SET_BIT(tim->DIER, source) : CLEAR_BIT(tim->DIER, source);
442 }
443 ////////////////////////////////////////////////////////////////////////////////
444 /// @brief Configures the tim internal Clock
445 /// @param tim: select the TIM peripheral.
446 /// @retval None.
447 ////////////////////////////////////////////////////////////////////////////////
TIM_InternalClockConfig(TIM_TypeDef * tim)448 void TIM_InternalClockConfig(TIM_TypeDef* tim)
449 {
450 CLEAR_BIT(tim->SMCR, TIM_SMCR_SMS);
451 }
452
453 ////////////////////////////////////////////////////////////////////////////////
454 /// @brief Configures the tim Internal Trigger as External Clock
455 /// @param tim: select the TIM peripheral.
456 /// @param source: Trigger source.
457 /// This parameter can be one of the following values:
458 /// @arg TIM_TS_ITR0: Internal Trigger 0
459 /// @arg TIM_TS_ITR1: Internal Trigger 1
460 /// @arg TIM_TS_ITR2: Internal Trigger 2
461 /// @arg TIM_TS_ITR3: Internal Trigger 3
462 /// @retval None.
463 ////////////////////////////////////////////////////////////////////////////////
TIM_ITRxExternalClockConfig(TIM_TypeDef * tim,TIMTS_TypeDef source)464 void TIM_ITRxExternalClockConfig(TIM_TypeDef* tim, TIMTS_TypeDef source)
465 {
466 TIM_SelectInputTrigger(tim, source);
467 SET_BIT(tim->SMCR, TIM_SlaveMode_External1);
468 }
469
470 ////////////////////////////////////////////////////////////////////////////////
471 /// @brief Configures the tim Trigger as External Clock
472 /// @param tim: select the TIM peripheral.
473 /// @param source: Trigger source.
474 /// This parameter can be one of the following values:
475 /// @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
476 /// @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
477 /// @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
478 /// @param polarity: specifies the TIx Polarity.
479 /// This parameter can be one of the following values:
480 /// @arg TIM_ICPolarity_Rising
481 /// @arg TIM_ICPolarity_Falling
482 /// @param filter : specifies the filter value.
483 /// This parameter must be a value between 0x0 and 0xF.
484 /// @retval None.
485 ////////////////////////////////////////////////////////////////////////////////
TIM_TIxExternalClockConfig(TIM_TypeDef * tim,TIM_TIEXTCLKSRC_Typedef source,TIMICP_Typedef polarity,u16 filter)486 void TIM_TIxExternalClockConfig(TIM_TypeDef* tim, TIM_TIEXTCLKSRC_Typedef source, TIMICP_Typedef polarity, u16 filter)
487 {
488 (source == TIM_TIxExternalCLK1Source_TI2) ? (TI2_Configure(tim, polarity, TIM_ICSelection_DirectTI, filter))
489 : (TI1_Configure(tim, polarity, TIM_ICSelection_DirectTI, filter));
490 TIM_SelectInputTrigger(tim, (TIMTS_TypeDef)source);
491 SET_BIT(tim->SMCR, TIM_SlaveMode_External1);
492 }
493
494 ////////////////////////////////////////////////////////////////////////////////
495 /// @brief Configures the tim External Trigger (ETR).
496 /// @param tim: select the TIM peripheral.
497 /// @param psc: The external Trigger Prescaler.
498 /// This parameter can be one of the following values:
499 /// @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
500 /// @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
501 /// @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
502 /// @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
503 /// @param polarity: The external Trigger Polarity.
504 /// This parameter can be one of the following values:
505 /// @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
506 /// @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
507 /// @param filter: External Trigger Filter.
508 /// This parameter must be a value between 0x00 and 0x0F
509 /// @retval None.
510 ////////////////////////////////////////////////////////////////////////////////
TIM_ETRConfig(TIM_TypeDef * tim,TIMEXTTRGPSC_Typedef psc,TIMETP_Typedef polarity,u16 filter)511 void TIM_ETRConfig(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter)
512 {
513 CLEAR_BIT(tim->SMCR, TIM_SMCR_ECEN);
514 MODIFY_REG(tim->SMCR, TIM_SMCR_ETP, polarity);
515 MODIFY_REG(tim->SMCR, TIM_SMCR_ETPS, psc);
516 MODIFY_REG(tim->SMCR, TIM_SMCR_ETF, filter << 8);
517 }
518
519 ////////////////////////////////////////////////////////////////////////////////
520 /// @brief Configures the External clock Mode1
521 /// @param tim: select the TIM peripheral.
522 /// @param psc: The external Trigger Prescaler.
523 /// This parameter can be one of the following values:
524 /// @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
525 /// @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
526 /// @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
527 /// @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
528 /// @param polarity: The external Trigger Polarity.
529 /// This parameter can be one of the following values:
530 /// @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
531 /// @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
532 /// @param filter: External Trigger Filter.
533 /// This parameter must be a value between 0x00 and 0x0F
534 /// @retval None.
535 ////////////////////////////////////////////////////////////////////////////////
TIM_ETRClockMode1Config(TIM_TypeDef * tim,TIMEXTTRGPSC_Typedef psc,TIMETP_Typedef polarity,u16 filter)536 void TIM_ETRClockMode1Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter)
537 {
538 TIM_ETRConfig(tim, psc, polarity, filter);
539 MODIFY_REG(tim->SMCR, TIM_SMCR_TS | TIM_SMCR_SMS, ((u32)TIM_TS_ETRF) | ((u32)TIM_SlaveMode_External1));
540 }
541
542 ////////////////////////////////////////////////////////////////////////////////
543 /// @brief Configures the External clock Mode2
544 /// @param tim: select the TIM peripheral.
545 /// @param psc: The external Trigger Prescaler.
546 /// This parameter can be one of the following values:
547 /// @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
548 /// @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
549 /// @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
550 /// @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
551 /// @param polarity: The external Trigger Polarity.
552 /// This parameter can be one of the following values:
553 /// @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
554 /// @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
555 /// @param filter: External Trigger Filter.
556 /// This parameter must be a value between 0x00 and 0x0F
557 /// @retval None.
558 ////////////////////////////////////////////////////////////////////////////////
TIM_ETRClockMode2Config(TIM_TypeDef * tim,TIMEXTTRGPSC_Typedef psc,TIMETP_Typedef polarity,u16 filter)559 void TIM_ETRClockMode2Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter)
560 {
561 TIM_ETRConfig(tim, psc, polarity, filter);
562 SET_BIT(tim->SMCR, TIM_SMCR_ECEN);
563 }
564
565 ////////////////////////////////////////////////////////////////////////////////
566 /// @brief Configures the tim Prescaler.
567 /// @param tim: select the TIM peripheral.
568 /// @param prescaler: specifies the Prescaler Register value
569 /// @param reloadMode: specifies the TIM Prescaler Reload mode
570 /// This parameter can be one of the following values:
571 /// @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
572 /// @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
573 /// @retval None.
574 ////////////////////////////////////////////////////////////////////////////////
TIM_PrescalerConfig(TIM_TypeDef * tim,u16 prescaler,TIMUG_Typedef reloadMode)575 void TIM_PrescalerConfig(TIM_TypeDef* tim, u16 prescaler, TIMUG_Typedef reloadMode)
576 {
577 WRITE_REG(tim->PSC, prescaler);
578 WRITE_REG(tim->EGR, reloadMode);
579 }
580
581 ////////////////////////////////////////////////////////////////////////////////
582 /// @brief Specifies the tim Counter Mode to be used.
583 /// @param tim:select the TIM peripheral.
584 /// @param counter_mode: specifies the Counter Mode to be used
585 /// This parameter can be one of the following values:
586 /// @arg TIM_CounterMode_Up: TIM Up Counting Mode
587 /// @arg TIM_CounterMode_Down: TIM Down Counting Mode
588 /// @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
589 /// @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
590 /// @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
591 /// @retval None.
592 ////////////////////////////////////////////////////////////////////////////////
TIM_CounterModeConfig(TIM_TypeDef * tim,TIMCOUNTMODE_Typedef counter_mode)593 void TIM_CounterModeConfig(TIM_TypeDef* tim, TIMCOUNTMODE_Typedef counter_mode)
594 {
595 MODIFY_REG(tim->CR1, TIM_CR1_CMS | TIM_CR1_DIR, counter_mode);
596 }
597
598 ////////////////////////////////////////////////////////////////////////////////
599 /// @brief Selects the Input Trigger source
600 /// @param tim: select the TIM peripheral.
601 /// @param source: The Input Trigger source.
602 /// This parameter can be one of the following values:
603 /// @arg TIM_TS_ITR0: Internal Trigger 0
604 /// @arg TIM_TS_ITR1: Internal Trigger 1
605 /// @arg TIM_TS_ITR2: Internal Trigger 2
606 /// @arg TIM_TS_ITR3: Internal Trigger 3
607 /// @arg TIM_TS_TI1F_ED: TI1 Edge Detector
608 /// @arg TIM_TS_TI1FP1: Filtered Timer Input 1
609 /// @arg TIM_TS_TI2FP2: Filtered Timer Input 2
610 /// @arg TIM_TS_ETRF: External Trigger input
611 /// @retval None.
612 ////////////////////////////////////////////////////////////////////////////////
TIM_SelectInputTrigger(TIM_TypeDef * tim,TIMTS_TypeDef source)613 void TIM_SelectInputTrigger(TIM_TypeDef* tim, TIMTS_TypeDef source)
614 {
615 MODIFY_REG(tim->SMCR, TIM_SMCR_TS, source);
616 }
617
618 ////////////////////////////////////////////////////////////////////////////////
619 /// @brief Configures the tim Encoder Interface.
620 /// @param tim: select the TIM peripheral.
621 /// @param encoder_mode: specifies the tim Encoder Mode.
622 /// This parameter can be one of the following values:
623 /// @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
624 /// @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
625 /// @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
626 /// on the level of the other input.
627 /// @param ic1_polarity: specifies the IC1 Polarity
628 /// This parameter can be one of the following values:
629 /// @arg TIM_ICPolarity_Falling: IC Falling edge.
630 /// @arg TIM_ICPolarity_Rising: IC Rising edge.
631 /// @param ic2_polarity: specifies the IC2 Polarity
632 /// This parameter can be one of the following values:
633 /// @arg TIM_ICPolarity_Falling: IC Falling edge.
634 /// @arg TIM_ICPolarity_Rising: IC Rising edge.
635 /// @retval None.
636 ////////////////////////////////////////////////////////////////////////////////
TIM_EncoderInterfaceConfig(TIM_TypeDef * tim,TIMSMSENCODER_Typedef encoder_mode,TIMICP_Typedef ic1_polarity,TIMICP_Typedef ic2_polarity)637 void TIM_EncoderInterfaceConfig(TIM_TypeDef* tim,
638 TIMSMSENCODER_Typedef encoder_mode,
639 TIMICP_Typedef ic1_polarity,
640 TIMICP_Typedef ic2_polarity)
641 {
642 MODIFY_REG(tim->SMCR, TIM_SMCR_SMS, encoder_mode);
643 MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC1S | TIM_CCMR1_CC2S, TIM_CCMR1_CC1S_DIRECTTI | TIM_CCMR1_CC2S_DIRECTTI);
644 MODIFY_REG(tim->CCER, TIM_CCER_CC1P | TIM_CCER_CC2P, ic1_polarity | (ic2_polarity << 4));
645 }
646
647 ////////////////////////////////////////////////////////////////////////////////
648 /// @brief Forces the tim output 1 waveform to active or inactive level.
649 /// @param tim: select the TIM peripheral.
650 /// @param forced_action: specifies the forced Action to be set to the output waveform.
651 /// This parameter can be one of the following values:
652 /// @arg TIM_ForcedAction_Active: Force active level on OC1REF
653 /// @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
654 /// @retval None.
655 ////////////////////////////////////////////////////////////////////////////////
TIM_ForcedOC1Config(TIM_TypeDef * tim,TIMOCMODE_Typedef forced_action)656 void TIM_ForcedOC1Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action)
657 {
658 MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, forced_action);
659 }
660
661 ////////////////////////////////////////////////////////////////////////////////
662 /// @brief Forces the tim output 2 waveform to active or inactive level.
663 /// @param tim: select the TIM peripheral.
664 /// @param forced_action: specifies the forced Action to be set to the output waveform.
665 /// This parameter can be one of the following values:
666 /// @arg TIM_ForcedAction_Active: Force active level on OC2REF
667 /// @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
668 /// @retval None.
669 ////////////////////////////////////////////////////////////////////////////////
TIM_ForcedOC2Config(TIM_TypeDef * tim,TIMOCMODE_Typedef forced_action)670 void TIM_ForcedOC2Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action)
671 {
672 MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, forced_action << 8);
673 }
674
675 ////////////////////////////////////////////////////////////////////////////////
676 /// @brief Forces the tim output 3 waveform to active or inactive level.
677 /// @param tim: select the TIM peripheral.
678 /// @param forced_action: specifies the forced Action to be set to the output waveform.
679 /// This parameter can be one of the following values:
680 /// @arg TIM_ForcedAction_Active: Force active level on OC3REF
681 /// @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
682 /// @retval None.
683 ////////////////////////////////////////////////////////////////////////////////
TIM_ForcedOC3Config(TIM_TypeDef * tim,TIMOCMODE_Typedef forced_action)684 void TIM_ForcedOC3Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action)
685 {
686 MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, forced_action);
687 }
688
689 ////////////////////////////////////////////////////////////////////////////////
690 /// @brief Forces the tim output 4 waveform to active or inactive level.
691 /// @param tim: select the TIM peripheral.
692 /// @param forced_action: specifies the forced Action to be set to the output waveform.
693 /// This parameter can be one of the following values:
694 /// @arg TIM_ForcedAction_Active: Force active level on OC4REF
695 /// @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
696 /// @retval None.
697 ////////////////////////////////////////////////////////////////////////////////
TIM_ForcedOC4Config(TIM_TypeDef * tim,TIMOCMODE_Typedef forced_action)698 void TIM_ForcedOC4Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action)
699 {
700 MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, forced_action << 8);
701 }
702
703 ////////////////////////////////////////////////////////////////////////////////
704 /// @brief Enables or disables tim peripheral Preload register on ARR.
705 /// @param tim: select the TIM peripheral.
706 /// @param state: new state of the tim peripheral Preload register
707 /// This parameter can be: ENABLE or DISABLE.
708 /// @retval None.
709 ////////////////////////////////////////////////////////////////////////////////
TIM_ARRPreloadConfig(TIM_TypeDef * tim,FunctionalState state)710 void TIM_ARRPreloadConfig(TIM_TypeDef* tim, FunctionalState state)
711 {
712 (state) ? SET_BIT(tim->CR1, TIM_CR1_ARPEN) : CLEAR_BIT(tim->CR1, TIM_CR1_ARPEN);
713 }
714
715 ////////////////////////////////////////////////////////////////////////////////
716 /// @brief Selects the TIM peripheral Commutation event.
717 /// @param tim: select the tim peripheral.
718 /// @param state: new state of the Commutation event.
719 /// This parameter can be: ENABLE or DISABLE.
720 /// @retval None.
721 ////////////////////////////////////////////////////////////////////////////////
TIM_SelectCOM(TIM_TypeDef * tim,FunctionalState state)722 void TIM_SelectCOM(TIM_TypeDef* tim, FunctionalState state)
723 {
724 (state) ? SET_BIT(tim->CR2, TIM_CR2_CCUS) : CLEAR_BIT(tim->CR2, TIM_CR2_CCUS);
725 }
726 ////////////////////////////////////////////////////////////////////////////////
727 /// @brief Selects the tim peripheral Capture Compare DMA source.
728 /// @param tim: select the TIM peripheral.
729 /// @param state: new state of the Capture Compare DMA source
730 /// This parameter can be: ENABLE or DISABLE.
731 /// @retval None.
732 ////////////////////////////////////////////////////////////////////////////////
TIM_SelectCCDMA(TIM_TypeDef * tim,FunctionalState state)733 void TIM_SelectCCDMA(TIM_TypeDef* tim, FunctionalState state)
734 {
735 (state) ? SET_BIT(tim->CR2, TIM_CR2_CCDS) : CLEAR_BIT(tim->CR2, TIM_CR2_CCDS);
736 }
737 ////////////////////////////////////////////////////////////////////////////////
738 /// @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
739 /// @param tim: select the tim peripheral.
740 /// @param state: new state of the Capture Compare Preload Control bit
741 /// This parameter can be: ENABLE or DISABLE.
742 /// @retval None.
743 ////////////////////////////////////////////////////////////////////////////////
TIM_CCPreloadControl(TIM_TypeDef * tim,FunctionalState state)744 void TIM_CCPreloadControl(TIM_TypeDef* tim, FunctionalState state)
745 {
746 (state) ? SET_BIT(tim->CR2, TIM_CR2_CCPC) : CLEAR_BIT(tim->CR2, TIM_CR2_CCPC);
747 }
748
749 ////////////////////////////////////////////////////////////////////////////////
750 /// @brief Enables or disables the tim peripheral Preload register on CCR1.
751 /// @param tim: select the TIM peripheral.
752 /// @param preload: new state of the tim peripheral Preload register
753 /// This parameter can be one of the following values:
754 /// @arg TIM_OCPreload_Enable
755 /// @arg TIM_OCPreload_Disable
756 /// @retval None.
757 ////////////////////////////////////////////////////////////////////////////////
TIM_OC1PreloadConfig(TIM_TypeDef * tim,TIMOCPE_Typedef preload)758 void TIM_OC1PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
759 {
760 MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1PEN, preload);
761 }
762
763 ////////////////////////////////////////////////////////////////////////////////
764 /// @brief Enables or disables the tim peripheral Preload register on CCR2.
765 /// @param tim: select the TIM peripheral.
766 /// @param preload: new state of the tim peripheral Preload register
767 /// This parameter can be one of the following values:
768 /// @arg TIM_OCPreload_Enable
769 /// @arg TIM_OCPreload_Disable
770 /// @retval None.
771 ////////////////////////////////////////////////////////////////////////////////
TIM_OC2PreloadConfig(TIM_TypeDef * tim,TIMOCPE_Typedef preload)772 void TIM_OC2PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
773 {
774 MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2PEN, preload << 8);
775 }
776
777 ////////////////////////////////////////////////////////////////////////////////
778 /// @brief Enables or disables the tim peripheral Preload register on CCR3.
779 /// @param tim: select the TIM peripheral.
780 /// @param preload: new state of the tim peripheral Preload register
781 /// This parameter can be one of the following values:
782 /// @arg TIM_OCPreload_Enable
783 /// @arg TIM_OCPreload_Disable
784 /// @retval None.
785 ////////////////////////////////////////////////////////////////////////////////
TIM_OC3PreloadConfig(TIM_TypeDef * tim,TIMOCPE_Typedef preload)786 void TIM_OC3PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
787 {
788 MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3PEN, preload);
789 }
790
791 ////////////////////////////////////////////////////////////////////////////////
792 /// @brief Enables or disables the tim peripheral Preload register on CCR4.
793 /// @param tim: select the TIM peripheral.
794 /// @param preload: new state of the tim peripheral Preload register
795 /// This parameter can be one of the following values:
796 /// @arg TIM_OCPreload_Enable
797 /// @arg TIM_OCPreload_Disable
798 /// @retval None.
799 ////////////////////////////////////////////////////////////////////////////////
TIM_OC4PreloadConfig(TIM_TypeDef * tim,TIMOCPE_Typedef preload)800 void TIM_OC4PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
801 {
802 MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4PEN, preload << 8);
803 }
804
805 ////////////////////////////////////////////////////////////////////////////////
806 /// @brief Configures the tim Output Compare 1 Fast feature.
807 /// @param tim: select the TIM peripheral.
808 /// @param fast: new state of the Output Compare Fast Enable Bit.
809 /// This parameter can be one of the following values:
810 /// @arg TIM_OCFast_Enable: TIM output compare fast enable
811 /// @arg TIM_OCFast_Disable: TIM output compare fast disable
812 /// @retval None.
813 ////////////////////////////////////////////////////////////////////////////////
TIM_OC1FastConfig(TIM_TypeDef * tim,TIMOCFE_Typedef fast)814 void TIM_OC1FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
815 {
816 MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1FEN, fast);
817 }
818
819 ////////////////////////////////////////////////////////////////////////////////
820 /// @brief Configures the tim Output Compare 2 Fast feature.
821 /// @param tim: select the TIM peripheral.
822 /// @param fast: new state of the Output Compare Fast Enable Bit.
823 /// This parameter can be one of the following values:
824 /// @arg TIM_OCFast_Enable: TIM output compare fast enable
825 /// @arg TIM_OCFast_Disable: TIM output compare fast disable
826 /// @retval None.
827 ////////////////////////////////////////////////////////////////////////////////
TIM_OC2FastConfig(TIM_TypeDef * tim,TIMOCFE_Typedef fast)828 void TIM_OC2FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
829 {
830 MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2FEN, fast << 8);
831 }
832
833 ////////////////////////////////////////////////////////////////////////////////
834 /// @brief Configures the tim Output Compare 3 Fast feature.
835 /// @param tim: select the TIM peripheral.
836 /// @param fast: new state of the Output Compare Fast Enable Bit.
837 /// This parameter can be one of the following values:
838 /// @arg TIM_OCFast_Enable: TIM output compare fast enable
839 /// @arg TIM_OCFast_Disable: TIM output compare fast disable
840 /// @retval None.
841 ////////////////////////////////////////////////////////////////////////////////
TIM_OC3FastConfig(TIM_TypeDef * tim,TIMOCFE_Typedef fast)842 void TIM_OC3FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
843 {
844 MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3FEN, fast);
845 }
846
847 ////////////////////////////////////////////////////////////////////////////////
848 /// @brief Configures the tim Output Compare 4 Fast feature.
849 /// @param tim: select the TIM peripheral.
850 /// @param fast: new state of the Output Compare Fast Enable Bit.
851 /// This parameter can be one of the following values:
852 /// @arg TIM_OCFast_Enable: TIM output compare fast enable
853 /// @arg TIM_OCFast_Disable: TIM output compare fast disable
854 /// @retval None.
855 ////////////////////////////////////////////////////////////////////////////////
TIM_OC4FastConfig(TIM_TypeDef * tim,TIMOCFE_Typedef fast)856 void TIM_OC4FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
857 {
858 MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4FEN, fast << 8);
859 }
860
861 ////////////////////////////////////////////////////////////////////////////////
862 /// @brief Clears or safeguards the OCREF1 signal on an external event
863 /// @param tim: select the TIM peripheral.
864 /// @param clear: new state of the Output Compare Clear Enable Bit.
865 /// This parameter can be one of the following values:
866 /// @arg TIM_OCClear_Enable: TIM Output clear enable
867 /// @arg TIM_OCClear_Disable: TIM Output clear disable
868 /// @retval None.
869 ////////////////////////////////////////////////////////////////////////////////
TIM_ClearOC1Ref(TIM_TypeDef * tim,TIMOCCE_Typedef clear)870 void TIM_ClearOC1Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
871 {
872 MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1CEN, clear);
873 }
874
875 ////////////////////////////////////////////////////////////////////////////////
876 /// @brief Clears or safeguards the OCREF2 signal on an external event
877 /// @param tim: select the TIM peripheral.
878 /// @param clear: new state of the Output Compare Clear Enable Bit.
879 /// This parameter can be one of the following values:
880 /// @arg TIM_OCClear_Enable: TIM Output clear enable
881 /// @arg TIM_OCClear_Disable: TIM Output clear disable
882 /// @retval None.
883 ////////////////////////////////////////////////////////////////////////////////
TIM_ClearOC2Ref(TIM_TypeDef * tim,TIMOCCE_Typedef clear)884 void TIM_ClearOC2Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
885 {
886 MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2CEN, clear << 8);
887 }
888
889 ////////////////////////////////////////////////////////////////////////////////
890 /// @brief Clears or safeguards the OCREF3 signal on an external event
891 /// @param tim: select the TIM peripheral.
892 /// @param clear: new state of the Output Compare Clear Enable Bit.
893 /// This parameter can be one of the following values:
894 /// @arg TIM_OCClear_Enable: TIM Output clear enable
895 /// @arg TIM_OCClear_Disable: TIM Output clear disable
896 /// @retval None.
897 ////////////////////////////////////////////////////////////////////////////////
TIM_ClearOC3Ref(TIM_TypeDef * tim,TIMOCCE_Typedef clear)898 void TIM_ClearOC3Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
899 {
900 MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3CEN, clear);
901 }
902
903 ////////////////////////////////////////////////////////////////////////////////
904 /// @brief Clears or safeguards the OCREF4 signal on an external event
905 /// @param tim: select the TIM peripheral.
906 /// @param clear: new state of the Output Compare Clear Enable Bit.
907 /// This parameter can be one of the following values:
908 /// @arg TIM_OCClear_Enable: TIM Output clear enable
909 /// @arg TIM_OCClear_Disable: TIM Output clear disable
910 /// @retval None.
911 ////////////////////////////////////////////////////////////////////////////////
TIM_ClearOC4Ref(TIM_TypeDef * tim,TIMOCCE_Typedef clear)912 void TIM_ClearOC4Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
913 {
914 MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4CEN, clear << 8);
915 }
916
917 ////////////////////////////////////////////////////////////////////////////////
918 /// @brief Configures the tim channel 1 polarity.
919 /// @param tim: select the TIM peripheral.
920 /// @param polarity: specifies the OC1 Polarity
921 /// This parameter can be one of the following values:
922 /// @arg TIM_OCPolarity_High: Output Compare active high
923 /// @arg TIM_OCPolarity_Low: Output Compare active low
924 /// @retval None.
925 ////////////////////////////////////////////////////////////////////////////////
TIM_OC1PolarityConfig(TIM_TypeDef * tim,TIMCCxP_Typedef polarity)926 void TIM_OC1PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
927 {
928 MODIFY_REG(tim->CCER, TIM_CCER_CC1P, polarity);
929 }
930
931 ////////////////////////////////////////////////////////////////////////////////
932 /// @brief Configures the tim Channel 1N polarity.
933 /// @param tim: select the TIM peripheral.
934 /// @param polarity: specifies the OC1N Polarity
935 /// This parameter can be one of the following values:
936 /// @arg TIM_OCNPolarity_High: Output Compare active high
937 /// @arg TIM_OCNPolarity_Low: Output Compare active low
938 /// @retval None.
939 ////////////////////////////////////////////////////////////////////////////////
TIM_OC1NPolarityConfig(TIM_TypeDef * tim,TIMCCxNP_Typedef polarity)940 void TIM_OC1NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity)
941 {
942 MODIFY_REG(tim->CCER, TIM_CCER_CC1NP, polarity);
943 }
944
945 ////////////////////////////////////////////////////////////////////////////////
946 /// @brief Configures the tim channel 2 polarity.
947 /// @param tim: select the TIM peripheral.
948 /// @param polarity: specifies the OC2 Polarity
949 /// This parameter can be one of the following values:
950 /// @arg TIM_OCPolarity_High: Output Compare active high
951 /// @arg TIM_OCPolarity_Low: Output Compare active low
952 /// @retval None.
953 ////////////////////////////////////////////////////////////////////////////////
TIM_OC2PolarityConfig(TIM_TypeDef * tim,TIMCCxP_Typedef polarity)954 void TIM_OC2PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
955 {
956 MODIFY_REG(tim->CCER, TIM_CCER_CC2P, polarity << 4);
957 }
958
959 ////////////////////////////////////////////////////////////////////////////////
960 /// @brief Configures the tim Channel 2N polarity.
961 /// @param tim: select the TIM peripheral.
962 /// @param polarity: specifies the OC2N Polarity
963 /// This parameter can be one of the following values:
964 /// @arg TIM_OCNPolarity_High: Output Compare active high
965 /// @arg TIM_OCNPolarity_Low: Output Compare active low
966 /// @retval None.
967 ////////////////////////////////////////////////////////////////////////////////
TIM_OC2NPolarityConfig(TIM_TypeDef * tim,TIMCCxNP_Typedef polarity)968 void TIM_OC2NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity)
969 {
970 MODIFY_REG(tim->CCER, TIM_CCER_CC2NP, polarity << 4);
971 }
972
973 ////////////////////////////////////////////////////////////////////////////////
974 /// @brief Configures the tim channel 3 polarity.
975 /// @param tim: select the TIM peripheral.
976 /// @param polarity: specifies the OC3 Polarity
977 /// This parameter can be one of the following values:
978 /// @arg TIM_OCPolarity_High: Output Compare active high
979 /// @arg TIM_OCPolarity_Low: Output Compare active low
980 /// @retval None.
981 ////////////////////////////////////////////////////////////////////////////////
TIM_OC3PolarityConfig(TIM_TypeDef * tim,TIMCCxP_Typedef polarity)982 void TIM_OC3PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
983 {
984 MODIFY_REG(tim->CCER, TIM_CCER_CC3P, polarity << 8);
985 }
986
987 ////////////////////////////////////////////////////////////////////////////////
988 /// @brief Configures the tim Channel 3N polarity.
989 /// @param tim: select the TIM peripheral.
990 /// @param polarity: specifies the OC3N Polarity
991 /// This parameter can be one of the following values:
992 /// @arg TIM_OCNPolarity_High: Output Compare active high
993 /// @arg TIM_OCNPolarity_Low: Output Compare active low
994 /// @retval None.
995 ////////////////////////////////////////////////////////////////////////////////
TIM_OC3NPolarityConfig(TIM_TypeDef * tim,TIMCCxNP_Typedef polarity)996 void TIM_OC3NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity)
997 {
998 MODIFY_REG(tim->CCER, TIM_CCER_CC3NP, polarity << 8);
999 }
1000
1001 ////////////////////////////////////////////////////////////////////////////////
1002 /// @brief Configures the tim channel 4 polarity.
1003 /// @param tim: select the TIM peripheral.
1004 /// @param polarity: specifies the OC4 Polarity
1005 /// This parameter can be one of the following values:
1006 /// @arg TIM_OCPolarity_High: Output Compare active high
1007 /// @arg TIM_OCPolarity_Low: Output Compare active low
1008 /// @retval None.
1009 ////////////////////////////////////////////////////////////////////////////////
TIM_OC4PolarityConfig(TIM_TypeDef * tim,TIMCCxP_Typedef polarity)1010 void TIM_OC4PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
1011 {
1012 MODIFY_REG(tim->CCER, TIM_CCER_CC4P, polarity << 12);
1013 }
1014
1015 ////////////////////////////////////////////////////////////////////////////////
1016 /// @brief Enables or disables the TIM Capture Compare Channel x.
1017 /// @param tim: select the TIM peripheral.
1018 /// @param channel: specifies the TIM Channel
1019 /// This parameter can be one of the following values:
1020 /// @arg TIM_Channel_1: TIM Channel 1
1021 /// @arg TIM_Channel_2: TIM Channel 2
1022 /// @arg TIM_Channel_3: TIM Channel 3
1023 /// @arg TIM_Channel_4: TIM Channel 4
1024 /// @arg TIM_Channel_5: TIM Channel 5(Only for some MM32 TIM1/8)
1025 /// @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
1026 /// This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
1027 /// @retval None.
1028 ////////////////////////////////////////////////////////////////////////////////
TIM_CCxCmd(TIM_TypeDef * tim,TIMCHx_Typedef channel,TIMCCxE_Typedef ccx_en)1029 void TIM_CCxCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxE_Typedef ccx_en)
1030 {
1031 MODIFY_REG(tim->CCER, TIM_CCER_CC1EN << channel, ccx_en << channel);
1032 }
1033
1034 ////////////////////////////////////////////////////////////////////////////////
1035 /// @brief Enables or disables the TIM Capture Compare Channel xN.
1036 /// @param tim: select the TIM peripheral.
1037 /// @param channel: specifies the TIM Channel
1038 /// This parameter can be one of the following values:
1039 /// @arg TIM_Channel_1: TIM Channel 1
1040 /// @arg TIM_Channel_2: TIM Channel 2
1041 /// @arg TIM_Channel_3: TIM Channel 3
1042 /// @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
1043 /// This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
1044 /// @retval None.
1045 ////////////////////////////////////////////////////////////////////////////////
TIM_CCxNCmd(TIM_TypeDef * tim,TIMCHx_Typedef channel,TIMCCxNE_Typedef ccxn_en)1046 void TIM_CCxNCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxNE_Typedef ccxn_en)
1047 {
1048 if (channel != TIM_Channel_4)
1049 MODIFY_REG(tim->CCER, TIM_CCER_CC1NEN << channel, ccxn_en << channel);
1050 }
1051
1052 ////////////////////////////////////////////////////////////////////////////////
1053 /// @brief Selects the TIM Output Compare Mode.
1054 /// @note This function disables the selected channel before changing the Output
1055 /// Compare Mode.
1056 /// User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
1057 /// @param tim: select the TIM peripheral.
1058 /// @param channel: specifies the TIM Channel
1059 /// This parameter can be one of the following values:
1060 /// @arg TIM_Channel_1: TIM Channel 1
1061 /// @arg TIM_Channel_2: TIM Channel 2
1062 /// @arg TIM_Channel_3: TIM Channel 3
1063 /// @arg TIM_Channel_4: TIM Channel 4
1064 /// @param mode: specifies the TIM Output Compare Mode.
1065 /// This parameter can be one of the following values:
1066 /// @arg TIM_OCMode_Timing
1067 /// @arg TIM_OCMode_Active
1068 /// @arg TIM_OCMode_Toggle
1069 /// @arg TIM_OCMode_PWM1
1070 /// @arg TIM_OCMode_PWM2
1071 /// @arg TIM_ForcedAction_Active
1072 /// @arg TIM_ForcedAction_InActive
1073 /// @retval None.
1074 ////////////////////////////////////////////////////////////////////////////////
TIM_SelectOCxM(TIM_TypeDef * tim,TIMCHx_Typedef channel,TIMOCMODE_Typedef mode)1075 void TIM_SelectOCxM(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMOCMODE_Typedef mode)
1076 {
1077 CLEAR_BIT(tim->CCER, TIM_CCER_CC1EN << channel);
1078 switch (channel) {
1079 case TIM_Channel_1:
1080 MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, mode);
1081 break;
1082 case TIM_Channel_2:
1083 MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, mode << 8);
1084 break;
1085 case TIM_Channel_3:
1086 MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, mode);
1087 break;
1088 case TIM_Channel_4:
1089 MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, mode << 8);
1090 break;
1091 default:
1092 break;
1093 }
1094 }
1095
1096 ////////////////////////////////////////////////////////////////////////////////
1097 /// @brief Enables or Disables the tim Update event.
1098 /// @param tim: select the TIM peripheral.
1099 /// @param state: new state of the tim UDIS bit
1100 /// This parameter can be: ENABLE or DISABLE.
1101 /// @retval None.
1102 ////////////////////////////////////////////////////////////////////////////////
TIM_UpdateDisableConfig(TIM_TypeDef * tim,FunctionalState state)1103 void TIM_UpdateDisableConfig(TIM_TypeDef* tim, FunctionalState state)
1104 {
1105 (state) ? SET_BIT(tim->CR1, TIM_CR1_UDIS) : CLEAR_BIT(tim->CR1, TIM_CR1_UDIS);
1106 }
1107
1108 ////////////////////////////////////////////////////////////////////////////////
1109 /// @brief Configures the tim Update Request Interrupt source.
1110 /// @param tim: select the TIM peripheral.
1111 /// @param source: specifies the Update source.
1112 /// This parameter can be one of the following values:
1113 /// @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
1114 /// or the setting of UG bit, or an update generation
1115 /// through the slave mode controller.
1116 /// @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
1117 /// @retval None.
1118 ////////////////////////////////////////////////////////////////////////////////
TIM_UpdateRequestConfig(TIM_TypeDef * tim,TIMURS_Typedef source)1119 void TIM_UpdateRequestConfig(TIM_TypeDef* tim, TIMURS_Typedef source)
1120 {
1121 MODIFY_REG(tim->CR1, TIM_CR1_URS, source);
1122 }
1123
1124 ////////////////////////////////////////////////////////////////////////////////
1125 /// @brief Enables or disables the tim's Hall sensor interface.
1126 /// @param tim: select the TIM peripheral.
1127 /// @param state: new state of the tim Hall sensor interface.
1128 /// This parameter can be: ENABLE or DISABLE.
1129 /// @retval None.
1130 ////////////////////////////////////////////////////////////////////////////////
TIM_SelectHallSensor(TIM_TypeDef * tim,FunctionalState state)1131 void TIM_SelectHallSensor(TIM_TypeDef* tim, FunctionalState state)
1132 {
1133 (state) ? SET_BIT(tim->CR2, TIM_CR2_TI1S) : CLEAR_BIT(tim->CR2, TIM_CR2_TI1S);
1134 }
1135
1136 ////////////////////////////////////////////////////////////////////////////////
1137 /// @brief Selects the tim's One Pulse Mode.
1138 /// @param tim: select the TIM peripheral.
1139 /// @param mode: specifies the OPM Mode to be used.
1140 /// This parameter can be one of the following values:
1141 /// @arg TIM_OPMode_Single
1142 /// @arg TIM_OPMode_Repetitive
1143 /// @retval None.
1144 ////////////////////////////////////////////////////////////////////////////////
TIM_SelectOnePulseMode(TIM_TypeDef * tim,TIMOPMODE_Typedef mode)1145 void TIM_SelectOnePulseMode(TIM_TypeDef* tim, TIMOPMODE_Typedef mode)
1146 {
1147 MODIFY_REG(tim->CR1, TIM_CR1_OPM, mode);
1148 }
1149
1150 ////////////////////////////////////////////////////////////////////////////////
1151 /// @brief Selects the tim Trigger Output Mode.
1152 /// @param tim:select the TIM peripheral.
1153 /// @param source: specifies the Trigger Output source.
1154 /// This paramter can be one of the following values:
1155 /// - For all tim
1156 /// @arg TIM_TRIGSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRIG).
1157 /// @arg TIM_TRIGSource_Enable: The Counter Enable CEN is used as the trigger output (TRIG).
1158 /// @arg TIM_TRIGSource_Update: The update event is selected as the trigger output (TRIG).
1159 /// @arg TIM_TRIGSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
1160 /// is to be set, as soon as a capture or compare match occurs (TRIG).
1161 /// @arg TIM_TRIGSource_OC1Ref: OC1REF signal is used as the trigger output (TRIG).
1162 /// @arg TIM_TRIGSource_OC2Ref: OC2REF signal is used as the trigger output (TRIG).
1163 /// @arg TIM_TRIGSource_OC3Ref: OC3REF signal is used as the trigger output (TRIG).
1164 /// @arg TIM_TRIGSource_OC4Ref: OC4REF signal is used as the trigger output (TRIG).
1165 ///
1166 /// @retval None.
1167 ////////////////////////////////////////////////////////////////////////////////
TIM_SelectOutputTrigger(TIM_TypeDef * tim,TIMMMS_Typedef source)1168 void TIM_SelectOutputTrigger(TIM_TypeDef* tim, TIMMMS_Typedef source)
1169 {
1170 MODIFY_REG(tim->CR2, TIM_CR2_MMS, source);
1171 }
1172
1173 ////////////////////////////////////////////////////////////////////////////////
1174 /// @brief Selects the tim Slave Mode.
1175 /// @param tim: select the TIM peripheral.
1176 /// @param mode: specifies the Timer Slave Mode.
1177 /// This parameter can be one of the following values:
1178 /// @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
1179 /// the counter and triggers an update of the registers.
1180 /// @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
1181 /// @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
1182 /// @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
1183 /// @retval None.
1184 ////////////////////////////////////////////////////////////////////////////////
TIM_SelectSlaveMode(TIM_TypeDef * tim,TIMSMSMODE_Typedef mode)1185 void TIM_SelectSlaveMode(TIM_TypeDef* tim, TIMSMSMODE_Typedef mode)
1186 {
1187 MODIFY_REG(tim->SMCR, TIM_SMCR_SMS, mode);
1188 }
1189
1190 ////////////////////////////////////////////////////////////////////////////////
1191 /// @brief Sets or Resets the tim Master/Slave Mode.
1192 /// @param tim: select the TIM peripheral.
1193 /// @param mode: specifies the Timer Master Slave Mode.
1194 /// This parameter can be one of the following values:
1195 /// @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
1196 /// and its slaves (through TRIG).
1197 /// @arg TIM_MasterSlaveMode_Disable: No action
1198 /// @retval None.
1199 ////////////////////////////////////////////////////////////////////////////////
TIM_SelectMasterSlaveMode(TIM_TypeDef * tim,TIMMSM_Typedef mode)1200 void TIM_SelectMasterSlaveMode(TIM_TypeDef* tim, TIMMSM_Typedef mode)
1201 {
1202 MODIFY_REG(tim->SMCR, TIM_SMCR_MSM, mode);
1203 }
1204
1205 ////////////////////////////////////////////////////////////////////////////////
1206 /// @brief Sets the tim Counter Register value
1207 /// @param tim: select the TIM peripheral.
1208 /// @param auto_reload: specifies the Counter register new value.
1209 /// @retval None.
1210 ////////////////////////////////////////////////////////////////////////////////
TIM_SetAutoreload(TIM_TypeDef * tim,u16 auto_reload)1211 void TIM_SetAutoreload(TIM_TypeDef* tim, u16 auto_reload)
1212 {
1213 WRITE_REG(tim->ARR, auto_reload);
1214 }
1215
1216 ////////////////////////////////////////////////////////////////////////////////
1217 /// @brief Sets the tim Input Capture 1 prescaler.
1218 /// @param tim: select the TIM peripheral.
1219 /// @param psc: specifies the Input Capture1 prescaler new value.
1220 /// This parameter can be one of the following values:
1221 /// @arg TIM_ICPSC_DIV1: no prescaler
1222 /// @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1223 /// @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1224 /// @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1225 /// @retval None.
1226 ////////////////////////////////////////////////////////////////////////////////
TIM_SetIC1Prescaler(TIM_TypeDef * tim,TIMICPSC_Typedef psc)1227 void TIM_SetIC1Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc)
1228 {
1229 MODIFY_REG(tim->CCMR1, TIM_CCMR1_IC1PSC, psc);
1230 }
1231
1232 ////////////////////////////////////////////////////////////////////////////////
1233 /// @brief Sets the tim Input Capture 2 prescaler.
1234 /// @param tim: select the TIM peripheral.
1235 /// @param psc: specifies the Input Capture2 prescaler new value.
1236 /// This parameter can be one of the following values:
1237 /// @arg TIM_ICPSC_DIV1: no prescaler
1238 /// @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1239 /// @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1240 /// @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1241 /// @retval None.
1242 ////////////////////////////////////////////////////////////////////////////////
TIM_SetIC2Prescaler(TIM_TypeDef * tim,TIMICPSC_Typedef psc)1243 void TIM_SetIC2Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc)
1244 {
1245 MODIFY_REG(tim->CCMR1, TIM_CCMR1_IC2PSC, psc << 8);
1246 }
1247
1248 ////////////////////////////////////////////////////////////////////////////////
1249 /// @brief Sets the tim Input Capture 3 prescaler.
1250 /// @param tim: select the TIM peripheral.
1251 /// @param psc: specifies the Input Capture3 prescaler new value.
1252 /// This parameter can be one of the following values:
1253 /// @arg TIM_ICPSC_DIV1: no prescaler
1254 /// @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1255 /// @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1256 /// @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1257 /// @retval None.
1258 ////////////////////////////////////////////////////////////////////////////////
TIM_SetIC3Prescaler(TIM_TypeDef * tim,TIMICPSC_Typedef psc)1259 void TIM_SetIC3Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc)
1260 {
1261 MODIFY_REG(tim->CCMR2, TIM_CCMR2_IC3PSC, psc);
1262 }
1263
1264 ////////////////////////////////////////////////////////////////////////////////
1265 /// @brief Sets the tim Input Capture 4 prescaler.
1266 /// @param tim: select the TIM peripheral.
1267 /// @param psc: specifies the Input Capture4 prescaler new value.
1268 /// This parameter can be one of the following values:
1269 /// @arg TIM_ICPSC_DIV1: no prescaler
1270 /// @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1271 /// @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1272 /// @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1273 /// @retval None.
1274 ////////////////////////////////////////////////////////////////////////////////
TIM_SetIC4Prescaler(TIM_TypeDef * tim,TIMICPSC_Typedef psc)1275 void TIM_SetIC4Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc)
1276 {
1277 MODIFY_REG(tim->CCMR2, TIM_CCMR2_IC4PSC, psc << 8);
1278 }
1279
1280 ////////////////////////////////////////////////////////////////////////////////
1281 /// @brief Sets the tim Clock Division value.
1282 /// @param tim: select
1283 /// the TIM peripheral.
1284 /// @param clock_div: specifies the clock division value.
1285 /// This parameter can be one of the following value:
1286 /// @arg TIM_CKD_DIV1: TDTS = Tck_tim
1287 /// @arg TIM_CKD_DIV2: TDTS = 2 * Tck_tim
1288 /// @arg TIM_CKD_DIV4: TDTS = 4 * Tck_tim
1289 /// @retval None.
1290 ////////////////////////////////////////////////////////////////////////////////
TIM_SetClockDivision(TIM_TypeDef * tim,TIMCKD_TypeDef clock_div)1291 void TIM_SetClockDivision(TIM_TypeDef* tim, TIMCKD_TypeDef clock_div)
1292 {
1293 MODIFY_REG(tim->CR1, TIM_CR1_CKD, clock_div);
1294 }
1295
1296 ////////////////////////////////////////////////////////////////////////////////
1297 /// @brief Sets the tim Counter Register value
1298 /// @param tim: select the TIM peripheral.
1299 /// @param counter: specifies the Counter register new value.
1300 /// @retval None.
1301 ////////////////////////////////////////////////////////////////////////////////
TIM_SetCounter(TIM_TypeDef * tim,u32 counter)1302 void TIM_SetCounter(TIM_TypeDef* tim, u32 counter)
1303 {
1304 if ((tim == TIM2) || (tim == TIM5))
1305 WRITE_REG(tim->CNT, (u32)counter);
1306 else
1307 WRITE_REG(tim->CNT, (u16)counter);
1308 }
1309
1310 ////////////////////////////////////////////////////////////////////////////////
1311 /// @brief Sets the tim Capture Compare1 Register value
1312 /// @param tim: select the TIM peripheral.
1313 /// @param compare: specifies the Capture Compare1 register new value.
1314 /// @retval None.
1315 ////////////////////////////////////////////////////////////////////////////////
TIM_SetCompare1(TIM_TypeDef * tim,u32 compare)1316 void TIM_SetCompare1(TIM_TypeDef* tim, u32 compare)
1317 {
1318 if ((tim == TIM2) || (tim == TIM5))
1319 WRITE_REG(tim->CCR1, (u32)compare);
1320 else
1321 WRITE_REG(tim->CCR1, (u16)compare);
1322 }
1323
1324 ////////////////////////////////////////////////////////////////////////////////
1325 /// @brief Sets the tim Capture Compare2 Register value
1326 /// @param tim: select the TIM peripheral.
1327 /// @param compare: specifies the Capture Compare2 register new value.
1328 /// @retval None.
1329 ////////////////////////////////////////////////////////////////////////////////
TIM_SetCompare2(TIM_TypeDef * tim,u32 compare)1330 void TIM_SetCompare2(TIM_TypeDef* tim, u32 compare)
1331 {
1332 if ((tim == TIM2) || (tim == TIM5))
1333 WRITE_REG(tim->CCR2, (u32)compare);
1334 else
1335 WRITE_REG(tim->CCR2, (u16)compare);
1336 }
1337
1338 ////////////////////////////////////////////////////////////////////////////////
1339 /// @brief Sets the tim Capture Compare3 Register value
1340 /// @param tim: select the TIM peripheral.
1341 /// @param compare: specifies the Capture Compare3 register new value.
1342 /// @retval None.
1343 ////////////////////////////////////////////////////////////////////////////////
TIM_SetCompare3(TIM_TypeDef * tim,u32 compare)1344 void TIM_SetCompare3(TIM_TypeDef* tim, u32 compare)
1345 {
1346 if ((tim == TIM2) || (tim == TIM5))
1347 WRITE_REG(tim->CCR3, (u32)compare);
1348 else
1349 WRITE_REG(tim->CCR3, (u16)compare);
1350 }
1351
1352 ////////////////////////////////////////////////////////////////////////////////
1353 /// @brief Sets the tim Capture Compare4 Register value
1354 /// @param tim: select the TIM peripheral.
1355 /// @param compare: specifies the Capture Compare4 register new value.
1356 /// @retval None.
1357 ////////////////////////////////////////////////////////////////////////////////
TIM_SetCompare4(TIM_TypeDef * tim,u32 compare)1358 void TIM_SetCompare4(TIM_TypeDef* tim, u32 compare)
1359 {
1360 if ((tim == TIM2) || (tim == TIM5))
1361 WRITE_REG(tim->CCR4, (u32)compare);
1362 else
1363 WRITE_REG(tim->CCR4, (u16)compare);
1364 }
1365
1366 ////////////////////////////////////////////////////////////////////////////////
1367 /// @brief Gets the tim Input Capture 1 value.
1368 /// @param tim: select the TIM peripheral.
1369 /// @retval Value: Capture Compare 1 Register value.
1370 ////////////////////////////////////////////////////////////////////////////////
TIM_GetCapture1(TIM_TypeDef * tim)1371 u32 TIM_GetCapture1(TIM_TypeDef* tim)
1372 {
1373 return tim->CCR1;
1374 }
1375
1376 ////////////////////////////////////////////////////////////////////////////////
1377 /// @brief Gets the tim Input Capture 2 value.
1378 /// @param tim: select the TIM peripheral.
1379 /// @retval Value: Capture Compare 2 Register value.
1380 ////////////////////////////////////////////////////////////////////////////////
TIM_GetCapture2(TIM_TypeDef * tim)1381 u32 TIM_GetCapture2(TIM_TypeDef* tim)
1382 {
1383 return tim->CCR2;
1384 }
1385
1386 ////////////////////////////////////////////////////////////////////////////////
1387 /// @brief Gets the tim Input Capture 3 value.
1388 /// @param tim: select the TIM peripheral.
1389 /// @retval Value: Capture Compare 3 Register value.
1390 ////////////////////////////////////////////////////////////////////////////////
TIM_GetCapture3(TIM_TypeDef * tim)1391 u32 TIM_GetCapture3(TIM_TypeDef* tim)
1392 {
1393 return tim->CCR3;
1394 }
1395
1396 ////////////////////////////////////////////////////////////////////////////////
1397 /// @brief Gets the tim Input Capture 4 value.
1398 /// @param tim: select the TIM peripheral.
1399 /// @retval Value: Capture Compare 4 Register value.
1400 ////////////////////////////////////////////////////////////////////////////////
TIM_GetCapture4(TIM_TypeDef * tim)1401 u32 TIM_GetCapture4(TIM_TypeDef* tim)
1402 {
1403 return tim->CCR4;
1404 }
1405
1406 ////////////////////////////////////////////////////////////////////////////////
1407 /// @brief Gets the tim Counter value.
1408 /// @param tim: select the TIM peripheral.
1409 /// @retval Value: Counter Register value.
1410 ////////////////////////////////////////////////////////////////////////////////
TIM_GetCounter(TIM_TypeDef * tim)1411 u32 TIM_GetCounter(TIM_TypeDef* tim)
1412 {
1413 return tim->CNT;
1414 }
1415
1416 ////////////////////////////////////////////////////////////////////////////////
1417 /// @brief Gets the tim Prescaler value.
1418 /// @param tim: select the TIM peripheral.
1419 /// @retval Value: Prescaler Register value.
1420 ////////////////////////////////////////////////////////////////////////////////
TIM_GetPrescaler(TIM_TypeDef * tim)1421 u16 TIM_GetPrescaler(TIM_TypeDef* tim)
1422 {
1423 return tim->PSC;
1424 }
1425
1426 ////////////////////////////////////////////////////////////////////////////////
1427 /// @brief Checks whether the specified TIM flag is set or not.
1428 /// @param tim: select the TIM peripheral.
1429 /// @param flag: specifies the flag to check.
1430 /// This parameter can be one of the following values:
1431 /// @arg TIM_FLAG_Update: TIM update Flag
1432 /// @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
1433 /// @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
1434 /// @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
1435 /// @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
1436 /// @arg TIM_FLAG_COM: TIM Commutation Flag
1437 /// @arg TIM_FLAG_Trigger: TIM Trigger Flag
1438 /// @arg TIM_FLAG_Break: TIM Break Flag
1439 /// @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
1440 /// @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
1441 /// @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
1442 /// @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
1443 /// @note
1444 /// - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
1445 /// - TIM_FLAG_Break is used only with TIM1 and TIM8.
1446 /// - TIM_FLAG_COM is used only with TIM1, TIM8, TIM16 and TIM17.
1447 /// @retval State: The new state of TIM_FLAG (SET or RESET).
1448 ////////////////////////////////////////////////////////////////////////////////
TIM_GetFlagStatus(TIM_TypeDef * tim,TIMFLAG_Typedef flag)1449 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* tim, TIMFLAG_Typedef flag)
1450 {
1451 return ((tim->SR & flag) ? SET : RESET);
1452 }
1453
1454 ////////////////////////////////////////////////////////////////////////////////
1455 /// @brief Clears the tim's pending flags.
1456 /// @param tim: select the TIM peripheral.
1457 /// @param flag: specifies the flag bit to clear.
1458 /// This parameter can be any combination of the following values:
1459 /// @arg TIM_FLAG_Update: TIM update Flag
1460 /// @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
1461 /// @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
1462 /// @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
1463 /// @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
1464 /// @arg TIM_FLAG_COM: TIM Commutation Flag
1465 /// @arg TIM_FLAG_Trigger: TIM Trigger Flag
1466 /// @arg TIM_FLAG_Break: TIM Break Flag
1467 /// @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
1468 /// @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
1469 /// @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
1470 /// @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
1471 /// @note
1472 /// - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
1473 /// - TIM_FLAG_Break is used only with TIM1 and TIM8.
1474 /// - TIM_FLAG_COM is used only with TIM1, TIM8, TIM16 and TIM17.
1475 /// @retval None.
1476 ////////////////////////////////////////////////////////////////////////////////
TIM_ClearFlag(TIM_TypeDef * tim,TIMFLAG_Typedef flag)1477 void TIM_ClearFlag(TIM_TypeDef* tim, TIMFLAG_Typedef flag)
1478 {
1479 CLEAR_BIT(tim->SR, flag);
1480 }
1481
1482 ////////////////////////////////////////////////////////////////////////////////
1483 /// @brief Checks whether the TIM interrupt has occurred or not.
1484 /// @param tim: select the TIM peripheral.
1485 /// @param it: specifies the TIM interrupt source to check.
1486 /// This parameter can be one of the following values:
1487 /// @arg TIM_IT_Update: TIM update Interrupt source
1488 /// @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
1489 /// @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
1490 /// @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
1491 /// @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
1492 /// @arg TIM_IT_COM: TIM Commutation Interrupt source
1493 /// @arg TIM_IT_Trigger: TIM Trigger Interrupt source
1494 /// @arg TIM_IT_Break: TIM Break Interrupt source
1495 /// @note
1496 /// - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
1497 /// - TIM_IT_Break is used only with TIM1 and TIM8.
1498 /// - TIM_IT_COM is used only with TIM1, TIM8, TIM16 and TIM17.
1499 /// @retval State: The new state of the TIM_IT(SET or RESET).
1500 ////////////////////////////////////////////////////////////////////////////////
TIM_GetITStatus(TIM_TypeDef * tim,TIMIT_TypeDef it)1501 ITStatus TIM_GetITStatus(TIM_TypeDef* tim, TIMIT_TypeDef it)
1502 {
1503 return (((tim->SR & it) && (tim->DIER & it)) ? SET : RESET);
1504 }
1505
1506 ////////////////////////////////////////////////////////////////////////////////
1507 /// @brief Clears the tim's interrupt pending bits.
1508 /// @param tim: select the TIM peripheral.
1509 /// @param it: specifies the pending bit to clear.
1510 /// This parameter can be any combination of the following values:
1511 /// @arg TIM_IT_Update: TIM1 update Interrupt source
1512 /// @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
1513 /// @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
1514 /// @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
1515 /// @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
1516 /// @arg TIM_IT_COM: TIM Commutation Interrupt source
1517 /// @arg TIM_IT_Trigger: TIM Trigger Interrupt source
1518 /// @arg TIM_IT_Break: TIM Break Interrupt source
1519 /// @note
1520 /// - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
1521 /// - TIM_IT_Break is used only with TIM1 and TIM8.
1522 /// - TIM_IT_COM is used only with TIM1, TIM8, TIM16 and TIM17.
1523 /// @retval None.
1524 ////////////////////////////////////////////////////////////////////////////////
TIM_ClearITPendingBit(TIM_TypeDef * tim,u32 it)1525 void TIM_ClearITPendingBit(TIM_TypeDef* tim, u32 it) //TIMIT_TypeDef
1526 {
1527 CLEAR_BIT(tim->SR, it);
1528 }
1529
1530 ////////////////////////////////////////////////////////////////////////////////
1531 /// @brief Configures the tim channel 1 polarity.
1532 /// @param tim: select the TIM peripheral.
1533 /// @param polarity: specifies the IC1 Polarity
1534 /// This parameter can be one of the following values:
1535 /// @arg TIM_ICPolarity_Rising
1536 /// @arg TIM_ICPolarity_Falling
1537 /// @retval None.
1538 ////////////////////////////////////////////////////////////////////////////////
TIM_SetIC1Plority(TIM_TypeDef * tim,TIMICP_Typedef pol)1539 void TIM_SetIC1Plority(TIM_TypeDef* tim, TIMICP_Typedef pol)
1540 {
1541 (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC1P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC1P);
1542 }
1543
1544 ////////////////////////////////////////////////////////////////////////////////
1545 /// @brief Configures the tim channel 2 polarity.
1546 /// @param tim: select the TIM peripheral.
1547 /// @param polarity: specifies the IC2 Polarity
1548 /// This parameter can be one of the following values:
1549 /// @arg TIM_ICPolarity_Rising
1550 /// @arg TIM_ICPolarity_Falling
1551 /// @retval None.
1552 ////////////////////////////////////////////////////////////////////////////////
TIM_SetIC2Plority(TIM_TypeDef * tim,TIMICP_Typedef pol)1553 void TIM_SetIC2Plority(TIM_TypeDef* tim, TIMICP_Typedef pol)
1554 {
1555 (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC2P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC2P);
1556 }
1557
1558 ////////////////////////////////////////////////////////////////////////////////
1559 /// @brief Configures the tim channel 3 polarity.
1560 /// @param tim: select the TIM peripheral.
1561 /// @param polarity: specifies the IC3 Polarity
1562 /// This parameter can be one of the following values:
1563 /// @arg TIM_ICPolarity_Rising
1564 /// @arg TIM_ICPolarity_Falling
1565 /// @retval None.
1566 ////////////////////////////////////////////////////////////////////////////////
TIM_SetIC3Plority(TIM_TypeDef * tim,TIMICP_Typedef pol)1567 void TIM_SetIC3Plority(TIM_TypeDef* tim, TIMICP_Typedef pol)
1568 {
1569 (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC3P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC3P);
1570 }
1571
1572 ////////////////////////////////////////////////////////////////////////////////
1573 /// @brief Configures the tim channel 4 polarity.
1574 /// @param tim: select the TIM peripheral.
1575 /// @param polarity: specifies the IC4 Polarity
1576 /// This parameter can be one of the following values:
1577 /// @arg TIM_ICPolarity_Rising
1578 /// @arg TIM_ICPolarity_Falling
1579 /// @retval None.
1580 ////////////////////////////////////////////////////////////////////////////////
TIM_SetIC4Plority(TIM_TypeDef * tim,TIMICP_Typedef pol)1581 void TIM_SetIC4Plority(TIM_TypeDef* tim, TIMICP_Typedef pol)
1582 {
1583 (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC4P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC4P);
1584 }
1585
1586
1587 ////////////////////////////////////////////////////////////////////////////////
1588 /// @brief Sets the tim Capture Compare 5 Register value
1589 /// @param tim: select the TIM peripheral.
1590 /// @param compare: specifies the Capture Compare5 register new value.
1591 /// @retval None.
1592 ////////////////////////////////////////////////////////////////////////////////
TIM_SetCompare5(TIM_TypeDef * tim,u32 compare)1593 void TIM_SetCompare5(TIM_TypeDef* tim, u32 compare)
1594 {
1595 WRITE_REG(tim->CCR5, (u16)compare);
1596 }
1597
1598 ////////////////////////////////////////////////////////////////////////////////
1599 /// @brief Gets the tim Input Capture 5 value.
1600 /// @param tim: select the TIM peripheral.
1601 /// @retval Value: Capture Compare 5 Register value.
1602 ////////////////////////////////////////////////////////////////////////////////
TIM_GetCapture5(TIM_TypeDef * tim)1603 u32 TIM_GetCapture5(TIM_TypeDef* tim)
1604 {
1605 return tim->CCR5;
1606 }
1607
1608 ////////////////////////////////////////////////////////////////////////////////
1609 /// @brief Initializes the tim Channel5 according to the specified
1610 /// parameters in the init_struct.
1611 /// @param tim: select the TIM peripheral.
1612 /// @param init_struct: pointer to a TIM_OCInitTypeDef structure that
1613 /// contains the configuration information for the specified TIM peripheral.
1614 /// @retval None.
1615 ////////////////////////////////////////////////////////////////////////////////
TIM_OC5Init(TIM_TypeDef * tim,TIM_OCInitTypeDef * init_struct)1616 void TIM_OC5Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
1617 {
1618 MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5M, (init_struct->TIM_OCMode) << 4);
1619 MODIFY_REG(tim->CCER, TIM_CCER_CC5EN | TIM_CCER_CC5P,
1620 (init_struct->TIM_OCPolarity << 16) | (init_struct->TIM_OutputState << 16));
1621 WRITE_REG(tim->CCR4, init_struct->TIM_Pulse);
1622
1623 if ((tim == TIM1) || (tim == TIM8))
1624 MODIFY_REG(tim->CR2, TIM_CR2_OIS5, init_struct->TIM_OCIdleState << 8);
1625 }
1626
1627 ////////////////////////////////////////////////////////////////////////////////
1628 /// @brief Enables or disables the tim peripheral Preload register on CCR5.
1629 /// @param tim: select the TIM peripheral.
1630 /// @param preload: new state of the tim peripheral Preload register
1631 /// This parameter can be one of the following values:
1632 /// @arg TIM_OCPreload_Enable
1633 /// @arg TIM_OCPreload_Disable
1634 /// @retval None.
1635 ////////////////////////////////////////////////////////////////////////////////
TIM_OC5PreloadConfig(TIM_TypeDef * tim,TIMOCPE_Typedef preload)1636 void TIM_OC5PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
1637 {
1638 MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5PEN, preload);
1639 }
1640
1641 ////////////////////////////////////////////////////////////////////////////////
1642 /// @brief Configures the tim channel 5 polarity.
1643 /// @param tim: select the TIM peripheral.
1644 /// @param polarity: specifies the OC5 Polarity
1645 /// This parameter can be one of the following values:
1646 /// @arg TIM_OCPolarity_High: Output Compare active high
1647 /// @arg TIM_OCPolarity_Low: Output Compare active low
1648 /// @retval None.
1649 ////////////////////////////////////////////////////////////////////////////////
TIM_OC5PolarityConfig(TIM_TypeDef * tim,TIMCCxP_Typedef polarity)1650 void TIM_OC5PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
1651 {
1652 MODIFY_REG(tim->CCER, TIM_CCER_CC5P, polarity << 16);
1653 }
1654
1655 ////////////////////////////////////////////////////////////////////////////////
1656 /// @brief Configures the tim Output Compare 5 Fast feature.
1657 /// @param tim: select the TIM peripheral.
1658 /// @param fast: new state of the Output Compare Fast Enable Bit.
1659 /// This parameter can be one of the following values:
1660 /// @arg TIM_OCFast_Enable: TIM output compare fast enable
1661 /// @arg TIM_OCFast_Disable: TIM output compare fast disable
1662 /// @retval None.
1663 ////////////////////////////////////////////////////////////////////////////////
TIM_OC5FastConfig(TIM_TypeDef * tim,TIMOCFE_Typedef fast)1664 void TIM_OC5FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
1665 {
1666 MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5FEN, fast);
1667 }
1668
1669 ////////////////////////////////////////////////////////////////////////////////
1670 /// @brief Clears or safeguards the OCREF4 signal on an external event
1671 /// @param tim: select the TIM peripheral.
1672 /// @param clear: new state of the Output Compare Clear Enable Bit.
1673 /// This parameter can be one of the following values:
1674 /// @arg TIM_OCClear_Enable: TIM Output clear enable
1675 /// @arg TIM_OCClear_Disable: TIM Output clear disable
1676 /// @retval None.
1677 ////////////////////////////////////////////////////////////////////////////////
TIM_ClearOC5Ref(TIM_TypeDef * tim,TIMOCCE_Typedef clear)1678 void TIM_ClearOC5Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
1679 {
1680 MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5CEN, clear);
1681 }
1682
1683
1684
1685 ////////////////////////////////////////////////////////////////////////////////
1686 /// @brief Enables or disables the tim complementary PWM output Status after Break.
1687 /// @param tim: select the TIM peripheral.
1688 /// @param state: new state of the tim complementary PWM output.
1689 /// This parameter can be: ENABLE or DISABLE.
1690 /// @arg ENABLE: Direct output enable, no longer waiting for output after dead time.
1691 /// @arg DISABLE: Direct output disable, output waiting for dead time.
1692 /// @retval None.
1693 ////////////////////////////////////////////////////////////////////////////////
TIM_DirectOutput(TIM_TypeDef * tim,FunctionalState state)1694 void TIM_DirectOutput(TIM_TypeDef* tim, FunctionalState state)
1695 {
1696 (state) ? SET_BIT(tim->BDTR, TIM_BDTR_DOEN) : CLEAR_BIT(tim->BDTR, TIM_BDTR_DOEN);
1697 }
1698
1699 /// @}
1700
1701 ////////////////////////////////////////////////////////////////////////////////
1702 /// @defgroup TIM_Private_Functions
1703 /// @{
1704
1705 ////////////////////////////////////////////////////////////////////////////////
1706 /// @brief Configure the TI1 as Input.
1707 /// @param tim: select the TIM peripheral.
1708 /// @param polarity : The Input Polarity.
1709 /// This parameter can be one of the following values:
1710 /// @arg TIM_ICPolarity_Rising
1711 /// @arg TIM_ICPolarity_Falling
1712 /// @param selection: specifies the input to be used.
1713 /// This parameter can be one of the following values:
1714 /// @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
1715 /// @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
1716 /// @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
1717 /// @param filter: Specifies the Input Capture Filter.
1718 /// This parameter must be a value between 0x00 and 0x0F.
1719 /// @retval None.
1720 ////////////////////////////////////////////////////////////////////////////////
TI1_Configure(TIM_TypeDef * tim,u16 polarity,u16 selection,u16 filter)1721 static void TI1_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter)
1722 {
1723 MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC1S | TIM_CCMR1_IC1F, (filter << 4) | selection);
1724 MODIFY_REG(tim->CCER, TIM_CCER_CC1EN | TIM_CCER_CC1P, polarity | TIM_CCER_CC1EN);
1725 }
1726
1727 ////////////////////////////////////////////////////////////////////////////////
1728 /// @brief Configure the TI2 as Input.
1729 /// @param tim: select the TIM peripheral.
1730 /// @param polarity : The Input Polarity.
1731 /// This parameter can be one of the following values:
1732 /// @arg TIM_ICPolarity_Rising
1733 /// @arg TIM_ICPolarity_Falling
1734 /// @param selection: specifies the input to be used.
1735 /// This parameter can be one of the following values:
1736 /// @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
1737 /// @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
1738 /// @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
1739 /// @param filter: Specifies the Input Capture Filter.
1740 /// This parameter must be a value between 0x00 and 0x0F.
1741 /// @retval None.
1742 ////////////////////////////////////////////////////////////////////////////////
TI2_Configure(TIM_TypeDef * tim,u16 polarity,u16 selection,u16 filter)1743 static void TI2_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter)
1744 {
1745 MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC2S | TIM_CCMR1_IC2F, (filter << 12) | (selection << 8));
1746 MODIFY_REG(tim->CCER, TIM_CCER_CC2EN | TIM_CCER_CC2P, (polarity << 4) | TIM_CCER_CC2EN);
1747 }
1748
1749 ////////////////////////////////////////////////////////////////////////////////
1750 /// @brief Configure the TI3 as Input.
1751 /// @param tim: select the TIM peripheral.
1752 /// @param polarity : The Input Polarity.
1753 /// This parameter can be one of the following values:
1754 /// @arg TIM_ICPolarity_Rising
1755 /// @arg TIM_ICPolarity_Falling
1756 /// @param selection: specifies the input to be used.
1757 /// This parameter can be one of the following values:
1758 /// @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
1759 /// @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
1760 /// @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
1761 /// @param filter: Specifies the Input Capture Filter.
1762 /// This parameter must be a value between 0x00 and 0x0F.
1763 /// @retval None.
1764 ////////////////////////////////////////////////////////////////////////////////
TI3_Configure(TIM_TypeDef * tim,u16 polarity,u16 selection,u16 filter)1765 static void TI3_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter)
1766 {
1767 MODIFY_REG(tim->CCMR2, TIM_CCMR2_CC3S | TIM_CCMR2_IC3F, (filter << 4) | selection);
1768 MODIFY_REG(tim->CCER, TIM_CCER_CC3EN | TIM_CCER_CC3P, (polarity << 8) | TIM_CCER_CC3EN);
1769 }
1770
1771 ////////////////////////////////////////////////////////////////////////////////
1772 /// @brief Configure the TI4 as Input.
1773 /// @param tim: select the TIM peripheral.
1774 /// @param polarity : The Input Polarity.
1775 /// This parameter can be one of the following values:
1776 /// @arg TIM_ICPolarity_Rising
1777 /// @arg TIM_ICPolarity_Falling
1778 /// @param selection: specifies the input to be used.
1779 /// This parameter can be one of the following values:
1780 /// @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
1781 /// @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
1782 /// @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
1783 /// @param filter: Specifies the Input Capture Filter.
1784 /// This parameter must be a value between 0x00 and 0x0F.
1785 /// @retval None.
1786 ////////////////////////////////////////////////////////////////////////////////
TI4_Configure(TIM_TypeDef * tim,u16 polarity,u16 selection,u16 filter)1787 static void TI4_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter)
1788 {
1789 MODIFY_REG(tim->CCMR2, TIM_CCMR2_CC4S | TIM_CCMR2_IC4F, (filter << 12) | (selection << 8));
1790 MODIFY_REG(tim->CCER, TIM_CCER_CC4EN | TIM_CCER_CC4P, (polarity << 12) | TIM_CCER_CC4EN);
1791 }
1792 ////////////////////////////////////////////////////////////////////////////////
1793 /// @brief Enables or disables the specified TIM PWM shift /DMA reqeat.
1794 /// @param tim: select the tim peripheral.
1795 /// @param it: Specifies the TIM PWM shift channel to enable or disable.
1796 /// This parameter can be any combination of the following values:
1797 /// @arg TIM_PDER_CCDREPE: TIM DMA reqeat enable bit
1798 /// @arg TIM_PDER_CCR1SHIFTEN: TIM Channel 1 output PWM phase shift enable bit
1799 /// @arg TIM_PDER_CCR2SHIFTEN: TIM Channel 2 output PWM phase shift enable bit
1800 /// @arg TIM_PDER_CCR3SHIFTEN: TIM Channel 3 output PWM phase shift enable bit
1801 /// @arg TIM_PDER_CCR4SHIFTEN: TIM Channel 4 output PWM phase shift enable bit
1802 /// @arg TIM_PDER_CCR5SHIFTEN: TIM Channel 5 output PWM phase shift enable bit
1803 /// @param state: new state of the TIM interrupts.
1804 /// This parameter can be: ENABLE or DISABLE.
1805 /// @retval None.
1806 ////////////////////////////////////////////////////////////////////////////////
TIM_PWMShiftConfig(TIM_TypeDef * tim,u32 it,FunctionalState state)1807 void TIM_PWMShiftConfig(TIM_TypeDef* tim, u32 it, FunctionalState state)//TIMIT_TypeDef
1808 {
1809 (state) ? SET_BIT(tim->PDER, it) : CLEAR_BIT(tim->PDER, it);
1810 }
1811 ////////////////////////////////////////////////////////////////////////////////
1812 /// @brief Sets the tim CCR1 shift Register value
1813 /// @param tim: select the TIM peripheral.
1814 /// @param compare: specifies the Capture Compare1 register new value.
1815 /// @retval None.
1816 ////////////////////////////////////////////////////////////////////////////////
TIM_SetCCR1FALL(TIM_TypeDef * tim,u32 shift)1817 void TIM_SetCCR1FALL(TIM_TypeDef* tim, u32 shift)
1818 {
1819 if (tim == TIM1)
1820 WRITE_REG(tim->CCR1FALL, (u32)shift);
1821
1822 }
1823 ////////////////////////////////////////////////////////////////////////////////
1824 /// @brief Sets the tim CCR2 shift Register value
1825 /// @param tim: select the TIM peripheral.
1826 /// @param compare: specifies the Capture Compare1 register new value.
1827 /// @retval None.
1828 ////////////////////////////////////////////////////////////////////////////////
TIM_SetCCR2FALL(TIM_TypeDef * tim,u32 shift)1829 void TIM_SetCCR2FALL(TIM_TypeDef* tim, u32 shift)
1830 {
1831 if (tim == TIM1)
1832 WRITE_REG(tim->CCR2FALL, (u32)shift);
1833
1834 }
1835 ////////////////////////////////////////////////////////////////////////////////
1836 /// @brief Sets the tim CCR3 shift Register value
1837 /// @param tim: select the TIM peripheral.
1838 /// @param compare: specifies the Capture Compare1 register new value.
1839 /// @retval None.
1840 ////////////////////////////////////////////////////////////////////////////////
TIM_SetCCR3FALL(TIM_TypeDef * tim,u32 shift)1841 void TIM_SetCCR3FALL(TIM_TypeDef* tim, u32 shift)
1842 {
1843 if (tim == TIM1)
1844 WRITE_REG(tim->CCR3FALL, (u32)shift);
1845
1846 }
1847 ////////////////////////////////////////////////////////////////////////////////
1848 /// @brief Sets the tim CCR4 shift Register value
1849 /// @param tim: select the TIM peripheral.
1850 /// @param compare: specifies the Capture Compare1 register new value.
1851 /// @retval None.
1852 ////////////////////////////////////////////////////////////////////////////////
TIM_SetCCR4FALL(TIM_TypeDef * tim,u32 shift)1853 void TIM_SetCCR4FALL(TIM_TypeDef* tim, u32 shift)
1854 {
1855 if (tim == TIM1)
1856 WRITE_REG(tim->CCR4FALL, (u32)shift);
1857
1858 }
1859 ////////////////////////////////////////////////////////////////////////////////
1860 /// @brief Sets the tim CCR5 shift Register value
1861 /// @param tim: select the TIM peripheral.
1862 /// @param compare: specifies the Capture Compare1 register new value.
1863 /// @retval None.
1864 ////////////////////////////////////////////////////////////////////////////////
TIM_SetCCR5FALL(TIM_TypeDef * tim,u32 shift)1865 void TIM_SetCCR5FALL(TIM_TypeDef* tim, u32 shift)
1866 {
1867 if (tim == TIM1)
1868 WRITE_REG(tim->CCR5FALL, (u32)shift);
1869
1870 }
1871 /// @}
1872
1873 /// @}
1874
1875 /// @}
1876