1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file hal_tim.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE TIM 5 /// FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 #ifndef __HAL_TIM_H 21 #define __HAL_TIM_H 22 23 // Files includes 24 #include "types.h" 25 #include "reg_tim.h" 26 27 //////////////////////////////////////////////////////////////////////////////// 28 /// @addtogroup MM32_Hardware_Abstract_Layer 29 /// @{ 30 31 //////////////////////////////////////////////////////////////////////////////// 32 /// @defgroup TIM_HAL 33 /// @brief TIM HAL modules 34 /// @{ 35 36 //////////////////////////////////////////////////////////////////////////////// 37 /// @defgroup TIM_Exported_Types 38 /// @{ 39 40 //////////////////////////////////////////////////////////////////////////////// 41 /// @brief TIM_Channel 42 /// @anchor TIM_Channel 43 typedef enum { 44 TIM_Channel_1 = 0x0000, ///< TIM Channel 1 45 TIM_Channel_2 = 0x0004, ///< TIM Channel 2 46 TIM_Channel_3 = 0x0008, ///< TIM Channel 3 47 TIM_Channel_4 = 0x000C, ///< TIM Channel 4 48 TIM_Channel_5 = 0x0010 ///< TIM Channel 5 49 } TIMCHx_Typedef; 50 51 //////////////////////////////////////////////////////////////////////////////// 52 /// @brief TIM_Counter_Mode 53 /// @anchor TIM_Counter_Mode 54 typedef enum { 55 TIM_CounterMode_Up = 0x0000, ///< TIM Up Counting Mode 56 TIM_CounterMode_Down = TIM_CR1_DIR, ///< TIM Down Counting Mode 57 TIM_CounterMode_CenterAligned1 = TIM_CR1_CMS_CENTERALIGNED1, ///< TIM Center Aligned Mode1 58 TIM_CounterMode_CenterAligned2 = TIM_CR1_CMS_CENTERALIGNED2, ///< TIM Center Aligned Mode2 59 TIM_CounterMode_CenterAligned3 = TIM_CR1_CMS_CENTERALIGNED3 ///< TIM Center Aligned Mode3 60 } TIMCOUNTMODE_Typedef; 61 62 //////////////////////////////////////////////////////////////////////////////// 63 /// @brief TIM_Output_Compare_and_PWM_modes_and_Forced_Action 64 /// @anchor TIM_Output_Compare_and_PWM_modes_and_Forced_Action 65 typedef enum { 66 TIM_OCMode_Timing = 0x0000, ///< Output compare mode: Timing 67 TIM_OCMode_Active = 0x0010, ///< Output compare mode: Active 68 TIM_OCMode_Inactive = 0x0020, ///< Output compare mode: Inactive 69 TIM_OCMode_Toggle = 0x0030, ///< Output compare mode: Toggle 70 TIM_OCMode_PWM1 = 0x0060, ///< Output compare mode: PWM1 71 TIM_OCMode_PWM2 = 0x0070, ///< Output compare mode: PWM2 72 TIM_ForcedAction_Active = 0x0050, ///< Force active level on OCnREF 73 TIM_ForcedAction_InActive = 0x0040 ///< Force inactive level on OCnREF 74 } TIMOCMODE_Typedef; 75 76 //////////////////////////////////////////////////////////////////////////////// 77 /// @brief TIM_Clock_Division_CKD 78 /// @anchor TIM_Clock_Division_CKD 79 typedef enum { 80 TIM_CKD_DIV1 = TIM_CR1_CKD_DIV1, ///< TDTS = Tck_tim 81 TIM_CKD_DIV2 = TIM_CR1_CKD_DIV2, ///< TDTS = 2 * Tck_tim 82 TIM_CKD_DIV4 = TIM_CR1_CKD_DIV4 ///< TDTS = 4 * Tck_tim 83 } TIMCKD_TypeDef; 84 85 //////////////////////////////////////////////////////////////////////////////// 86 /// @brief TIM_Internal_Trigger_Selection 87 /// @anchor TIM_Internal_Trigger_Selection 88 typedef enum { 89 TIM_TS_ITR0 = TIM_SMCR_TS_ITR0, ///< Internal Trigger 0 90 TIM_TS_ITR1 = TIM_SMCR_TS_ITR1, ///< Internal Trigger 1 91 TIM_TS_ITR2 = TIM_SMCR_TS_ITR2, ///< Internal Trigger 2 92 TIM_TS_ITR3 = TIM_SMCR_TS_ITR3, ///< Internal Trigger 3 93 TIM_TS_TI1F_ED = TIM_SMCR_TS_TI1F_ED, ///< TI1 Edge Detector 94 TIM_TS_TI1FP1 = TIM_SMCR_TS_TI1FP1, ///< Filtered Timer Input 1 95 TIM_TS_TI2FP2 = TIM_SMCR_TS_TI2FP2, ///< Filtered Timer Input 2 96 TIM_TS_ETRF = TIM_SMCR_TS_ETRF ///< TI1 Edge Detector 97 } TIMTS_TypeDef; 98 99 //////////////////////////////////////////////////////////////////////////////// 100 /// @brief TIM_Trigger_Output_Source 101 /// @anchor TIM_Trigger_Output_Source 102 typedef enum { 103 TIM_TRIGSource_Reset = TIM_CR2_MMS_RESET, ///< The UG bit in the TIM_EGR register is used as the trigger output (TRIG). 104 TIM_TRIGSource_Enable = TIM_CR2_MMS_ENABLE, ///< The Counter Enable CEN is used as the trigger output (TRIG). 105 TIM_TRIGSource_Update = TIM_CR2_MMS_UPDATE, ///< The update event is used as the trigger output (TRIG). 106 TIM_TRIGSource_OC1 = TIM_CR2_MMS_OC1, ///< The trigger output sends a positive pulse when the CC1IF flag 107 ///< is to be set, as soon as a capture or compare match occurs (TRIG). 108 TIM_TRIGSource_OC1Ref = TIM_CR2_MMS_OC1REF, ///< OC1REF signal is used as the trigger output (TRIG). 109 TIM_TRIGSource_OC2Ref = TIM_CR2_MMS_OC2REF, ///< OC2REF signal is used as the trigger output (TRIG). 110 TIM_TRIGSource_OC3Ref = TIM_CR2_MMS_OC3REF, ///< OC3REF signal is used as the trigger output (TRIG). 111 TIM_TRIGSource_OC4Ref = TIM_CR2_MMS_OC4REF ///< OC4REF signal is used as the trigger output (TRIG). 112 } TIMMMS_Typedef; 113 114 //////////////////////////////////////////////////////////////////////////////// 115 /// @brief TIM_Slave_Mode 116 /// @anchor TIM_Slave_Mode 117 typedef enum { 118 TIM_SlaveMode_Reset = TIM_SMCR_SMS_RESET, ///< Rising edge of the selected trigger signal (TRGI) re-initializes 119 ///< the counter and triggers an update of the registers. 120 TIM_SlaveMode_Gated = TIM_SMCR_SMS_GATED, ///< The counter clock is enabled when the trigger signal (TRGI) is high. 121 TIM_SlaveMode_Trigger = TIM_SMCR_SMS_TRIGGER, ///< The counter starts at a rising edge of the trigger TRGI. 122 TIM_SlaveMode_External1 = TIM_SMCR_SMS_EXTERNAL1 ///< Rising edges of the selected trigger (TRGI) clock the counter. 123 } TIMSMSMODE_Typedef; 124 125 //////////////////////////////////////////////////////////////////////////////// 126 /// @brief TIM_Event_Source 127 /// @anchor TIM_Event_Source 128 typedef enum { 129 TIM_EventSource_Update = TIM_EGR_UG, ///< Timer update Event source 130 TIM_EventSource_CC1 = TIM_EGR_CC1G, ///< Timer Capture Compare 1 Event source 131 TIM_EventSource_CC2 = TIM_EGR_CC2G, ///< Timer Capture Compare 2 Event source 132 TIM_EventSource_CC3 = TIM_EGR_CC3G, ///< Timer Capture Compare 3 Event source 133 TIM_EventSource_CC4 = TIM_EGR_CC4G, ///< Timer Capture Compare 4 Event source 134 TIM_EventSource_COM = TIM_EGR_COMG, ///< Timer COM event source 135 TIM_EventSource_Trigger = TIM_EGR_TG, ///< Timer Trigger Event source 136 TIM_EventSource_Break = TIM_EGR_BG, ///< Timer Break event source 137 TIM_EventSource_CC5 = (s32)0x00010000, ///< Timer Capture Compare 5 Event source 138 } TIMEGR_Typedef; 139 140 //////////////////////////////////////////////////////////////////////////////// 141 /// @brief TIM_External_Trigger_Prescaler 142 /// @anchor TIM_External_Trigger_Prescaler 143 typedef enum { 144 TIM_ExtTRGPSC_OFF = TIM_SMCR_ETPS_OFF, ///< ETRP Prescaler OFF 145 TIM_ExtTRGPSC_DIV2 = TIM_SMCR_ETPS_DIV2, ///< ETRP frequency divided by 2 146 TIM_ExtTRGPSC_DIV4 = TIM_SMCR_ETPS_DIV4, ///< ETRP frequency divided by 4 147 TIM_ExtTRGPSC_DIV8 = TIM_SMCR_ETPS_DIV8 ///< ETRP frequency divided by 8 148 } TIMEXTTRGPSC_Typedef; 149 150 //////////////////////////////////////////////////////////////////////////////// 151 /// @brief TIM_TIx_External_Clock_Source 152 /// @anchor TIM_TIx_External_Clock_Source 153 typedef enum { 154 TIM_TIxExternalCLK1Source_TI1 = TIM_SMCR_TS_TI1FP1, ///< Filtered Timer Input 1 155 TIM_TIxExternalCLK1Source_TI2 = TIM_SMCR_TS_TI2FP2, ///< Filtered Timer Input 2 156 TIM_TIxExternalCLK1Source_TI1ED = TIM_SMCR_TS_TI1F_ED ///< TI1 Edge Detector 157 } TIM_TIEXTCLKSRC_Typedef; 158 159 //////////////////////////////////////////////////////////////////////////////// 160 /// @brief Lock_level 161 /// @anchor Lock_level 162 typedef enum { 163 TIM_LOCKLevel_OFF = TIM_BDTR_LOCK_OFF, ///< No bit is write protected. 164 TIM_LOCKLevel_1 = TIM_BDTR_LOCK_1, ///< DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 165 ///< register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. 166 TIM_LOCKLevel_2 = TIM_BDTR_LOCK_2, ///< LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER 167 ///< register, as s32 as the related channel is configured in output through the CCxS 168 ///< bits) as well as OSSR and OSSI bits can no longer be written. 169 TIM_LOCKLevel_3 = TIM_BDTR_LOCK_3 ///< LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, 170 ///< as s32 as the related channel is configured in output through the CCxS bits) 171 ///< can no longer be written. 172 } TIMLOCKLEVEL_Typedef; 173 174 //////////////////////////////////////////////////////////////////////////////// 175 /// @brief TIM_One_Pulse_Mode 176 /// @anchor TIM_One_Pulse_Mode 177 typedef enum { 178 TIM_OPMode_Repetitive = 0, ///< Counter is not stopped at update event 179 TIM_OPMode_Single = TIM_CR1_OPM ///< Counter stops counting at the next update event (clearing the bit CEN) 180 } TIMOPMODE_Typedef; 181 182 //////////////////////////////////////////////////////////////////////////////// 183 /// @brief TIM_Output_Compare_Polarity 184 /// @anchor TIM_Output_Compare_Polarity 185 typedef enum { 186 TIM_OCPolarity_High, ///< Output Compare active high 187 TIM_OCPolarity_Low = TIM_CCER_CC1P ///< Output Compare active low 188 } TIMCCxP_Typedef; 189 190 //////////////////////////////////////////////////////////////////////////////// 191 /// @brief TIM_Output_Compare_N_Polarity 192 /// @anchor TIM_Output_Compare_N_Polarity 193 typedef enum { 194 TIM_OCNPolarity_High, ///< Output Compare active high 195 TIM_OCNPolarity_Low = TIM_CCER_CC1NP ///< Output Compare active low 196 } TIMCCxNP_Typedef; 197 198 //////////////////////////////////////////////////////////////////////////////// 199 /// @brief TIM_Output_Compare_state 200 /// @anchor TIM_Output_Compare_state 201 typedef enum { 202 TIM_OutputState_Disable = 0, ///< Output Compare Disable 203 TIM_OutputState_Enable = TIM_CCER_CC1EN ///< Output Compare Enable 204 } TIMOUTPUTSTATE_Typedef; 205 206 //////////////////////////////////////////////////////////////////////////////// 207 /// @brief TIM_Output_Compare_N_state 208 /// @anchor TIM_Output_Compare_N_state 209 typedef enum { 210 TIM_OutputNState_Disable = 0, ///< Output Compare N Disable 211 TIM_OutputNState_Enable = TIM_CCER_CC1NEN ///< Output Compare N Enable 212 } TIMOUTPUTNSTATE_Typedef; 213 214 //////////////////////////////////////////////////////////////////////////////// 215 /// @brief TIM_Capture_Compare_state 216 /// @anchor TIM_Capture_Compare_state 217 typedef enum { 218 TIM_CCx_Disable = 0, ///< Capture/Compare Enable 219 TIM_CCx_Enable = TIM_CCER_CC1EN ///< Capture/Compare Enable 220 } TIMCCxE_Typedef; 221 222 //////////////////////////////////////////////////////////////////////////////// 223 /// @brief TIM_Capture_Compare_N_state 224 /// @anchor TIM_Capture_Compare_N_state 225 typedef enum { 226 TIM_CCxN_Disable = 0, ///< Capture/Compare N Enable 227 TIM_CCxN_Enable = TIM_CCER_CC1NEN ///< Capture/Compare N Enable 228 } TIMCCxNE_Typedef; 229 230 //////////////////////////////////////////////////////////////////////////////// 231 /// @brief Break_Input_enable_disable 232 /// @anchor Break_Input_enable_disable 233 typedef enum { 234 TIM_Break_Disable = 0, ///< Break inputs (BRK and CSS clock failure event) disabled 235 TIM_Break_Enable = TIM_BDTR_BKEN ///< Break inputs (BRK and CSS clock failure event) enabled 236 } TIMBKE_Typedef; 237 238 //////////////////////////////////////////////////////////////////////////////// 239 /// @brief Break_Polarity 240 /// @anchor Break_Polarity 241 typedef enum { 242 TIM_BreakPolarity_Low = 0, ///< Break input BRK is active low 243 TIM_BreakPolarity_High = TIM_BDTR_BKP ///< Break input BRK is active high 244 } TIMBKP_Typedef; 245 246 //////////////////////////////////////////////////////////////////////////////// 247 /// @brief TIM_AOE_Bit_Set_Reset 248 /// @anchor TIM_AOE_Bit_Set_Reset 249 typedef enum { 250 TIM_AutomaticOutput_Disable = 0, ///< MOE can be set only by software. 251 TIM_AutomaticOutput_Enable = TIM_BDTR_AOEN ///< MOE can be set by software or automatically at the next 252 ///< update event (if the break input is not be active). 253 } TIMAOE_Typedef; 254 255 //////////////////////////////////////////////////////////////////////////////// 256 /// @brief TIM_DOE_Bit_Set_Reset 257 /// @anchor TIM_DOE_Bit_Set_Reset 258 typedef enum { 259 TIM_DirectOutput_Disable = 0, ///< Direct output disable, output waiting for dead time 260 TIM_DirectOutput_Enable = TIM_BDTR_DOEN ///< Direct output enable, no longer waiting for output after dead time 261 } TIMDOE_Typedef; 262 263 //////////////////////////////////////////////////////////////////////////////// 264 /// @brief OSSI_Off_State_Selection_for_Idle_mode_state 265 /// @anchor OSSI_Off_State_Selection_for_Idle_mode_state 266 typedef enum { 267 TIM_OSSIState_Disable = 0, ///< When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0). 268 TIM_OSSIState_Enable = TIM_BDTR_OSSI ///< When inactive, OC/OCN outputs are forced first with their idle level 269 ///< as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1). 270 } TIMOSSI_Typedef; 271 272 //////////////////////////////////////////////////////////////////////////////// 273 /// @brief OSSR_Off_State_Selection_for_Run_mode_state 274 /// @anchor OSSR_Off_State_Selection_for_Run_mode_state 275 typedef enum { 276 TIM_OSSRState_Disable = 0, ///< When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0). 277 TIM_OSSRState_Enable = TIM_BDTR_OSSR ///< When inactive, OC/OCN outputs are enabled with their inactive level 278 ///< as soon as CCxE=1 or CCxNE=1. Then, OC/OCN enable output signal=1. 279 } TIMOSSR_Typedef; 280 281 //////////////////////////////////////////////////////////////////////////////// 282 /// @brief TIM_Output_Compare_Idle_State 283 /// @anchor TIM_Output_Compare_Idle_State 284 typedef enum { 285 TIM_OCIdleState_Reset = 0, ///< OCn=0 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4) 286 TIM_OCIdleState_Set = TIM_CR2_OIS1 ///< OCn=1 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4) 287 } TIMOIS_Typedef; 288 289 //////////////////////////////////////////////////////////////////////////////// 290 /// @brief TIM_Output_Compare_N_Idle_State 291 /// @anchor TIM_Output_Compare_N_Idle_State 292 typedef enum { 293 TIM_OCNIdleState_Reset = 0, ///< OCnN=0 after a dead-time when MOE=0.(n= 0 : 4) 294 TIM_OCNIdleState_Set = TIM_CR2_OIS1N ///< OCnN=1 after a dead-time when MOE=0.(n= 0 : 4) 295 } TIMOISN_Typedef; 296 297 //////////////////////////////////////////////////////////////////////////////// 298 /// @brief TIM_Input_Capture_Selection 299 /// @anchor TIM_Input_Capture_Selection 300 typedef enum { 301 TIM_ICSelection_DirectTI = TIM_CCMR1_CC1S_DIRECTTI, 302 TIM_ICSelection_IndirectTI = TIM_CCMR1_CC1S_INDIRECTTI, 303 TIM_ICSelection_TRC = TIM_CCMR1_CC1S_TRC ///< TIM Input is selected to be connected to TRC. 304 } TIMICSEL_Typedef; 305 306 //////////////////////////////////////////////////////////////////////////////// 307 /// @brief TIM_Input_Capture_Prescaler 308 /// @anchor TIM_Input_Capture_Prescaler 309 typedef enum { 310 TIM_ICPSC_DIV1 = 0x0000, ///< no prescaler 311 TIM_ICPSC_DIV2 = 0x0004, ///< capture is done once every 2 events 312 TIM_ICPSC_DIV4 = 0x0008, ///< capture is done once every 4 events 313 TIM_ICPSC_DIV8 = 0x000C ///< capture is done once every 8 events 314 } TIMICPSC_Typedef; 315 316 //////////////////////////////////////////////////////////////////////////////// 317 /// @brief TIM_Input_Capture_Polarity 318 /// @anchor TIM_Input_Capture_Polarity 319 typedef enum { 320 TIM_ICPolarity_Rising = 0, ///< IC Rising edge 321 TIM_ICPolarity_Falling = TIM_CCER_CC1P, ///< IC Falling edge 322 TIM_ICPolarity_BothEdge = TIM_CCER_CC1P | TIM_CCER_CC1NP 323 } TIMICP_Typedef; 324 325 //////////////////////////////////////////////////////////////////////////////// 326 /// @brief TIM_External_Trigger_Polarity 327 /// @anchor TIM_External_Trigger_Polarity 328 typedef enum { 329 TIM_ExtTRGPolarity_NonInverted = 0, ///< Active high or rising edge active 330 TIM_ExtTRGPolarity_Inverted = TIM_SMCR_ETP ///< Active low or falling edge active 331 } TIMETP_Typedef; 332 333 //////////////////////////////////////////////////////////////////////////////// 334 /// @brief TIM_Prescaler_Reload_Mode 335 /// @anchor TIM_Prescaler_Reload_Mode 336 typedef enum { 337 TIM_PSCReloadMode_Update = 0, ///< The Prescaler is loaded at the update event 338 TIM_PSCReloadMode_Immediate = TIM_EGR_UG ///< The Prescaler is loaded immediately 339 } TIMUG_Typedef; 340 341 //////////////////////////////////////////////////////////////////////////////// 342 /// @brief TIM_Encoder_Mode 343 /// @anchor TIM_Encoder_Mode 344 typedef enum { 345 TIM_EncoderMode_TI1 = TIM_SMCR_SMS_ENCODER1, ///< Counter counts on TI1FP1 edge depending on TI2FP2 level. 346 TIM_EncoderMode_TI2 = TIM_SMCR_SMS_ENCODER2, ///< Counter counts on TI2FP2 edge depending on TI1FP1 level. 347 TIM_EncoderMode_TI12 = TIM_SMCR_SMS_ENCODER3 ///< Counter counts on both TI1FP1 and TI2FP2 edges depending 348 ///< on the level of the other input. 349 } TIMSMSENCODER_Typedef; 350 351 //////////////////////////////////////////////////////////////////////////////// 352 /// @brief TIM_Update_Source 353 /// @anchor TIM_Update_Source 354 typedef enum { 355 TIM_UpdateSource_Global = 0, ///< Source of update is counter overflow/underflow. 356 TIM_UpdateSource_Regular = TIM_CR1_URS ///< Source of update is the counter overflow/underflow 357 ///< or the setting of UG bit, or an update generation 358 ///< through the slave mode controller. 359 } TIMURS_Typedef; 360 361 //////////////////////////////////////////////////////////////////////////////// 362 /// @brief TIM_Output_Compare_Preload_State 363 /// @anchor TIM_Output_Compare_Preload_State 364 typedef enum { 365 TIM_OCPreload_Disable = 0, ///< TIM output compare preload disable 366 TIM_OCPreload_Enable = TIM_CCMR1_OC1PEN ///< TIM output compare preload enable 367 } TIMOCPE_Typedef; 368 369 //////////////////////////////////////////////////////////////////////////////// 370 /// @brief TIM_Output_Compare_Fast_State 371 /// @anchor TIM_Output_Compare_Fast_State 372 typedef enum { 373 TIM_OCFast_Disable = 0, ///< TIM output compare fast disable 374 TIM_OCFast_Enable = TIM_CCMR1_OC1FEN, ///< TIM output compare fast enable 375 } TIMOCFE_Typedef; 376 377 //////////////////////////////////////////////////////////////////////////////// 378 /// @brief TIM_Output_Compare_Clear_State 379 /// @anchor TIM_Output_Compare_Clear_State 380 typedef enum { 381 TIM_OCClear_Disable = 0, ///< TIM Output clear disable 382 TIM_OCClear_Enable = TIM_CCMR1_OC1CEN ///< TIM Output clear enable 383 } TIMOCCE_Typedef; 384 385 //////////////////////////////////////////////////////////////////////////////// 386 /// @brief TIM_Master_Slave_Mode 387 /// @anchor TIM_Master_Slave_Mode 388 typedef enum { 389 TIM_MasterSlaveMode_Disable = 0, ///< No action 390 TIM_MasterSlaveMode_Enable = TIM_SMCR_MSM ///< synchronization between the current timer and its slaves (through TRIG) 391 } TIMMSM_Typedef; 392 393 //////////////////////////////////////////////////////////////////////////////// 394 /// @brief TIM_interrupt_sources 395 /// @anchor TIM_Master_Slave_Mode 396 typedef enum { 397 TIM_IT_Update = TIM_DIER_UI, ///< TIM update Interrupt source 398 TIM_IT_CC1 = TIM_DIER_CC1I, ///< TIM Capture Compare 1 Interrupt source 399 TIM_IT_CC2 = TIM_DIER_CC2I, ///< TIM Capture Compare 2 Interrupt source 400 TIM_IT_CC3 = TIM_DIER_CC3I, ///< TIM Capture Compare 3 Interrupt source 401 TIM_IT_CC4 = TIM_DIER_CC4I, ///< TIM Capture Compare 4 Interrupt source 402 TIM_IT_COM = TIM_DIER_COMI, ///< TIM Commutation Interrupt source 403 TIM_IT_Trigger = TIM_DIER_TI, ///< TIM Trigger Interrupt source 404 TIM_IT_Break = TIM_DIER_BI ///< TIM Break Interrupt source 405 , TIM_IT_CC5 = TIM_DIER_CC5I ///< TIM Capture Compare 5 Interrupt source 406 } TIMIT_TypeDef; 407 408 //////////////////////////////////////////////////////////////////////////////// 409 /// @brief TIM_Flags 410 /// @anchor TIM_Flags 411 typedef enum { 412 TIM_FLAG_Update = TIM_SR_UI, ///< TIM update Flag 413 TIM_FLAG_CC1 = TIM_SR_CC1I, ///< TIM Capture Compare 1 Flag 414 TIM_FLAG_CC2 = TIM_SR_CC2I, ///< TIM Capture Compare 2 Flag 415 TIM_FLAG_CC3 = TIM_SR_CC3I, ///< TIM Capture Compare 3 Flag 416 TIM_FLAG_CC4 = TIM_SR_CC4I, ///< TIM Capture Compare 4 Flag 417 TIM_FLAG_COM = TIM_SR_COMI, ///< TIM Commutation Flag 418 TIM_FLAG_Trigger = TIM_SR_TI, ///< TIM Trigger Flag 419 TIM_FLAG_Break = TIM_SR_BI, ///< TIM Break Flag 420 TIM_FLAG_CC1OF = TIM_SR_CC1O, ///< TIM Capture Compare 1 overcapture Flag 421 TIM_FLAG_CC2OF = TIM_SR_CC2O, ///< TIM Capture Compare 2 overcapture Flag 422 TIM_FLAG_CC3OF = TIM_SR_CC3O, ///< TIM Capture Compare 3 overcapture Flag 423 TIM_FLAG_CC4OF = TIM_SR_CC4O ///< TIM Capture Compare 4 overcapture Flag 424 , TIM_FLAG_CC5 = TIM_SR_CC5I ///< TIM Capture Compare 5 Flag 425 } TIMFLAG_Typedef; 426 //////////////////////////////////////////////////////////////////////////////// 427 /// @brief TIM_DMA_sources 428 /// @anchor TIM_DMA_sources 429 typedef enum { 430 TIM_DMA_Update = TIM_DIER_UD, ///< TIM update Interrupt source 431 TIM_DMA_CC1 = TIM_DIER_CC1D, ///< TIM Capture Compare 1 DMA source 432 TIM_DMA_CC2 = TIM_DIER_CC2D, ///< TIM Capture Compare 2 DMA source 433 TIM_DMA_CC3 = TIM_DIER_CC3D, ///< TIM Capture Compare 3 DMA source 434 TIM_DMA_CC4 = TIM_DIER_CC4D, ///< TIM Capture Compare 4 DMA source 435 TIM_DMA_COM = TIM_DIER_COMD, ///< TIM Commutation DMA source 436 TIM_DMA_Trigger = TIM_DIER_TD ///< TIM Trigger DMA source 437 } TIMDMASRC_Typedef; 438 439 //////////////////////////////////////////////////////////////////////////////// 440 /// @brief TIM_DMA_Base_address 441 /// @anchor TIM_DMA_Base_address 442 typedef enum { 443 TIM_DMABase_CR1 = 0x0000, 444 TIM_DMABase_CR2 = 0x0001, 445 TIM_DMABase_SMCR = 0x0002, 446 TIM_DMABase_DIER = 0x0003, 447 TIM_DMABase_SR = 0x0004, 448 TIM_DMABase_EGR = 0x0005, 449 TIM_DMABase_CCMR1 = 0x0006, 450 TIM_DMABase_CCMR2 = 0x0007, 451 TIM_DMABase_CCER = 0x0008, 452 TIM_DMABase_CNT = 0x0009, 453 TIM_DMABase_PSC = 0x000A, 454 TIM_DMABase_ARR = 0x000B, 455 TIM_DMABase_RCR = 0x000C, 456 TIM_DMABase_CCR1 = 0x000D, 457 TIM_DMABase_CCR2 = 0x000E, 458 TIM_DMABase_CCR3 = 0x000F, 459 TIM_DMABase_CCR4 = 0x0010, 460 TIM_DMABase_BDTR = 0x0011, 461 TIM_DMABase_DCR = 0x0012 462 } TIMDMABASE_Typedef; 463 464 //////////////////////////////////////////////////////////////////////////////// 465 /// @brief TIM_DMA_Burst_Length 466 /// @anchor TIM_DMA_Burst_Length 467 typedef enum { 468 TIM_DMABurstLength_1Byte = 0x0000, 469 TIM_DMABurstLength_2Bytes = 0x0100, 470 TIM_DMABurstLength_3Bytes = 0x0200, 471 TIM_DMABurstLength_4Bytes = 0x0300, 472 TIM_DMABurstLength_5Bytes = 0x0400, 473 TIM_DMABurstLength_6Bytes = 0x0500, 474 TIM_DMABurstLength_7Bytes = 0x0600, 475 TIM_DMABurstLength_8Bytes = 0x0700, 476 TIM_DMABurstLength_9Bytes = 0x0800, 477 TIM_DMABurstLength_10Bytes = 0x0900, 478 TIM_DMABurstLength_11Bytes = 0x0A00, 479 TIM_DMABurstLength_12Bytes = 0x0B00, 480 TIM_DMABurstLength_13Bytes = 0x0C00, 481 TIM_DMABurstLength_14Bytes = 0x0D00, 482 TIM_DMABurstLength_15Bytes = 0x0E00, 483 TIM_DMABurstLength_16Bytes = 0x0F00, 484 TIM_DMABurstLength_17Bytes = 0x1000, 485 TIM_DMABurstLength_18Bytes = 0x1100 486 } TIMDMABURSTLENGTH_Typedef; 487 //////////////////////////////////////////////////////////////////////////////// 488 /// @brief TIM Time Base Init structure definition 489 /// @note This structure is used with all tim. 490 //////////////////////////////////////////////////////////////////////////////// 491 typedef struct { 492 u16 TIM_Prescaler; ///< Specifies the prescaler value used to divide the TIM clock. 493 ///< This parameter can be a number between 0x0000 and 0xFFFF 494 TIMCOUNTMODE_Typedef TIM_CounterMode; ///< Specifies the counter mode. 495 ///< This parameter can be a value of @ref TIM_Counter_Mode 496 u32 TIM_Period; ///< Specifies the period value to be loaded into the active 497 ///< Auto-Reload Register at the next update event. 498 ///< This parameter must be a number between 0x0000 and 0xFFFF/0xFFFFFFFF. 499 ///< @note 0xFFFFFFFF is valid only for MM32 32bit Timers: eg.TIM2 or TIM5. 500 TIMCKD_TypeDef TIM_ClockDivision; ///< Specifies the clock division. 501 ///< This parameter can be a value of @ref TIM_Clock_Division_CKD 502 u8 TIM_RepetitionCounter; ///< Specifies the repetition counter value. Each time the RCR downcounter 503 ///< reaches zero, an update event is generated and counting restarts 504 ///< from the RCR value (N). 505 ///< This means in PWM mode that (N+1) corresponds to: 506 ///< - the number of PWM periods in edge-aligned mode 507 ///< - the number of half PWM period in center-aligned mode 508 ///< This parameter must be a number between 0x00 and 0xFF. 509 ///< @note This parameter is valid only for TIM1 and TIM8. 510 } TIM_TimeBaseInitTypeDef; 511 512 //////////////////////////////////////////////////////////////////////////////// 513 /// @brief TIM Output Compare Init structure definition 514 //////////////////////////////////////////////////////////////////////////////// 515 typedef struct { 516 TIMOCMODE_Typedef TIM_OCMode; ///< Specifies the TIM mode. 517 ///< This parameter can be a value of TIM_Output_Compare_and_PWM_modes 518 TIMOUTPUTSTATE_Typedef TIM_OutputState; ///< Specifies the TIM Output Compare state. 519 ///< This parameter can be a value of TIM_Output_Compare_state 520 TIMOUTPUTNSTATE_Typedef TIM_OutputNState; ///< Specifies the TIM complementary Output Compare state. 521 ///< This parameter can be a value of TIM_Output_Compare_N_state 522 ///< @note This parameter is valid only for TIM1 and TIM8. 523 u32 TIM_Pulse; ///< Specifies the pulse value to be loaded into the Capture Compare Register. 524 ///< This parameter can be a number between 0x0000 and 0xFFFF/0xFFFFFFFF 525 ///< @note 0xFFFFFFFF is valid only for MM32 32bit Timers: eg.TIM2 or TIM5. 526 TIMCCxP_Typedef TIM_OCPolarity; ///< Specifies the output polarity. 527 ///< This parameter can be a value of @ref TIM_Output_Compare_Polarity 528 TIMCCxNP_Typedef TIM_OCNPolarity; ///< Specifies the complementary output polarity. 529 ///< This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 530 ///< @note This parameter is valid only for TIM1 and TIM8. 531 TIMOIS_Typedef TIM_OCIdleState; ///< Specifies the TIM Output Compare pin state during Idle state. 532 ///< This parameter can be a value of @ref TIM_Output_Compare_Idle_State 533 ///< @note This parameter is valid only for TIM1 and TIM8. 534 TIMOISN_Typedef TIM_OCNIdleState; ///< Specifies the TIM Output Compare pin state during Idle state. 535 ///< This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 536 ///< @note This parameter is valid only for TIM1 and TIM8. 537 } TIM_OCInitTypeDef; 538 539 //////////////////////////////////////////////////////////////////////////////// 540 /// @brief TIM Input Capture Init structure definition 541 //////////////////////////////////////////////////////////////////////////////// 542 typedef struct { 543 TIMCHx_Typedef TIM_Channel; ///< Specifies the TIM channel. 544 ///< This parameter can be a value of @ref TIM_Channel 545 TIMICP_Typedef TIM_ICPolarity; ///< Specifies the active edge of the input signal. 546 ///< This parameter can be a value of @ref TIM_Input_Capture_Polarity 547 TIMICSEL_Typedef TIM_ICSelection; ///< Specifies the input. 548 ///< This parameter can be a value of @ref TIM_Input_Capture_Selection 549 TIMICPSC_Typedef TIM_ICPrescaler; ///< Specifies the Input Capture Prescaler. 550 ///< This parameter can be a value of @ref TIM_Input_Capture_Prescaler 551 u16 TIM_ICFilter; ///< Specifies the input capture filter. 552 ///< This parameter can be a number between 0x0 and 0xF 553 } TIM_ICInitTypeDef; 554 555 //////////////////////////////////////////////////////////////////////////////// 556 /// @brief BDTR structure definition 557 /// @note This structure is used only with TIM1 and TIM8. 558 //////////////////////////////////////////////////////////////////////////////// 559 typedef struct { 560 TIMOSSR_Typedef TIM_OSSRState; ///< Specifies the Off-State selection used in Run mode. 561 ///< This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state 562 TIMOSSI_Typedef TIM_OSSIState; ///< Specifies the Off-State used in Idle state. 563 ///< This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state 564 TIMLOCKLEVEL_Typedef TIM_LOCKLevel; ///< Specifies the LOCK level parameters. 565 ///< This parameter can be a value of @ref Lock_level 566 u16 TIM_DeadTime; ///< Specifies the delay time between the switching-off and 567 ///< the switching-on of the outputs. 568 ///< This parameter can be a number between 0x00 and 0xFF 569 TIMBKE_Typedef TIM_Break; ///< Specifies whether the TIM Break input is enabled or not. 570 ///< This parameter can be a value of @ref Break_Input_enable_disable 571 TIMBKP_Typedef TIM_BreakPolarity; ///< Specifies the TIM Break Input pin polarity. 572 ///< This parameter can be a value of @ref Break_Polarity 573 TIMAOE_Typedef TIM_AutomaticOutput; ///< Specifies whether the TIM Automatic Output feature is enabled or not. 574 ///< This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset 575 } TIM_BDTRInitTypeDef; 576 /// @} 577 578 //////////////////////////////////////////////////////////////////////////////// 579 /// @defgroup TIM_Exported_Variables 580 /// @{ 581 #ifdef _HAL_TIM_C_ 582 #define GLOBAL 583 584 static void TI1_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter); 585 static void TI2_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter); 586 static void TI3_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter); 587 static void TI4_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter); 588 589 590 #else 591 #define GLOBAL extern 592 #endif 593 594 #undef GLOBAL 595 /// @} 596 597 //////////////////////////////////////////////////////////////////////////////// 598 /// @defgroup TIM_Exported_Functions 599 /// @{ 600 601 //////////////////////////////////////////////////////////////////////////////// 602 //================= TimeBase management ====================================== 603 void TIM_DeInit(TIM_TypeDef* tim); 604 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* init_struct); 605 void TIM_TimeBaseInit(TIM_TypeDef* tim, TIM_TimeBaseInitTypeDef* init_struct); 606 void TIM_PrescalerConfig(TIM_TypeDef* tim, u16 prescaler, TIMUG_Typedef reload_mode); 607 void TIM_CounterModeConfig(TIM_TypeDef* tim, TIMCOUNTMODE_Typedef counter_mode); 608 void TIM_SetCounter(TIM_TypeDef* tim, u32 counter); 609 void TIM_SetAutoreload(TIM_TypeDef* tim, u16 auto_reload); 610 void TIM_UpdateDisableConfig(TIM_TypeDef* tim, FunctionalState state); 611 void TIM_UpdateRequestConfig(TIM_TypeDef* tim, TIMURS_Typedef source); 612 void TIM_ARRPreloadConfig(TIM_TypeDef* tim, FunctionalState state); 613 void TIM_SelectOnePulseMode(TIM_TypeDef* tim, TIMOPMODE_Typedef mode); 614 void TIM_SetClockDivision(TIM_TypeDef* tim, TIMCKD_TypeDef clock_div); 615 void TIM_Cmd(TIM_TypeDef* tim, FunctionalState state); 616 617 u32 TIM_GetCounter(TIM_TypeDef* tim); 618 u16 TIM_GetPrescaler(TIM_TypeDef* tim); 619 620 //================= Advanced-control timers specific features ================ 621 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* init_struct); 622 void TIM_BDTRConfig(TIM_TypeDef* tim, TIM_BDTRInitTypeDef* init_struct); 623 void TIM_CtrlPWMOutputs(TIM_TypeDef* tim, FunctionalState state); 624 625 //================= Output Compare management ================================ 626 void TIM_OCStructInit(TIM_OCInitTypeDef* init_struct); 627 void TIM_OC1Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct); 628 void TIM_OC2Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct); 629 void TIM_OC3Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct); 630 void TIM_OC4Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct); 631 void TIM_SelectOCxM(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMOCMODE_Typedef mode); 632 void TIM_SetCompare1(TIM_TypeDef* tim, u32 compare); 633 void TIM_SetCompare2(TIM_TypeDef* tim, u32 compare); 634 void TIM_SetCompare3(TIM_TypeDef* tim, u32 compare); 635 void TIM_SetCompare4(TIM_TypeDef* tim, u32 compare); 636 void TIM_ForcedOC1Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action); 637 void TIM_ForcedOC2Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action); 638 void TIM_ForcedOC3Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action); 639 void TIM_ForcedOC4Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action); 640 void TIM_CCPreloadControl(TIM_TypeDef* tim, FunctionalState state); 641 void TIM_OC1PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload); 642 void TIM_OC2PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload); 643 void TIM_OC3PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload); 644 void TIM_OC4PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload); 645 void TIM_OC1FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast); 646 void TIM_OC2FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast); 647 void TIM_OC3FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast); 648 void TIM_OC4FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast); 649 void TIM_ClearOC1Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear); 650 void TIM_ClearOC2Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear); 651 void TIM_ClearOC3Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear); 652 void TIM_ClearOC4Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear); 653 void TIM_OC1PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity); 654 void TIM_OC1NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity); 655 void TIM_OC2PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity); 656 void TIM_OC2NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity); 657 void TIM_OC3PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity); 658 void TIM_OC3NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity); 659 void TIM_OC4PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity); 660 void TIM_CCxCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxE_Typedef ccx_en); 661 void TIM_CCxNCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxNE_Typedef ccxn_en); 662 void TIM_SelectCOM(TIM_TypeDef* tim, FunctionalState state); 663 664 //================= Input Capture management ================================= 665 void TIM_ICStructInit(TIM_ICInitTypeDef* init_struct); 666 void TIM_ICInit(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct); 667 void TIM_PWMIConfig(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct); 668 void TIM_SetIC1Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc); 669 void TIM_SetIC2Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc); 670 void TIM_SetIC3Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc); 671 void TIM_SetIC4Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc); 672 673 u32 TIM_GetCapture1(TIM_TypeDef* tim); 674 u32 TIM_GetCapture2(TIM_TypeDef* tim); 675 u32 TIM_GetCapture3(TIM_TypeDef* tim); 676 u32 TIM_GetCapture4(TIM_TypeDef* tim); 677 678 //================= Interrupts, DMA and flags management ===================== 679 void TIM_ITConfig(TIM_TypeDef* tim, u32 it, FunctionalState state);//TIMIT_TypeDef 680 void TIM_GenerateEvent(TIM_TypeDef* tim, TIMEGR_Typedef source); 681 void TIM_ClearFlag(TIM_TypeDef* tim, TIMFLAG_Typedef flag); 682 void TIM_ClearITPendingBit(TIM_TypeDef* tim, u32 it);//TIMIT_TypeDef 683 void TIM_DMAConfig(TIM_TypeDef* tim, TIMDMABASE_Typedef dma_base, TIMDMABURSTLENGTH_Typedef length); 684 void TIM_DMACmd(TIM_TypeDef* tim, TIMDMASRC_Typedef source, FunctionalState state); 685 void TIM_SelectCCDMA(TIM_TypeDef* tim, FunctionalState state); 686 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* tim, TIMFLAG_Typedef flag); 687 ITStatus TIM_GetITStatus(TIM_TypeDef* tim, TIMIT_TypeDef it); 688 689 //================= Clocks management ======================================== 690 void TIM_InternalClockConfig(TIM_TypeDef* tim); 691 void TIM_ITRxExternalClockConfig(TIM_TypeDef* tim, TIMTS_TypeDef source); 692 void TIM_TIxExternalClockConfig(TIM_TypeDef* tim, TIM_TIEXTCLKSRC_Typedef source, TIMICP_Typedef polarity, u16 filter); 693 void TIM_ETRClockMode1Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter); 694 void TIM_ETRClockMode2Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter); 695 696 //================= Synchronization management =============================== 697 void TIM_SelectInputTrigger(TIM_TypeDef* tim, TIMTS_TypeDef source); 698 void TIM_SelectOutputTrigger(TIM_TypeDef* tim, TIMMMS_Typedef source); 699 void TIM_SelectSlaveMode(TIM_TypeDef* tim, TIMSMSMODE_Typedef mode); 700 void TIM_SelectMasterSlaveMode(TIM_TypeDef* tim, TIMMSM_Typedef mode); 701 void TIM_ETRConfig(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter); 702 703 //================= Specific interface management ============================ 704 void TIM_EncoderInterfaceConfig(TIM_TypeDef* tim, 705 TIMSMSENCODER_Typedef encoder_mode, 706 TIMICP_Typedef ic1_polarity, 707 TIMICP_Typedef iC2_polarity); 708 void TIM_SelectHallSensor(TIM_TypeDef* tim, FunctionalState state); 709 710 //================= extend Channel IC management ============================== 711 void TIM_SetIC1Plority(TIM_TypeDef* tim, TIMICP_Typedef pol); 712 void TIM_SetIC2Plority(TIM_TypeDef* tim, TIMICP_Typedef pol); 713 void TIM_SetIC3Plority(TIM_TypeDef* tim, TIMICP_Typedef pol); 714 void TIM_SetIC4Plority(TIM_TypeDef* tim, TIMICP_Typedef pol); 715 716 #define exTIM_SetIC1Plority TIM_SetIC1Plority 717 #define exTIM_SetIC2Plority TIM_SetIC2Plority 718 #define exTIM_SetIC3Plority TIM_SetIC3Plority 719 #define exTIM_SetIC4Plority TIM_SetIC4Plority 720 //================= extend Channel 5 management ============================== 721 722 void TIM_SetCompare5(TIM_TypeDef* tim, u32 compare); 723 void TIM_OC5Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct); 724 void TIM_OC5PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload); 725 void TIM_OC5PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity); 726 void TIM_OC5FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast); 727 void TIM_ClearOC5Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear); 728 u32 TIM_GetCapture5(TIM_TypeDef* tim); 729 730 #define exTIM_SetCompare5 TIM_SetCompare5 731 #define exTIM_OC5Init TIM_OC5Init 732 #define exTIM_OC5PreloadConfig TIM_OC5PreloadConfig 733 #define exTIM_OC5PolarityConfig TIM_OC5PolarityConfig 734 #define exTIM_OC5FastConfig TIM_OC5FastConfig 735 #define exTIM_ClearOC5Ref TIM_ClearOC5Ref 736 #define exTIM_GetCapture5 TIM_GetCapture5 737 738 //============= extend Advanced-control timers specific features ============== 739 void TIM_DirectOutput(TIM_TypeDef* tim, FunctionalState state); 740 #define exTIM_DirectOutput TIM_DirectOutput 741 void TIM_PWMShiftConfig(TIM_TypeDef* tim, u32 it, FunctionalState state); 742 void TIM_SetCCR1FALL(TIM_TypeDef* tim, u32 shift); 743 void TIM_SetCCR2FALL(TIM_TypeDef* tim, u32 shift); 744 void TIM_SetCCR3FALL(TIM_TypeDef* tim, u32 shift); 745 void TIM_SetCCR4FALL(TIM_TypeDef* tim, u32 shift); 746 void TIM_SetCCR5FALL(TIM_TypeDef* tim, u32 shift); 747 /// @} 748 749 /// @} 750 751 /// @} 752 753 //////////////////////////////////////////////////////////////////////////////// 754 #endif // __HAL_TIM_H 755 //////////////////////////////////////////////////////////////////////////////// 756