1 /********************************************************************** 2 * $Id$ lpc177x_8x_uart.h 2011-06-02 3 *//** 4 * @file lpc177x_8x_uart.h 5 * @brief Contains all macro definitions and function prototypes 6 * support for UART firmware library on LPC177x_8x 7 * @version 1.0 8 * @date 02. June. 2011 9 * @author NXP MCU SW Application Team 10 * 11 * Copyright(C) 2011, NXP Semiconductor 12 * All rights reserved. 13 * 14 *********************************************************************** 15 * Software that is described herein is for illustrative purposes only 16 * which provides customers with programming information regarding the 17 * products. This software is supplied "AS IS" without any warranties. 18 * NXP Semiconductors assumes no responsibility or liability for the 19 * use of the software, conveys no license or title under any patent, 20 * copyright, or mask work right to the product. NXP Semiconductors 21 * reserves the right to make changes in the software without 22 * notification. NXP Semiconductors also make no representation or 23 * warranty that such application will be suitable for the specified 24 * use without further testing or modification. 25 **********************************************************************/ 26 27 /* Peripheral group ----------------------------------------------------------- */ 28 /** @defgroup UART UART (Universal Asynchronous Receiver/Transmitter) 29 * @ingroup LPC177x_8xCMSIS_FwLib_Drivers 30 * @{ 31 */ 32 33 #ifndef __LPC177X_8X_UART_H_ 34 #define __LPC177X_8X_UART_H_ 35 36 /* Includes ------------------------------------------------------------------- */ 37 #include "LPC177x_8x.h" 38 #include "lpc_types.h" 39 40 41 #ifdef __cplusplus 42 extern "C" 43 { 44 #endif 45 46 /* Public Macros -------------------------------------------------------------- */ 47 /** @defgroup UART_Public_Macros UART Public Macros 48 * @{ 49 */ 50 51 /** UART time-out definitions in case of using Read() and Write function 52 * with Blocking Flag mode 53 */ 54 #define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL) 55 56 /** 57 * @} 58 */ 59 60 /* Private Macros ------------------------------------------------------------- */ 61 /** @defgroup UART_Private_Macros UART Private Macros 62 * @{ 63 */ 64 65 /* Accepted Error baud rate value (in percent unit) */ 66 #define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */ 67 68 69 /* --------------------- BIT DEFINITIONS -------------------------------------- */ 70 /*********************************************************************//** 71 * Macro defines for Macro defines for UARTn Receiver Buffer Register 72 **********************************************************************/ 73 /** UART Received Buffer mask bit (8 bits) */ 74 #define UART_RBR_MASKBIT ((uint8_t)0xFF) 75 76 /*********************************************************************//** 77 * Macro defines for Macro defines for UARTn Transmit Holding Register 78 **********************************************************************/ 79 /** UART Transmit Holding mask bit (8 bits) */ 80 #define UART_THR_MASKBIT ((uint8_t)0xFF) 81 82 /*********************************************************************//** 83 * Macro defines for Macro defines for UARTn Divisor Latch LSB register 84 **********************************************************************/ 85 /** Macro for loading least significant halfs of divisors */ 86 #define UART_LOAD_DLL(div) ((div) & 0xFF) 87 /** Divisor latch LSB bit mask */ 88 #define UART_DLL_MASKBIT ((uint8_t)0xFF) 89 90 /*********************************************************************//** 91 * Macro defines for Macro defines for UARTn Divisor Latch MSB register 92 **********************************************************************/ 93 /** Divisor latch MSB bit mask */ 94 #define UART_DLM_MASKBIT ((uint8_t)0xFF) 95 /** Macro for loading most significant halfs of divisors */ 96 #define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) 97 98 /*********************************************************************//** 99 * Macro defines for Macro defines for UART interrupt enable register 100 **********************************************************************/ 101 /** RBR Interrupt enable*/ 102 #define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) 103 /** THR Interrupt enable*/ 104 #define UART_IER_THREINT_EN ((uint32_t)(1<<1)) 105 /** RX line status interrupt enable*/ 106 #define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) 107 /** Modem status interrupt enable */ 108 #define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) 109 /** CTS1 signal transition interrupt enable */ 110 #define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) 111 /** Enables the end of auto-baud interrupt */ 112 #define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) 113 /** Enables the auto-baud time-out interrupt */ 114 #define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) 115 /** UART interrupt enable register bit mask */ 116 #define UART_IER_BITMASK ((uint32_t)(0x307)) 117 /** UART1 interrupt enable register bit mask */ 118 #define UART1_IER_BITMASK ((uint32_t)(0x38F)) 119 120 /*********************************************************************//** 121 * Macro defines for Macro defines for UART interrupt identification register 122 **********************************************************************/ 123 /** Interrupt Status - Active low */ 124 #define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) 125 /** Interrupt identification: Receive line status*/ 126 #define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) 127 /** Interrupt identification: Receive data available*/ 128 #define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) 129 /** Interrupt identification: Character time-out indicator*/ 130 #define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) 131 /** Interrupt identification: THRE interrupt*/ 132 #define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) 133 /** Interrupt identification: Modem interrupt*/ 134 #define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) 135 /** Interrupt identification: Interrupt ID mask */ 136 #define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) 137 /** These bits are equivalent to UnFCR[0] */ 138 #define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) 139 /** End of auto-baud interrupt */ 140 #define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) 141 /** Auto-baud time-out interrupt */ 142 #define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) 143 /** UART interrupt identification register bit mask */ 144 #define UART_IIR_BITMASK ((uint32_t)(0x3CF)) 145 146 /*********************************************************************//** 147 * Macro defines for Macro defines for UART FIFO control register 148 **********************************************************************/ 149 /** UART FIFO enable */ 150 #define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) 151 /** UART FIFO RX reset */ 152 #define UART_FCR_RX_RS ((uint8_t)(1<<1)) 153 /** UART FIFO TX reset */ 154 #define UART_FCR_TX_RS ((uint8_t)(1<<2)) 155 /** UART DMA mode selection */ 156 #define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) 157 /** UART FIFO trigger level 0: 1 character */ 158 #define UART_FCR_TRG_LEV0 ((uint8_t)(0)) 159 /** UART FIFO trigger level 1: 4 character */ 160 #define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) 161 /** UART FIFO trigger level 2: 8 character */ 162 #define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) 163 /** UART FIFO trigger level 3: 14 character */ 164 #define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) 165 /** UART FIFO control bit mask */ 166 #define UART_FCR_BITMASK ((uint8_t)(0xCF)) 167 168 #define UART_TX_FIFO_SIZE (16) 169 170 /*********************************************************************//** 171 * Macro defines for Macro defines for UART line control register 172 **********************************************************************/ 173 /** UART 5 bit data mode */ 174 #define UART_LCR_WLEN5 ((uint8_t)(0)) 175 /** UART 6 bit data mode */ 176 #define UART_LCR_WLEN6 ((uint8_t)(1<<0)) 177 /** UART 7 bit data mode */ 178 #define UART_LCR_WLEN7 ((uint8_t)(2<<0)) 179 /** UART 8 bit data mode */ 180 #define UART_LCR_WLEN8 ((uint8_t)(3<<0)) 181 /** UART Two Stop Bits Select */ 182 #define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) 183 /** UART Parity Enable */ 184 #define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) 185 /** UART Odd Parity Select */ 186 #define UART_LCR_PARITY_ODD ((uint8_t)(0)) 187 /** UART Even Parity Select */ 188 #define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) 189 /** UART force 1 stick parity */ 190 #define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) 191 /** UART force 0 stick parity */ 192 #define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) 193 /** UART Transmission Break enable */ 194 #define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) 195 /** UART Divisor Latches Access bit enable */ 196 #define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) 197 /** UART line control bit mask */ 198 #define UART_LCR_BITMASK ((uint8_t)(0xFF)) 199 200 /*********************************************************************//** 201 * Macro defines for Macro defines for UART1 Modem Control Register 202 **********************************************************************/ 203 /** Source for modem output pin DTR */ 204 #define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) 205 /** Source for modem output pin RTS */ 206 #define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) 207 /** Loop back mode select */ 208 #define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) 209 /** Enable Auto RTS flow-control */ 210 #define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) 211 /** Enable Auto CTS flow-control */ 212 #define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) 213 /** UART1 bit mask value */ 214 #define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) 215 216 /*********************************************************************//** 217 * Macro defines for Macro defines for UART line status register 218 **********************************************************************/ 219 /** Line status register: Receive data ready*/ 220 #define UART_LSR_RDR ((uint8_t)(1<<0)) 221 /** Line status register: Overrun error*/ 222 #define UART_LSR_OE ((uint8_t)(1<<1)) 223 /** Line status register: Parity error*/ 224 #define UART_LSR_PE ((uint8_t)(1<<2)) 225 /** Line status register: Framing error*/ 226 #define UART_LSR_FE ((uint8_t)(1<<3)) 227 /** Line status register: Break interrupt*/ 228 #define UART_LSR_BI ((uint8_t)(1<<4)) 229 /** Line status register: Transmit holding register empty*/ 230 #define UART_LSR_THRE ((uint8_t)(1<<5)) 231 /** Line status register: Transmitter empty*/ 232 #define UART_LSR_TEMT ((uint8_t)(1<<6)) 233 /** Error in RX FIFO*/ 234 #define UART_LSR_RXFE ((uint8_t)(1<<7)) 235 /** UART Line status bit mask */ 236 #define UART_LSR_BITMASK ((uint8_t)(0xFF)) 237 238 /*********************************************************************//** 239 * Macro defines for Macro defines for UART Modem (UART1 only) status register 240 **********************************************************************/ 241 /** Set upon state change of input CTS */ 242 #define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) 243 /** Set upon state change of input DSR */ 244 #define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) 245 /** Set upon low to high transition of input RI */ 246 #define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) 247 /** Set upon state change of input DCD */ 248 #define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) 249 /** Clear To Send State */ 250 #define UART1_MSR_CTS ((uint8_t)(1<<4)) 251 /** Data Set Ready State */ 252 #define UART1_MSR_DSR ((uint8_t)(1<<5)) 253 /** Ring Indicator State */ 254 #define UART1_MSR_RI ((uint8_t)(1<<6)) 255 /** Data Carrier Detect State */ 256 #define UART1_MSR_DCD ((uint8_t)(1<<7)) 257 /** MSR register bit-mask value */ 258 #define UART1_MSR_BITMASK ((uint8_t)(0xFF)) 259 260 /*********************************************************************//** 261 * Macro defines for Macro defines for UART Scratch Pad Register 262 **********************************************************************/ 263 /** UART Scratch Pad bit mask */ 264 #define UART_SCR_BIMASK ((uint8_t)(0xFF)) 265 266 /*********************************************************************//** 267 * Macro defines for Macro defines for UART Auto baudrate control register 268 **********************************************************************/ 269 /** UART Auto-baud start */ 270 #define UART_ACR_START ((uint32_t)(1<<0)) 271 /** UART Auto baudrate Mode 1 */ 272 #define UART_ACR_MODE ((uint32_t)(1<<1)) 273 /** UART Auto baudrate restart */ 274 #define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) 275 /** UART End of auto-baud interrupt clear */ 276 #define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) 277 /** UART Auto-baud time-out interrupt clear */ 278 #define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) 279 /** UART Auto Baudrate register bit mask */ 280 #define UART_ACR_BITMASK ((uint32_t)(0x307)) 281 282 /*********************************************************************//** 283 * Macro defines for Macro defines for UART IrDA control register 284 **********************************************************************/ 285 /** IrDA mode enable */ 286 #define UART_ICR_IRDAEN ((uint32_t)(1<<0)) 287 /** IrDA serial input inverted */ 288 #define UART_ICR_IRDAINV ((uint32_t)(1<<1)) 289 /** IrDA fixed pulse width mode */ 290 #define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) 291 /** PulseDiv - Configures the pulse when FixPulseEn = 1 */ 292 #define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) 293 /** UART IRDA bit mask */ 294 #define UART_ICR_BITMASK ((uint32_t)(0x3F)) 295 296 /*********************************************************************//** 297 * Macro defines for Macro defines for UART Fractional divider register 298 **********************************************************************/ 299 /** Baud-rate generation pre-scaler divisor */ 300 #define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) 301 /** Baud-rate pre-scaler multiplier value */ 302 #define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) 303 /** UART Fractional Divider register bit mask */ 304 #define UART_FDR_BITMASK ((uint32_t)(0xFF)) 305 306 /*********************************************************************//** 307 * Macro defines for Macro defines for UART Tx Enable register 308 **********************************************************************/ 309 /** Transmit enable bit */ 310 #define UART_TER_TXEN ((uint8_t)(1<<7)) 311 /** UART Transmit Enable Register bit mask */ 312 #define UART_TER_BITMASK ((uint8_t)(0x80)) 313 314 /*********************************************************************//** 315 * Macro defines for Macro defines for UART1 RS485 Control register 316 **********************************************************************/ 317 /** RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */ 318 #define UART1_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) 319 /** The receiver is disabled */ 320 #define UART1_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) 321 /** Auto Address Detect (AAD) is enabled */ 322 #define UART1_RS485CTRL_AADEN ((uint32_t)(1<<2)) 323 /** If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control */ 324 #define UART1_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) 325 /** Enable Auto Direction Control */ 326 #define UART1_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) 327 /** This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. 328 The direction control pin will be driven to logic "1" when the transmitter has data to be sent */ 329 #define UART1_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) 330 331 /** RS485 control bit-mask value */ 332 #define UART1_RS485CTRL_BITMASK ((uint32_t)(0x3F)) 333 334 /*********************************************************************//** 335 * Macro defines for Macro defines for UART1 RS-485 Address Match register 336 **********************************************************************/ 337 #define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */ 338 339 /*********************************************************************//** 340 * Macro defines for Macro defines for UART1 RS-485 Delay value register 341 **********************************************************************/ 342 /* Macro defines for UART1 RS-485 Delay value register */ 343 #define UART1_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */ 344 345 /*********************************************************************//** 346 * Macro defines for Macro defines for UART FIFO Level register 347 **********************************************************************/ 348 /** Reflects the current level of the UART receiver FIFO */ 349 #define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) 350 /** Reflects the current level of the UART transmitter FIFO */ 351 #define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) 352 /** UART FIFO Level Register bit mask */ 353 #define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) 354 355 356 /** 357 * @} 358 */ 359 360 361 /* Public Types --------------------------------------------------------------- */ 362 /** @defgroup UART_Public_Types UART Public Types 363 * @{ 364 */ 365 366 /** 367 * @brief UART Databit type definitions 368 */ 369 typedef enum { 370 UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */ 371 UART_DATABIT_6, /*!< UART 6 bit data mode */ 372 UART_DATABIT_7, /*!< UART 7 bit data mode */ 373 UART_DATABIT_8 /*!< UART 8 bit data mode */ 374 } UART_DATABIT_Type; 375 376 /** 377 * @brief UART Stop bit type definitions 378 */ 379 typedef enum { 380 UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */ 381 UART_STOPBIT_2, /*!< UART Two Stop Bits Select */ 382 } UART_STOPBIT_Type; 383 384 /** 385 * @brief UART Parity type definitions 386 */ 387 typedef enum { 388 UART_PARITY_NONE = 0, /*!< No parity */ 389 UART_PARITY_ODD, /*!< Odd parity */ 390 UART_PARITY_EVEN, /*!< Even parity */ 391 UART_PARITY_SP_1, /*!< Forced "1" stick parity */ 392 UART_PARITY_SP_0 /*!< Forced "0" stick parity */ 393 } UART_PARITY_Type; 394 395 /** 396 * @brief FIFO Level type definitions 397 */ 398 typedef enum { 399 UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */ 400 UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */ 401 UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */ 402 UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */ 403 } UART_FITO_LEVEL_Type; 404 405 /********************************************************************//** 406 * @brief UART Interrupt Type definitions 407 **********************************************************************/ 408 typedef enum { 409 UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/ 410 UART_INTCFG_THRE, /*!< THR Interrupt enable*/ 411 UART_INTCFG_RLS, /*!< RX line status interrupt enable*/ 412 UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */ 413 UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */ 414 UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */ 415 UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */ 416 } UART_INT_Type; 417 418 /** 419 * @brief UART Line Status Type definition 420 */ 421 typedef enum { 422 UART_LINESTAT_RDR = UART_LSR_RDR, /*!<Line status register: Receive data ready*/ 423 UART_LINESTAT_OE = UART_LSR_OE, /*!<Line status register: Overrun error*/ 424 UART_LINESTAT_PE = UART_LSR_PE, /*!<Line status register: Parity error*/ 425 UART_LINESTAT_FE = UART_LSR_FE, /*!<Line status register: Framing error*/ 426 UART_LINESTAT_BI = UART_LSR_BI, /*!<Line status register: Break interrupt*/ 427 UART_LINESTAT_THRE = UART_LSR_THRE, /*!<Line status register: Transmit holding register empty*/ 428 UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!<Line status register: Transmitter empty*/ 429 UART_LINESTAT_RXFE = UART_LSR_RXFE /*!<Error in RX FIFO*/ 430 } UART_LS_Type; 431 432 /** 433 * @brief UART Auto-baudrate mode type definition 434 */ 435 typedef enum { 436 UART_AUTOBAUD_MODE0 = 0, /**< UART Auto baudrate Mode 0 */ 437 UART_AUTOBAUD_MODE1, /**< UART Auto baudrate Mode 1 */ 438 } UART_AB_MODE_Type; 439 440 /** 441 * @brief Auto Baudrate mode configuration type definition 442 */ 443 typedef struct { 444 UART_AB_MODE_Type ABMode; /**< Autobaudrate mode */ 445 FunctionalState AutoRestart; /**< Auto Restart state */ 446 } UART_AB_CFG_Type; 447 448 /** 449 * @brief UART End of Auto-baudrate type definition 450 */ 451 typedef enum { 452 UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /**< UART End of auto-baud interrupt */ 453 UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /**< UART Auto-baud time-out interrupt */ 454 }UART_ABEO_Type; 455 456 /** 457 * UART IrDA Control type Definition 458 */ 459 typedef enum 460 { 461 /** Pulse width = 2 * Tpclk 462 - Configures the pulse when FixPulseEn = 1 */ 463 UART_IrDA_PULSEDIV2 = 0, 464 465 /** Pulse width = 4 * Tpclk 466 - Configures the pulse when FixPulseEn = 1 */ 467 UART_IrDA_PULSEDIV4, 468 469 /** Pulse width = 8 * Tpclk 470 - Configures the pulse when FixPulseEn = 1 */ 471 UART_IrDA_PULSEDIV8, 472 473 /** Pulse width = 16 * Tpclk 474 - Configures the pulse when FixPulseEn = 1 */ 475 UART_IrDA_PULSEDIV16, 476 477 /** Pulse width = 32 * Tpclk 478 - Configures the pulse when FixPulseEn = 1 */ 479 UART_IrDA_PULSEDIV32, 480 481 /**< Pulse width = 64 * Tpclk 482 - Configures the pulse when FixPulseEn = 1 */ 483 UART_IrDA_PULSEDIV64, 484 485 /**< Pulse width = 128 * Tpclk 486 - Configures the pulse when FixPulseEn = 1 */ 487 UART_IrDA_PULSEDIV128, 488 489 /**< Pulse width = 256 * Tpclk 490 - Configures the pulse when FixPulseEn = 1 */ 491 UART_IrDA_PULSEDIV256 492 } UART_IrDA_PULSE_Type; 493 494 /********************************************************************//** 495 * @brief UART1 Full modem - Signal states definition 496 **********************************************************************/ 497 typedef enum { 498 INACTIVE = 0, /* In-active state */ 499 ACTIVE = !INACTIVE /* Active state */ 500 }UART1_SignalState; 501 502 /** 503 * @brief UART modem status type definition 504 */ 505 typedef enum { 506 UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */ 507 UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */ 508 UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */ 509 UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */ 510 UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /*!< Clear To Send State */ 511 UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /*!< Data Set Ready State */ 512 UART1_MODEM_STAT_RI = UART1_MSR_RI, /*!< Ring Indicator State */ 513 UART1_MODEM_STAT_DCD = UART1_MSR_DCD /*!< Data Carrier Detect State */ 514 } UART_MODEM_STAT_type; 515 516 /** 517 * @brief Modem output pin type definition 518 */ 519 typedef enum { 520 UART1_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */ 521 UART1_MODEM_PIN_RTS /*!< Source for modem output pin RTS */ 522 } UART_MODEM_PIN_Type; 523 524 /** 525 * @brief UART Modem mode type definition 526 */ 527 typedef enum { 528 UART1_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */ 529 UART1_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */ 530 UART1_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */ 531 } UART_MODEM_MODE_Type; 532 533 /** 534 * @brief UART Direction Control Pin type definition 535 */ 536 typedef enum { 537 UART1_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */ 538 UART1_RS485_DIRCTRL_DTR /**< Pin DTR is used for direction control */ 539 } UART_RS485_DIRCTRL_PIN_Type; 540 541 /********************************************************************//** 542 * @brief UART Configuration Structure definition 543 **********************************************************************/ 544 typedef struct { 545 uint32_t Baud_rate; /**< UART baud rate */ 546 UART_PARITY_Type Parity; /**< Parity selection, should be: 547 - UART_PARITY_NONE: No parity 548 - UART_PARITY_ODD: Odd parity 549 - UART_PARITY_EVEN: Even parity 550 - UART_PARITY_SP_1: Forced "1" stick parity 551 - UART_PARITY_SP_0: Forced "0" stick parity 552 */ 553 UART_DATABIT_Type Databits; /**< Number of data bits, should be: 554 - UART_DATABIT_5: UART 5 bit data mode 555 - UART_DATABIT_6: UART 6 bit data mode 556 - UART_DATABIT_7: UART 7 bit data mode 557 - UART_DATABIT_8: UART 8 bit data mode 558 */ 559 UART_STOPBIT_Type Stopbits; /**< Number of stop bits, should be: 560 - UART_STOPBIT_1: UART 1 Stop Bits Select 561 - UART_STOPBIT_2: UART 2 Stop Bits Select 562 */ 563 } UART_CFG_Type; 564 565 /********************************************************************//** 566 * @brief UART FIFO Configuration Structure definition 567 **********************************************************************/ 568 569 typedef struct { 570 FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be: 571 - ENABLE: Reset Rx FIFO in UART 572 - DISABLE: Do not reset Rx FIFO in UART 573 */ 574 FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be: 575 - ENABLE: Reset Tx FIFO in UART 576 - DISABLE: Do not reset Tx FIFO in UART 577 */ 578 FunctionalState FIFO_DMAMode; /**< DMA mode, should be: 579 - ENABLE: Enable DMA mode in UART 580 - DISABLE: Disable DMA mode in UART 581 */ 582 UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be: 583 - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character 584 - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character 585 - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character 586 - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character 587 */ 588 } UART_FIFO_CFG_Type; 589 590 /********************************************************************//** 591 * @brief UART1 Full modem - RS485 Control configuration type 592 **********************************************************************/ 593 typedef struct { 594 FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State: 595 - ENABLE: Enable this function. 596 - DISABLE: Disable this function. */ 597 FunctionalState Rx_State; /*!< Receiver State: 598 - ENABLE: Enable Receiver. 599 - DISABLE: Disable Receiver. */ 600 FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state: 601 - ENABLE: ENABLE this function. 602 - DISABLE: Disable this function. */ 603 FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State: 604 - ENABLE: Enable this function. 605 - DISABLE: Disable this function. */ 606 UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state: 607 - UART1_RS485_DIRCTRL_RTS: 608 pin RTS is used for direction control. 609 - UART1_RS485_DIRCTRL_DTR: 610 pin DTR is used for direction control. */ 611 SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on 612 the RTS (or DTR) pin: 613 - RESET: The direction control pin will be driven 614 to logic "0" when the transmitter has data to be sent. 615 - SET: The direction control pin will be driven 616 to logic "1" when the transmitter has data to be sent. */ 617 uint8_t MatchAddrValue; /*!< address match value for RS-485/EIA-485 mode, 8-bit long */ 618 uint8_t DelayValue; /*!< delay time is in periods of the baud clock, 8-bit long */ 619 } UART1_RS485_CTRLCFG_Type; 620 621 /** 622 * @} 623 */ 624 625 626 /* Public Functions ----------------------------------------------------------- */ 627 /** @defgroup UART_Public_Functions UART Public Functions 628 * @{ 629 */ 630 /* UART Init/DeInit functions --------------------------------------------------*/ 631 void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct); 632 void UART_DeInit(LPC_UART_TypeDef* UARTx); 633 void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct); 634 635 /* UART Send/Receive functions -------------------------------------------------*/ 636 void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data); 637 uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx); 638 uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf, 639 uint32_t buflen, TRANSFER_BLOCK_Type flag); 640 uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \ 641 uint32_t buflen, TRANSFER_BLOCK_Type flag); 642 643 /* UART FIFO functions ----------------------------------------------------------*/ 644 void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg); 645 void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct); 646 647 /* UART get information functions -----------------------------------------------*/ 648 uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx); 649 uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx); 650 651 /* UART operate functions -------------------------------------------------------*/ 652 void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, \ 653 FunctionalState NewState); 654 void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState); 655 FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx); 656 void UART_ForceBreak(LPC_UART_TypeDef* UARTx); 657 658 /* UART Auto-baud functions -----------------------------------------------------*/ 659 void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType); 660 void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \ 661 FunctionalState NewState); 662 663 /* UART1 FullModem functions ----------------------------------------------------*/ 664 void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \ 665 UART1_SignalState NewState); 666 void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \ 667 FunctionalState NewState); 668 uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx); 669 670 /* UART RS485 functions ----------------------------------------------------------*/ 671 void UART_RS485Config(LPC_UART_TypeDef *UARTx, 672 UART1_RS485_CTRLCFG_Type *RS485ConfigStruct); 673 void UART_RS485ReceiverCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState); 674 void UART_RS485SendSlvAddr(LPC_UART_TypeDef *UARTx, uint8_t SlvAddr); 675 uint32_t UART_RS485SendData(LPC_UART_TypeDef *UARTx, uint8_t *pData, uint32_t size); 676 677 /* UART IrDA functions-------------------------------------------------------------*/ 678 void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState); 679 void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState); 680 void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv); 681 /** 682 * @} 683 */ 684 685 686 #ifdef __cplusplus 687 } 688 #endif 689 690 691 #endif /* __LPC177X_8X_UART_H_ */ 692 693 /** 694 * @} 695 */ 696 697 /* --------------------------------- End Of File ------------------------------ */ 698