1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2024-08-30 shelton first version 9 */ 10 11 #ifndef __DMA_CONFIG_H__ 12 #define __DMA_CONFIG_H__ 13 14 #include <rtthread.h> 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 /* DMA1 channel1 */ 21 #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL) 22 #define SPI1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler 23 #define SPI1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 24 #define SPI1_RX_DMA_CHANNEL DMA1_CHANNEL1 25 #define SPI1_RX_DMA_IRQ DMA1_Channel1_IRQn 26 #define SPI1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 27 #define SPI1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_SPI1_RX 28 #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL) 29 #define UART1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler 30 #define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 31 #define UART1_RX_DMA_CHANNEL DMA1_CHANNEL1 32 #define UART1_RX_DMA_IRQ DMA1_Channel1_IRQn 33 #define UART1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 34 #define UART1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_RX 35 #endif 36 37 /* DMA1 channel2 */ 38 #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL) 39 #define SPI1_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler 40 #define SPI1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 41 #define SPI1_TX_DMA_CHANNEL DMA1_CHANNEL2 42 #define SPI1_TX_DMA_IRQ DMA1_Channel2_IRQn 43 #define SPI1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 44 #define SPI1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_SPI1_TX 45 #elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_CHANNEL) 46 #define UART1_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler 47 #define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 48 #define UART1_TX_DMA_CHANNEL DMA1_CHANNEL2 49 #define UART1_TX_DMA_IRQ DMA1_Channel2_IRQn 50 #define UART1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 51 #define UART1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_TX 52 #endif 53 54 /* DMA1 channel3 */ 55 #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL) 56 #define SPI2_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler 57 #define SPI2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 58 #define SPI2_RX_DMA_CHANNEL DMA1_CHANNEL3 59 #define SPI2_RX_DMA_IRQ DMA1_Channel3_IRQn 60 #define SPI2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3 61 #define SPI2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_SPI2_RX 62 #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL) 63 #define I2C1_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler 64 #define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 65 #define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL3 66 #define I2C1_RX_DMA_IRQ DMA1_Channel3_IRQn 67 #define I2C1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1 68 #define I2C1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_RX 69 #endif 70 71 /* DMA1 channel4 */ 72 #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL) 73 #define SPI2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler 74 #define SPI2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 75 #define SPI2_TX_DMA_CHANNEL DMA1_CHANNEL4 76 #define SPI2_TX_DMA_IRQ DMA1_Channel4_IRQn 77 #define SPI2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4 78 #define SPI2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_SPI2_TX 79 #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL) 80 #define I2C1_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler 81 #define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 82 #define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL4 83 #define I2C1_TX_DMA_IRQ DMA1_Channel4_IRQn 84 #define I2C1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2 85 #define I2C1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_TX 86 #endif 87 88 /* DMA1 channel5 */ 89 #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL) 90 #define UART2_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler 91 #define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 92 #define UART2_RX_DMA_CHANNEL DMA1_CHANNEL5 93 #define UART2_RX_DMA_IRQ DMA1_Channel5_IRQn 94 #define UART2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 95 #define UART2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_RX 96 #elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL) 97 #define I2C2_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler 98 #define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 99 #define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL5 100 #define I2C2_RX_DMA_IRQ DMA1_Channel5_IRQn 101 #define I2C2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5 102 #define I2C2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_RX 103 #endif 104 105 /* DMA1 channel6 */ 106 #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_CHANNEL) 107 #define UART2_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler 108 #define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 109 #define UART2_TX_DMA_CHANNEL DMA1_CHANNEL6 110 #define UART2_TX_DMA_IRQ DMA1_Channel6_IRQn 111 #define UART2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 112 #define UART2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_TX 113 #elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL) 114 #define I2C2_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler 115 #define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK 116 #define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL6 117 #define I2C2_TX_DMA_IRQ DMA1_Channel6_IRQn 118 #define I2C2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6 119 #define I2C2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_TX 120 #endif 121 122 #ifdef __cplusplus 123 } 124 #endif 125 126 #endif /* __DMA_CONFIG_H__ */ 127