1 /* 2 * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2024-02-20 CDT first version 9 */ 10 11 #ifndef __DMA_CONFIG_H__ 12 #define __DMA_CONFIG_H__ 13 14 #include <rtthread.h> 15 #include "irq_config.h" 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 /* DMA1 ch0 */ 22 #if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) 23 #define UART1_TX_DMA_INSTANCE CM_DMA 24 #define UART1_TX_DMA_CHANNEL DMA_CH0 25 #define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) 26 #define UART1_TX_DMA_TRIG_SELECT AOS_DMA_0 27 #define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 28 #define UART1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM 29 #define UART1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO 30 #define UART1_TX_DMA_INT_SRC INT_SRC_DMA_TC0 31 32 #elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) 33 #define SPI1_TX_DMA_INSTANCE CM_DMA 34 #define SPI1_TX_DMA_CHANNEL DMA_CH0 35 #define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) 36 #define SPI1_TX_DMA_TRIG_SELECT AOS_DMA_0 37 #define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 38 #define SPI1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM 39 #define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO 40 #define SPI1_TX_DMA_INT_SRC INT_SRC_DMA_TC0 41 #endif 42 43 /* DMA1 ch1 */ 44 #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) 45 #define UART1_RX_DMA_INSTANCE CM_DMA 46 #define UART1_RX_DMA_CHANNEL DMA_CH1 47 #define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) 48 #define UART1_RX_DMA_TRIG_SELECT AOS_DMA_1 49 #define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 50 #define UART1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM 51 #define UART1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO 52 #define UART1_RX_DMA_INT_SRC INT_SRC_DMA_TC1 53 54 #elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) 55 #define SPI1_RX_DMA_INSTANCE CM_DMA 56 #define SPI1_RX_DMA_CHANNEL DMA_CH1 57 #define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) 58 #define SPI1_RX_DMA_TRIG_SELECT AOS_DMA_1 59 #define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 60 #define SPI1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM 61 #define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO 62 #define SPI1_RX_DMA_INT_SRC INT_SRC_DMA_TC1 63 #endif 64 65 /* DMA1 ch2 */ 66 #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) 67 #define UART2_TX_DMA_INSTANCE CM_DMA 68 #define UART2_TX_DMA_CHANNEL DMA_CH2 69 #define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) 70 #define UART2_TX_DMA_TRIG_SELECT AOS_DMA_2 71 #define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 72 #define UART2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM 73 #define UART2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO 74 #define UART2_TX_DMA_INT_SRC INT_SRC_DMA_TC2 75 76 #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) 77 #define I2C1_TX_DMA_INSTANCE CM_DMA 78 #define I2C1_TX_DMA_CHANNEL DMA_CH2 79 #define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) 80 #define I2C1_TX_DMA_TRIG_SELECT AOS_DMA_2 81 #define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 82 #define I2C1_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM 83 #define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO 84 #define I2C1_TX_DMA_INT_SRC INT_SRC_DMA_TC2 85 #endif 86 87 /* DMA1 ch3 */ 88 #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) 89 #define UART2_RX_DMA_INSTANCE CM_DMA 90 #define UART2_RX_DMA_CHANNEL DMA_CH3 91 #define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) 92 #define UART2_RX_DMA_TRIG_SELECT AOS_DMA_3 93 #define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 94 #define UART2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM 95 #define UART2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO 96 #define UART2_RX_DMA_INT_SRC INT_SRC_DMA_TC3 97 98 #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) 99 #define I2C1_RX_DMA_INSTANCE CM_DMA 100 #define I2C1_RX_DMA_CHANNEL DMA_CH3 101 #define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) 102 #define I2C1_RX_DMA_TRIG_SELECT AOS_DMA_3 103 #define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 104 #define I2C1_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM 105 #define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO 106 #define I2C1_RX_DMA_INT_SRC INT_SRC_DMA_TC3 107 #endif 108 109 /* DMA1 ch4 */ 110 #if defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE) 111 #define UART3_TX_DMA_INSTANCE CM_DMA 112 #define UART3_TX_DMA_CHANNEL DMA_CH4 113 #define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) 114 #define UART3_TX_DMA_TRIG_SELECT AOS_DMA_4 115 #define UART3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 116 #define UART3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM 117 #define UART3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO 118 #define UART3_TX_DMA_INT_SRC INT_SRC_DMA_TC4 119 120 #elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE) 121 #define ADC1_EOCA_DMA_INSTANCE CM_DMA 122 #define ADC1_EOCA_DMA_CHANNEL DMA_CH4 123 #define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) 124 #define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA_4 125 #define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 126 #define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM 127 #define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO 128 #define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA_TC4 129 #endif 130 131 /* DMA1 ch5 */ 132 #if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) 133 #define UART3_RX_DMA_INSTANCE CM_DMA 134 #define UART3_RX_DMA_CHANNEL DMA_CH5 135 #define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) 136 #define UART3_RX_DMA_TRIG_SELECT AOS_DMA_5 137 #define UART3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 138 #define UART3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM 139 #define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO 140 #define UART3_RX_DMA_INT_SRC INT_SRC_DMA_TC5 141 142 #elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE) 143 #define ADC2_EOCA_DMA_INSTANCE CM_DMA 144 #define ADC2_EOCA_DMA_CHANNEL DMA_CH5 145 #define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) 146 #define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA_5 147 #define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 148 #define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM 149 #define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO 150 #define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA_TC5 151 #endif 152 153 /* DMA1 ch6 */ 154 #if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) 155 #define UART4_TX_DMA_INSTANCE CM_DMA 156 #define UART4_TX_DMA_CHANNEL DMA_CH6 157 #define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) 158 #define UART4_TX_DMA_TRIG_SELECT AOS_DMA_6 159 #define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 160 #define UART4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM 161 #define UART4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO 162 #define UART4_TX_DMA_INT_SRC INT_SRC_DMA_TC6 163 164 #elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE) 165 #define ADC3_EOCA_DMA_INSTANCE CM_DMA 166 #define ADC3_EOCA_DMA_CHANNEL DMA_CH6 167 #define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) 168 #define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA_6 169 #define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 170 #define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM 171 #define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO 172 #define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA_TC6 173 #endif 174 175 /* DMA1 ch7 */ 176 #if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) 177 #define UART4_RX_DMA_INSTANCE CM_DMA 178 #define UART4_RX_DMA_CHANNEL DMA_CH7 179 #define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) 180 #define UART4_RX_DMA_TRIG_SELECT AOS_DMA_7 181 #define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 182 #define UART4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM 183 #define UART4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO 184 #define UART4_RX_DMA_INT_SRC INT_SRC_DMA_TC7 185 #endif 186 187 #ifdef __cplusplus 188 } 189 #endif 190 191 #endif /* __DMA_CONFIG_H__ */ 192