1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_uart.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_UART_H 22 #define __REG_UART_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 40 41 42 43 44 45 46 //////////////////////////////////////////////////////////////////////////////// 47 /// @brief UART Base Address Definition 48 //////////////////////////////////////////////////////////////////////////////// 49 #define UART1_BASE (APB2PERIPH_BASE + 0x3800) ///< Base Address: 0x40013800 50 #define UART2_BASE (APB1PERIPH_BASE + 0x4400) ///< Base Address: 0x40004400 51 #define UART3_BASE (APB1PERIPH_BASE + 0x4800) ///< Base Address: 0x40004800 52 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) ///< Base Address: 0x40004C00 53 #define UART5_BASE (APB1PERIPH_BASE + 0x5000) ///< Base Address: 0x40005000 54 #define UART6_BASE (APB2PERIPH_BASE + 0x3C00) ///< Base Address: 0x40013C00 55 #define UART7_BASE (APB1PERIPH_BASE + 0x7800) ///< Base Address: 0x40007800 56 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00) ///< Base Address: 0x40007C00 57 58 59 60 61 62 63 64 //////////////////////////////////////////////////////////////////////////////// 65 /// @brief UART Register Structure Definition 66 //////////////////////////////////////////////////////////////////////////////// 67 typedef struct { 68 __IO u32 TDR; ///< Transmit Data Register, offset: 0x00 69 __IO u32 RDR; ///< Receive Data Register, offset: 0x04 70 __IO u32 CSR; ///< Current Status Register, offset: 0x08 71 __IO u32 ISR; ///< Interrupt Status Register, offset: 0x0C 72 __IO u32 IER; ///< Interrupt Enable Register, offset: 0x10 73 __IO u32 ICR; ///< Interrupt Clear Register, offset: 0x14 74 __IO u32 GCR; ///< Global Control Register, offset: 0x18 75 __IO u32 CCR; ///< Config Control Register, offset: 0x1C 76 __IO u32 BRR; ///< Baud Rate Register, offset: 0x20 77 __IO u32 FRA; ///< Fraction Register, offset: 0x24 78 79 __IO u32 RXAR; ///< Receive Address Register, offset: 0x28 80 __IO u32 RXMR; ///< Receive Address Mask Register, offset: 0x2C 81 __IO u32 SCR; ///< Smart Card Register, offset: 0x30 82 83 __IO u32 IDLR; ///< Data length register offset: 0x34 84 __IO u32 ABRCR; ///< automatic Baud rate control delivery offset: 0x38 85 __IO u32 IRDA; ///< Infrared function control register, offset: 0x3C 86 } UART_TypeDef; 87 88 89 //////////////////////////////////////////////////////////////////////////////// 90 /// @brief UART type pointer Definition 91 //////////////////////////////////////////////////////////////////////////////// 92 #define UART1 ((UART_TypeDef*) UART1_BASE) 93 #define UART2 ((UART_TypeDef*) UART2_BASE) 94 95 #define UART3 ((UART_TypeDef*) UART3_BASE) 96 #define UART4 ((UART_TypeDef*) UART4_BASE) 97 #define UART5 ((UART_TypeDef*) UART5_BASE) 98 #define UART6 ((UART_TypeDef*) UART6_BASE) 99 #define UART7 ((UART_TypeDef*) UART7_BASE) 100 #define UART8 ((UART_TypeDef*) UART8_BASE) 101 102 103 //////////////////////////////////////////////////////////////////////////////// 104 /// @brief UART_TDR Register Bit Definition 105 //////////////////////////////////////////////////////////////////////////////// 106 #define UART_TDR_DATA_Pos (0) 107 #define UART_TDR_DATA (0xFFU << UART_TDR_DATA_Pos) ///< Transmit data register 108 109 //////////////////////////////////////////////////////////////////////////////// 110 /// @brief UART_RDR Register Bit Definition 111 //////////////////////////////////////////////////////////////////////////////// 112 #define UART_RDR_DATA_Pos (0) 113 #define UART_RDR_DATA (0xFFU << UART_RDR_DATA_Pos) ///< Receive data register 114 115 //////////////////////////////////////////////////////////////////////////////// 116 /// @brief UART_CSR Register Bit Definition 117 //////////////////////////////////////////////////////////////////////////////// 118 #define UART_CSR_TXC_Pos (0) 119 #define UART_CSR_TXC (0x01U << UART_CSR_TXC_Pos) ///< Transmit complete flag bit 120 #define UART_CSR_RXAVL_Pos (1) 121 #define UART_CSR_RXAVL (0x01U << UART_CSR_RXAVL_Pos) ///< Receive valid data flag bit 122 #define UART_CSR_TXFULL_Pos (2) 123 #define UART_CSR_TXFULL (0x01U << UART_CSR_TXFULL_Pos) ///< Transmit buffer full flag bit 124 #define UART_CSR_TXEPT_Pos (3) 125 #define UART_CSR_TXEPT (0x01U << UART_CSR_TXEPT_Pos) ///< Transmit buffer empty flag bit 126 127 //////////////////////////////////////////////////////////////////////////////// 128 /// @brief UART_ISR Register Bit Definition 129 //////////////////////////////////////////////////////////////////////////////// 130 #define UART_ISR_TX_Pos (0) 131 #define UART_ISR_TX (0x01U << UART_ISR_TX_Pos) ///< Transmit buffer empty interrupt flag bit 132 #define UART_ISR_RX_Pos (1) 133 #define UART_ISR_RX (0x01U << UART_ISR_RX_Pos) ///< Receive valid data interrupt flag bit 134 135 #define UART_ISR_TXC_Pos (2) 136 #define UART_ISR_TXC (0x01U << UART_ISR_TXC_Pos) ///< Transmit complete interrupt flag bit 137 138 #define UART_ISR_RXOERR_Pos (3) 139 #define UART_ISR_RXOERR (0x01U << UART_ISR_RXOERR_Pos) ///< Receive overflow error interrupt flag bit 140 #define UART_ISR_RXPERR_Pos (4) 141 #define UART_ISR_RXPERR (0x01U << UART_ISR_RXPERR_Pos) ///< Parity error interrupt flag bit 142 #define UART_ISR_RXFERR_Pos (5) 143 #define UART_ISR_RXFERR (0x01U << UART_ISR_RXFERR_Pos) ///< Frame error interrupt flag bit 144 #define UART_ISR_RXBRK_Pos (6) 145 #define UART_ISR_RXBRK (0x01U << UART_ISR_RXBRK_Pos) ///< Receive frame break interrupt flag bit 146 147 #define UART_ISR_TXBRK_Pos (7) 148 #define UART_ISR_TXBRK (0x01U << UART_ISR_TXBRK_Pos) ///< Transmit Break Frame Interrupt Flag Bit 149 #define UART_ISR_RXB8_Pos (8) 150 #define UART_ISR_RXB8 (0x01U << UART_ISR_RXB8_Pos) ///< Receive Bit 8 Interrupt Flag Bit 151 152 #define UART_ISR_RXIDLE_Pos (9) 153 #define UART_ISR_RXIDLE (0x01U << UART_ISR_RXIDLE_Pos) ///< Receive Bit 8 Interrupt clear Bit 154 #define UART_ISR_ABREND_INTF_Pos (10) 155 #define UART_ISR_ABREND_INTF (0x01U << UART_ISR_ABREND_INTF_Pos) ///< Auto baud rate end interrupt flag bit 156 #define UART_ISR_ABRERR_INTF_Pos (11) 157 #define UART_ISR_ABRERR_INTF (0x01U << UART_ISR_ABRERR_INTF_Pos) ///< Auto baud rate error interrupt flag bit 158 159 //////////////////////////////////////////////////////////////////////////////// 160 /// @brief UART_IER Register Bit Definition 161 //////////////////////////////////////////////////////////////////////////////// 162 #define UART_IER_TX_Pos (0) 163 #define UART_IER_TX (0x01U << UART_IER_TX_Pos) ///< Transmit buffer empty interrupt enable bit 164 #define UART_IER_RX_Pos (1) 165 #define UART_IER_RX (0x01U << UART_IER_RX_Pos) ///< Receive buffer interrupt enable bit 166 167 #define UART_IER_TXC_Pos (2) 168 #define UART_IER_TXC (0x01U << UART_IER_TXC_Pos) ///< Transmit complete interrupt enable bit 169 170 #define UART_IER_RXOERR_Pos (3) 171 #define UART_IER_RXOERR (0x01U << UART_IER_RXOERR_Pos) ///< Receive overflow error interrupt enable bit 172 #define UART_IER_RXPERR_Pos (4) 173 #define UART_IER_RXPERR (0x01U << UART_IER_RXPERR_Pos) ///< Parity error interrupt enable bit 174 #define UART_IER_RXFERR_Pos (5) 175 #define UART_IER_RXFERR (0x01U << UART_IER_RXFERR_Pos) ///< Frame error interrupt enable bit 176 #define UART_IER_RXBRK_Pos (6) 177 #define UART_IER_RXBRK (0x01U << UART_IER_RXBRK_Pos) ///< Receive frame break interrupt enable bit 178 179 #define UART_IER_TXBRK_Pos (7) 180 #define UART_IER_TXBRK (0x01U << UART_IER_TXBRK_Pos) ///< Transmit Break Frame Interrupt Enable Bit 181 #define UART_IER_RXB8_Pos (8) 182 #define UART_IER_RXB8 (0x01U << UART_IER_RXB8_Pos) ///< Receive Bit 8 Interrupt Enable Bit 183 184 #define UART_IER_RXIDLE_Pos (9) 185 #define UART_IER_RXIDLE (0x01U << UART_IER_RXIDLE_Pos) ///< Receive Bit 8 Interrupt clear Bit 186 #define UART_IER_ABREND_IEN_Pos (10) 187 #define UART_IER_ABREND_IEN (0x01U << UART_IER_ABREND_IEN_Pos) ///< Auto baud rate end enable bit 188 #define UART_IER_ABRERR_IEN_Pos (11) 189 #define UART_IER_ABRERR_IEN (0x01U << UART_IER_ABRERR_IEN_Pos) ///< Auto baud rate error enable bit 190 191 //////////////////////////////////////////////////////////////////////////////// 192 /// @brief UART_ICR Register Bit Definition 193 //////////////////////////////////////////////////////////////////////////////// 194 195 #define UART_ICR_TX_Pos (0) 196 #define UART_ICR_TX (0x01U << UART_ICR_TX_Pos) ///< Transmit buffer empty interrupt clear bit 197 #define UART_ICR_RX_Pos (1) 198 #define UART_ICR_RX (0x01U << UART_ICR_RX_Pos) ///< Receive interrupt clear bit 199 200 #define UART_ICR_TXC_Pos (2) 201 #define UART_ICR_TXC (0x01U << UART_ICR_TXC_Pos) ///< Transmit complete interrupt clear bit 202 203 #define UART_ICR_RXOERR_Pos (3) 204 #define UART_ICR_RXOERR (0x01U << UART_ICR_RXOERR_Pos) ///< Receive overflow error interrupt clear bit 205 #define UART_ICR_RXPERR_Pos (4) 206 #define UART_ICR_RXPERR (0x01U << UART_ICR_RXPERR_Pos) ///< Parity error interrupt clear bit 207 208 #define UART_ICR_RXFERR_Pos (5) 209 #define UART_ICR_RXFERR (0x01U << UART_ICR_RXFERR_Pos) ///< Frame error interrupt clear bit 210 #define UART_ICR_RXBRK_Pos (6) 211 #define UART_ICR_RXBRK (0x01U << UART_ICR_RXBRK_Pos) ///< Receive frame break interrupt clear bit 212 213 #define UART_ICR_TXBRK_Pos (7) 214 #define UART_ICR_TXBRK (0x01U << UART_ICR_TXBRK_Pos) ///< Transmit Break Frame Interrupt clear Bit 215 #define UART_ICR_RXB8_Pos (8) 216 #define UART_ICR_RXB8 (0x01U << UART_ICR_RXB8_Pos) ///< Receive Bit 8 Interrupt clear Bit 217 218 #define UART_ICR_RXIDLE_Pos (9) 219 #define UART_ICR_RXIDLE (0x01U << UART_ICR_RXIDLE_Pos) ///< Receive Bit 8 Interrupt clear Bit 220 #define UART_ICR_ABRENDCLR_Pos (10) 221 #define UART_ICR_ABRENDCLR (0x01U << UART_ICR_ABRENDCLR_Pos) ///< Auto baud rate end clear bit 222 #define UART_ICR_ABRERRCLR_Pos (11) 223 #define UART_ICR_ABRERRCLR (0x01U << UART_ICR_ABRERRCLR_Pos) ///< Auto baud rate error clear bit 224 225 //////////////////////////////////////////////////////////////////////////////// 226 /// @brief UART_GCR Register Bit Definition 227 //////////////////////////////////////////////////////////////////////////////// 228 #define UART_GCR_UART_Pos (0) 229 #define UART_GCR_UART (0x01U << UART_GCR_UART_Pos) ///< UART mode selection bit 230 #define UART_GCR_DMA_Pos (1) 231 #define UART_GCR_DMA (0x01U << UART_GCR_DMA_Pos) ///< DMA mode selection bit 232 #define UART_GCR_AUTOFLOW_Pos (2) 233 #define UART_GCR_AUTOFLOW (0x01U << UART_GCR_AUTOFLOW_Pos) ///< Automatic flow control enable bit 234 #define UART_GCR_RX_Pos (3) 235 #define UART_GCR_RX (0x01U << UART_GCR_RX_Pos) ///< Enable receive 236 #define UART_GCR_TX_Pos (4) 237 #define UART_GCR_TX (0x01U << UART_GCR_TX_Pos) ///< Enable transmit 238 239 #define UART_GCR_SELB8_Pos (7) 240 #define UART_GCR_SELB8 (0x01U << UART_GCR_SELB8_Pos) ///< UART mode selection bit 241 #define UART_GCR_SWAP_Pos (8) 242 #define UART_GCR_SWAP (0x01U << UART_GCR_SWAP_Pos) ///< DMA mode selection bit 243 #define UART_GCR_RXTOG_Pos (9) 244 #define UART_GCR_RXTOG (0x01U << UART_GCR_RXTOG_Pos) ///< Automatic flow control enable bit 245 #define UART_GCR_TXTOG_Pos (10) 246 #define UART_GCR_TXTOG (0x01U << UART_GCR_TXTOG_Pos) ///< Enable receive 247 248 //////////////////////////////////////////////////////////////////////////////// 249 /// @brief UART_CCR Register Bit Definition 250 //////////////////////////////////////////////////////////////////////////////// 251 #define UART_CCR_PEN_Pos (0) 252 #define UART_CCR_PEN (0x01U << UART_CCR_PEN_Pos) ///< Parity enable bit 253 #define UART_CCR_PSEL_Pos (1) 254 #define UART_CCR_PSEL (0x01U << UART_CCR_PSEL_Pos) ///< Parity selection bit 255 256 #define UART_CCR_SPB_Pos (2) 257 #define UART_CCR_SPB (0x01U << UART_CCR_SPB_Pos) ///< Stop bit selection 258 259 260 261 #define UART_CCR_SPB0_Pos UART_CCR_SPB_Pos 262 #define UART_CCR_SPB0 UART_CCR_SPB ///< Stop bit 0 selection 263 264 #define UART_CCR_BRK_Pos (3) 265 #define UART_CCR_BRK (0x01U << UART_CCR_BRK_Pos) ///< UART transmit frame break 266 #define UART_CCR_CHAR_Pos (4) 267 #define UART_CCR_CHAR (0x03U << UART_CCR_CHAR_Pos) ///< UART width bit 268 #define UART_CCR_CHAR_5b (0x00U << UART_CCR_CHAR_Pos) ///< UART Word Length 5b 269 #define UART_CCR_CHAR_6b (0x01U << UART_CCR_CHAR_Pos) ///< UART Word Length 6b 270 #define UART_CCR_CHAR_7b (0x02U << UART_CCR_CHAR_Pos) ///< UART Word Length 7b 271 #define UART_CCR_CHAR_8b (0x03U << UART_CCR_CHAR_Pos) ///< UART Word Length 8b 272 273 #define UART_CCR_SPB1_Pos (6) 274 #define UART_CCR_SPB1 (0x01U << UART_CCR_SPB1_Pos) ///< Stop bit 1 selection 275 #define UART_CCR_B8RXD_Pos (7) 276 #define UART_CCR_B8RXD (0x01U << UART_CCR_B8RXD_Pos) ///< Synchronous frame receive 277 #define UART_CCR_B8TXD_Pos (8) 278 #define UART_CCR_B8TXD (0x01U << UART_CCR_B8TXD_Pos) ///< Synchronous frame transmit 279 #define UART_CCR_B8POL_Pos (9) 280 #define UART_CCR_B8POL (0x01U << UART_CCR_B8POL_Pos) ///< Synchronous frame polarity control bit 281 #define UART_CCR_B8TOG_Pos (10) 282 #define UART_CCR_B8TOG (0x01U << UART_CCR_B8TOG_Pos) ///< Synchronous frame auto toggle bit 283 #define UART_CCR_B8EN_Pos (11) 284 #define UART_CCR_B8EN (0x01U << UART_CCR_B8EN_Pos) ///< Synchronous frame enable bit 285 #define UART_CCR_RWU_Pos (12) 286 #define UART_CCR_RWU (0x01U << UART_CCR_RWU_Pos) ///< Receive wake up method 287 #define UART_CCR_WAKE_Pos (13) 288 #define UART_CCR_WAKE (0x01U << UART_CCR_WAKE_Pos) ///< Wake up method 289 290 #define UART_CCR_LIN_Pos (14) 291 #define UART_CCR_LIN (0x01U << UART_CCR_LIN_Pos) ///< Wake up method 292 293 //////////////////////////////////////////////////////////////////////////////// 294 /// @brief UART_BRR Register Bit Definition 295 //////////////////////////////////////////////////////////////////////////////// 296 #define UART_BRR_MANTISSA_Pos (0) 297 #define UART_BRR_MANTISSA (0xFFFFU << UART_BRR_MANTISSA_Pos) ///< UART DIV MANTISSA 298 299 //////////////////////////////////////////////////////////////////////////////// 300 /// @brief UART_FRA Register Bit Definition 301 //////////////////////////////////////////////////////////////////////////////// 302 #define UART_BRR_FRACTION_Pos (0) 303 #define UART_BRR_FRACTION (0x0FU << UART_BRR_FRACTION_Pos) ///< UART DIV FRACTION 304 305 //////////////////////////////////////////////////////////////////////////////// 306 /// @brief UART_RXAR Register Bit Definition 307 //////////////////////////////////////////////////////////////////////////////// 308 #define UART_RXAR_ADDR_Pos (0) 309 #define UART_RXAR_ADDR (0xFFU << UART_RXAR_ADDR_Pos) ///< Synchronous frame match address 310 311 //////////////////////////////////////////////////////////////////////////////// 312 /// @brief UART_RXMR Register Bit Definition 313 //////////////////////////////////////////////////////////////////////////////// 314 #define UART_RXMR_MASK_Pos (0) 315 #define UART_RXMR_MASK (0xFFU << UART_RXMR_MASK_Pos) ///< Synchronous frame match address mask 316 317 //////////////////////////////////////////////////////////////////////////////// 318 /// @brief UART_SCR Register Bit Definition 319 //////////////////////////////////////////////////////////////////////////////// 320 #define UART_SCR_SCEN_Pos (0) 321 #define UART_SCR_SCEN (0x01U << UART_SCR_SCEN_Pos) ///< ISO7816 enable bit 322 #define UART_SCR_SCARB_Pos (1) 323 #define UART_SCR_SCARB (0x01U << UART_SCR_SCARB_Pos) ///< ISO7816 check auto answer bit 324 #define UART_SCR_NACK_Pos (2) 325 #define UART_SCR_NACK (0x01U << UART_SCR_NACK_Pos) ///< Master receive frame answer bit 326 #define UART_SCR_SCFCNT_Pos (4) 327 #define UART_SCR_SCFCNT (0xFFU << UART_SCR_SCFCNT_Pos) ///< ISO7816 protection counter bit 328 #define UART_SCR_HDSEL_Pos (12) 329 #define UART_SCR_HDSEL (0x01U << UART_SCR_HDSEL_Pos) ///< Single-line half-duplex mode selection bit 330 //////////////////////////////////////////////////////////////////////////////// 331 /// @brief UART_ABRCR Register Bit Definition 332 //////////////////////////////////////////////////////////////////////////////// 333 #define UART_ABRCR_ABREN_Pos (0) 334 #define UART_ABRCR_ABREN (0x01U<<UART_ABRCR_ABREN_Pos) 335 #define UART_ABRCR_BITCNT_Pos (1) 336 #define UART_ABRCR_BITCNT (0x03U<<UART_ABRCR_BITCNT_Pos) 337 #define UART_ABRCR_BITCNT_MODE0 (0x00U<<UART_ABRCR_BITCNT_Pos) 338 #define UART_ABRCR_BITCNT_MODE1 (0x01U<<UART_ABRCR_BITCNT_Pos) 339 #define UART_ABRCR_BITCNT_MODE2 (0x02U<<UART_ABRCR_BITCNT_Pos) 340 #define UART_ABRCR_BITCNT_MODE3 (0x03U<<UART_ABRCR_BITCNT_Pos) 341 #define UART_ABRCR_FORMER_Pos (3) 342 #define UART_ABRCR_FORMER (0x01U<<UART_ABRCR_FORMER_Pos) 343 #define UART_ABRCR_LATTER_Pos (4) 344 #define UART_ABRCR_LATTER (0x01U<<UART_ABRCR_LATTER_Pos) 345 346 //////////////////////////////////////////////////////////////////////////////// 347 /// @brief UART_IDLR Register Bit Definition 348 //////////////////////////////////////////////////////////////////////////////// 349 #define UART_IDLR_IDLR_Pos (0) 350 #define UART_IDLR_IDLR (0xFFFFU << UART_IDLR_IDLR_Pos) ///< ISO7816 enable bit 351 352 353 354 /// @} 355 356 /// @} 357 358 /// @} 359 360 //////////////////////////////////////////////////////////////////////////////// 361 #endif 362 //////////////////////////////////////////////////////////////////////////////// 363