1 #ifndef _DRV_UART_H_ 2 #define _DRV_UART_H_ 3 4 #include <stdint.h> 5 6 #ifdef __cplusplus 7 extern "C" { 8 #endif 9 10 /** @name Register Map 11 * 12 * Registers of the UART. 13 * @{ 14 */ 15 typedef struct 16 { 17 volatile uint32_t CR; /**< Control Register */ 18 volatile uint32_t MR; /**< Mode Register */ 19 volatile uint32_t IER; /**< Interrupt Enable */ 20 volatile uint32_t IDR; /**< Interrupt Disable */ 21 volatile uint32_t IMR; /**< Interrupt Mask */ 22 volatile uint32_t ISR; /**< Interrupt Status */ 23 volatile uint32_t BAUDGEN; /**< Baud Rate Generator */ 24 volatile uint32_t RXTOUT; /**< RX Timeout */ 25 volatile uint32_t RXWM; /**< RX FIFO Trigger Level */ 26 volatile uint32_t MODEMCR; /**< Modem Control */ 27 volatile uint32_t MODEMSR; /**< Modem Status */ 28 volatile uint32_t SR; /**< Channel Status */ 29 volatile uint32_t FIFO; /**< FIFO */ 30 volatile uint32_t BAUDDIV; /**< Baud Rate Divider */ 31 volatile uint32_t FLOWDEL; /**< Flow Delay */ 32 volatile uint32_t RESERVED1; 33 volatile uint32_t RESERVED2; 34 volatile uint32_t TXWM; /* TX FIFO Trigger Level */ 35 } UART_Registers; 36 /* @} */ 37 38 /** @name Control Register 39 * 40 * The Control register (CR) controls the major functions of the device. 41 * 42 * Control Register Bit Definition 43 */ 44 #define UART_CR_STOPBRK 0x00000100 /**< Stop transmission of break */ 45 #define UART_CR_STARTBRK 0x00000080 /**< Set break */ 46 #define UART_CR_TORST 0x00000040 /**< RX timeout counter restart */ 47 #define UART_CR_TX_DIS 0x00000020 /**< TX disabled. */ 48 #define UART_CR_TX_EN 0x00000010 /**< TX enabled */ 49 #define UART_CR_RX_DIS 0x00000008 /**< RX disabled. */ 50 #define UART_CR_RX_EN 0x00000004 /**< RX enabled */ 51 #define UART_CR_EN_DIS_MASK 0x0000003C /**< Enable/disable Mask */ 52 #define UART_CR_TXRST 0x00000002 /**< TX logic reset */ 53 #define UART_CR_RXRST 0x00000001 /**< RX logic reset */ 54 /* @}*/ 55 56 /** @name Mode Register 57 * 58 * The mode register (MR) defines the mode of transfer as well as the data 59 * format. If this register is modified during transmission or reception, 60 * data validity cannot be guaranteed. 61 * 62 * Mode Register Bit Definition 63 * @{ 64 */ 65 #define UART_MR_CCLK 0x00000400 /**< Input clock selection */ 66 #define UART_MR_CHMODE_R_LOOP 0x00000300 /**< Remote loopback mode */ 67 #define UART_MR_CHMODE_L_LOOP 0x00000200 /**< Local loopback mode */ 68 #define UART_MR_CHMODE_ECHO 0x00000100 /**< Auto echo mode */ 69 #define UART_MR_CHMODE_NORM 0x00000000 /**< Normal mode */ 70 #define UART_MR_CHMODE_SHIFT 8 /**< Mode shift */ 71 #define UART_MR_CHMODE_MASK 0x00000300 /**< Mode mask */ 72 #define UART_MR_STOPMODE_2_BIT 0x00000080 /**< 2 stop bits */ 73 #define UART_MR_STOPMODE_1_5_BIT 0x00000040 /**< 1.5 stop bits */ 74 #define UART_MR_STOPMODE_1_BIT 0x00000000 /**< 1 stop bit */ 75 #define UART_MR_STOPMODE_SHIFT 6 /**< Stop bits shift */ 76 #define UART_MR_STOPMODE_MASK 0x000000A0 /**< Stop bits mask */ 77 #define UART_MR_PARITY_NONE 0x00000020 /**< No parity mode */ 78 #define UART_MR_PARITY_MARK 0x00000018 /**< Mark parity mode */ 79 #define UART_MR_PARITY_SPACE 0x00000010 /**< Space parity mode */ 80 #define UART_MR_PARITY_ODD 0x00000008 /**< Odd parity mode */ 81 #define UART_MR_PARITY_EVEN 0x00000000 /**< Even parity mode */ 82 #define UART_MR_PARITY_SHIFT 3 /**< Parity setting shift */ 83 #define UART_MR_PARITY_MASK 0x00000038 /**< Parity mask */ 84 #define UART_MR_CHARLEN_6_BIT 0x00000006 /**< 6 bits data */ 85 #define UART_MR_CHARLEN_7_BIT 0x00000004 /**< 7 bits data */ 86 #define UART_MR_CHARLEN_8_BIT 0x00000000 /**< 8 bits data */ 87 #define UART_MR_CHARLEN_SHIFT 1 /**< Data Length shift */ 88 #define UART_MR_CHARLEN_MASK 0x00000006 /**< Data length mask */ 89 #define UART_MR_CLKSEL 0x00000001 /**< Input clock selection */ 90 /* @} */ 91 92 /** @name Interrupt Registers 93 * 94 * Interrupt control logic uses the interrupt enable register (IER) and the 95 * interrupt disable register (IDR) to set the value of the bits in the 96 * interrupt mask register (IMR). The IMR determines whether to pass an 97 * interrupt to the interrupt status register (ISR). 98 * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an 99 * interrupt. IMR and ISR are read only, and IER and IDR are write only. 100 * Reading either IER or IDR returns 0x00. 101 * 102 * All four registers have the same bit definitions. 103 * 104 * @{ 105 */ 106 #define UART_IXR_DMS 0x00000200 /**< Modem status change interrupt */ 107 #define UART_IXR_TOUT 0x00000100 /**< Timeout error interrupt */ 108 #define UART_IXR_PARITY 0x00000080 /**< Parity error interrupt */ 109 #define UART_IXR_FRAMING 0x00000040 /**< Framing error interrupt */ 110 #define UART_IXR_OVER 0x00000020 /**< Overrun error interrupt */ 111 #define UART_IXR_TXFULL 0x00000010 /**< TX FIFO full interrupt. */ 112 #define UART_IXR_TXEMPTY 0x00000008 /**< TX FIFO empty interrupt. */ 113 #define UART_IXR_RXFULL 0x00000004 /**< RX FIFO full interrupt. */ 114 #define UART_IXR_RXEMPTY 0x00000002 /**< RX FIFO empty interrupt. */ 115 #define UART_IXR_RXOVR 0x00000001 /**< RX FIFO trigger interrupt. */ 116 #define UART_IXR_MASK 0x00003FFF /**< Valid bit mask */ 117 /* @} */ 118 119 /** @name Baud Rate Generator Register 120 * 121 * The baud rate generator control register (BRGR) is a 16 bit register that 122 * controls the receiver bit sample clock and baud rate. 123 * Valid values are 1 - 65535. 124 * 125 * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit 126 * in the MR register. 127 * @{ 128 */ 129 #define UART_BAUDGEN_DISABLE 0x00000000 /**< Disable clock */ 130 #define UART_BAUDGEN_MASK 0x0000FFFF /**< Valid bits mask */ 131 /* @} */ 132 133 /** @name Baud Divisor Rate register 134 * 135 * The baud rate divider register (BDIV) controls how much the bit sample 136 * rate is divided by. It sets the baud rate. 137 * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored. 138 * 139 * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by 140 * the MR_CCLK bit in the MR register. 141 * @{ 142 */ 143 #define UART_BAUDDIV_MASK 0x000000FF /**< 8 bit baud divider mask */ 144 /* @} */ 145 146 147 /** @name Receiver Timeout Register 148 * 149 * Use the receiver timeout register (RTR) to detect an idle condition on 150 * the receiver data line. 151 * 152 * @{ 153 */ 154 #define UART_RXTOUT_DISABLE 0x00000000 /**< Disable time out */ 155 #define UART_RXTOUT_MASK 0x000000FF /**< Valid bits mask */ 156 /* @} */ 157 158 /** @name Receiver FIFO Trigger Level Register 159 * 160 * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at 161 * which the RX FIFO triggers an interrupt event. 162 * @{ 163 */ 164 #define UART_RXWM_DISABLE 0x00000000 /**< Disable RX trigger interrupt */ 165 #define UART_RXWM_MASK 0x0000003F /**< Valid bits mask */ 166 /* @} */ 167 168 /** @name Modem Control Register 169 * 170 * This register (MODEMCR) controls the interface with the modem or data set, 171 * or a peripheral device emulating a modem. 172 * 173 * @{ 174 */ 175 #define UART_MODEMCR_FCM 0x00000010 /**< Flow control mode */ 176 #define UART_MODEMCR_RTS 0x00000002 /**< Request to send */ 177 #define UART_MODEMCR_DTR 0x00000001 /**< Data terminal ready */ 178 /* @} */ 179 180 /** @name Modem Status Register 181 * 182 * This register (MODEMSR) indicates the current state of the control lines 183 * from a modem, or another peripheral device, to the CPU. In addition, four 184 * bits of the modem status register provide change information. These bits 185 * are set to a logic 1 whenever a control input from the modem changes state. 186 * 187 * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem 188 * status interrupt is generated and this is reflected in the modem status 189 * register. 190 * 191 * @{ 192 */ 193 #define UART_MODEMSR_FCMS 0x00000100 /**< Flow control mode (FCMS) */ 194 #define UART_MODEMSR_DCD 0x00000080 /**< Complement of DCD input */ 195 #define UART_MODEMSR_RI 0x00000040 /**< Complement of RI input */ 196 #define UART_MODEMSR_DSR 0x00000020 /**< Complement of DSR input */ 197 #define UART_MODEMSR_CTS 0x00000010 /**< Complement of CTS input */ 198 #define UART_MEDEMSR_DCDX 0x00000008 /**< Delta DCD indicator */ 199 #define UART_MEDEMSR_RIX 0x00000004 /**< Change of RI */ 200 #define UART_MEDEMSR_DSRX 0x00000002 /**< Change of DSR */ 201 #define UART_MEDEMSR_CTSX 0x00000001 /**< Change of CTS */ 202 /* @} */ 203 204 /** @name Channel Status Register 205 * 206 * The channel status register (CSR) is provided to enable the control logic 207 * to monitor the status of bits in the channel interrupt status register, 208 * even if these are masked out by the interrupt mask register. 209 * 210 * @{ 211 */ 212 #define UART_SR_FLOWDEL 0x00001000 /**< RX FIFO fill over flow delay */ 213 #define UART_SR_TACTIVE 0x00000800 /**< TX active */ 214 #define UART_SR_RACTIVE 0x00000400 /**< RX active */ 215 #define UART_SR_DMS 0x00000200 /**< Delta modem status change */ 216 #define UART_SR_TOUT 0x00000100 /**< RX timeout */ 217 #define UART_SR_PARITY 0x00000080 /**< RX parity error */ 218 #define UART_SR_FRAME 0x00000040 /**< RX frame error */ 219 #define UART_SR_OVER 0x00000020 /**< RX overflow error */ 220 #define UART_SR_TXFULL 0x00000010 /**< TX FIFO full */ 221 #define UART_SR_TXEMPTY 0x00000008 /**< TX FIFO empty */ 222 #define UART_SR_RXFULL 0x00000004 /**< RX FIFO full */ 223 #define UART_SR_RXEMPTY 0x00000002 /**< RX FIFO empty */ 224 #define UART_SR_RXOVR 0x00000001 /**< RX FIFO fill over trigger */ 225 /* @} */ 226 227 /** @name Flow Delay Register 228 * 229 * Operation of the flow delay register (FLOWDEL) is very similar to the 230 * receive FIFO trigger register. An internal trigger signal activates when the 231 * FIFO is filled to the level set by this register. This trigger will not 232 * cause an interrupt, although it can be read through the channel status 233 * register. In hardware flow control mode, RTS is deactivated when the trigger 234 * becomes active. RTS only resets when the FIFO level is four less than the 235 * level of the flow delay trigger and the flow delay trigger is not activated. 236 * A value less than 4 disables the flow delay. 237 * @{ 238 */ 239 #define UART_FLOWDEL_MASK UART_RXWM_MASK /**< Valid bit mask */ 240 /* @} */ 241 242 243 /****************************************************************************/ 244 /** 245 * Determine if there is receive data in the receiver and/or FIFO. 246 * 247 * @param BaseAddress contains the base address of the device. 248 * 249 * @return TRUE if there is receive data, FALSE otherwise. 250 * 251 * @note C-Style signature: 252 * uint32_t UartDataReceived(uint32_t BaseAddress) 253 * 254 ******************************************************************************/ 255 #define UartDataReceived(BaseAddress) \ 256 !((__REG32((BaseAddress) + UART_SR_OFFSET) & \ 257 UART_SR_RXEMPTY) == UART_SR_RXEMPTY) 258 259 /****************************************************************************/ 260 /** 261 * Determine if a byte of data can be sent with the transmitter. 262 * 263 * @param BaseAddress contains the base address of the device. 264 * 265 * @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the 266 * FIFO. 267 * 268 * @note C-Style signature: 269 * uint32_t UartTXFIFOFull(uint32_t BaseAddress) 270 * 271 ******************************************************************************/ 272 #define UartTXFIFOFull(BaseAddress) \ 273 ((__REG32((BaseAddress) + UART_SR_OFFSET) & \ 274 UART_SR_TXFULL) == UART_SR_TXFULL) 275 276 #ifdef __cplusplus 277 } 278 #endif 279 280 #endif 281 282